stm8s_i2c.h 27 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm8s_i2c.h
  4. * @author MCD Application Team
  5. * @version V2.3.0
  6. * @date 16-June-2017
  7. * @brief This file contains all functions prototype and macros for the I2C peripheral.
  8. ******************************************************************************
  9. * @attention
  10. *
  11. * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
  12. *
  13. * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
  14. * You may not use this file except in compliance with the License.
  15. * You may obtain a copy of the License at:
  16. *
  17. * http://www.st.com/software_license_agreement_liberty_v2
  18. *
  19. * Unless required by applicable law or agreed to in writing, software
  20. * distributed under the License is distributed on an "AS IS" BASIS,
  21. * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  22. * See the License for the specific language governing permissions and
  23. * limitations under the License.
  24. *
  25. ******************************************************************************
  26. */
  27. /* Define to prevent recursive inclusion -------------------------------------*/
  28. #ifndef __STM8S_I2C_H
  29. #define __STM8S_I2C_H
  30. /* Includes ------------------------------------------------------------------*/
  31. #include "stm8s.h"
  32. /* Exported types ------------------------------------------------------------*/
  33. /** @addtogroup I2C_Exported_Types
  34. * @{
  35. */
  36. /**
  37. * @brief I2C duty cycle (fast mode only)
  38. */
  39. typedef enum
  40. {
  41. I2C_DUTYCYCLE_2 = (uint8_t)0x00, /*!< Fast mode Tlow/THigh = 2 */
  42. I2C_DUTYCYCLE_16_9 = (uint8_t)0x40 /*!< Fast mode Tlow/Thigh = 16/9 */
  43. } I2C_DutyCycle_TypeDef;
  44. /**
  45. * @brief I2C Acknowledgement configuration
  46. */
  47. typedef enum
  48. {
  49. I2C_ACK_NONE = (uint8_t)0x00, /*!< No acknowledge */
  50. I2C_ACK_CURR = (uint8_t)0x01, /*!< Acknowledge on the current byte */
  51. I2C_ACK_NEXT = (uint8_t)0x02 /*!< Acknowledge on the next byte */
  52. } I2C_Ack_TypeDef;
  53. /**
  54. * @brief I2C Addressing Mode (slave mode only)
  55. */
  56. typedef enum
  57. {
  58. I2C_ADDMODE_7BIT = (uint8_t)0x00, /*!< 7-bit slave address (10-bit address not acknowledged) */
  59. I2C_ADDMODE_10BIT = (uint8_t)0x80 /*!< 10-bit slave address (7-bit address not acknowledged) */
  60. } I2C_AddMode_TypeDef;
  61. /**
  62. * @brief I2C Interrupt sources
  63. * Warning: the values correspond to the bit position in the ITR register
  64. */
  65. typedef enum
  66. {
  67. I2C_IT_ERR = (uint8_t)0x01, /*!< Error Interruption */
  68. I2C_IT_EVT = (uint8_t)0x02, /*!< Event Interruption */
  69. I2C_IT_BUF = (uint8_t)0x04 /*!< Buffer Interruption */
  70. } I2C_IT_TypeDef;
  71. /**
  72. * @brief I2C transfer direction
  73. * Warning: the values correspond to the ADD0 bit position in the OARL register
  74. */
  75. typedef enum
  76. {
  77. I2C_DIRECTION_TX = (uint8_t)0x00, /*!< Transmission direction */
  78. I2C_DIRECTION_RX = (uint8_t)0x01 /*!< Reception direction */
  79. } I2C_Direction_TypeDef;
  80. /**
  81. * @brief I2C Flags
  82. * @brief Elements values convention: 0xXXYY
  83. * X = SRx registers index
  84. * X = 1 : SR1
  85. * X = 2 : SR2
  86. * X = 3 : SR3
  87. * Y = Flag mask in the register
  88. */
  89. typedef enum
  90. {
  91. /* SR1 register flags */
  92. I2C_FLAG_TXEMPTY = (uint16_t)0x0180, /*!< Transmit Data Register Empty flag */
  93. I2C_FLAG_RXNOTEMPTY = (uint16_t)0x0140, /*!< Read Data Register Not Empty flag */
  94. I2C_FLAG_STOPDETECTION = (uint16_t)0x0110, /*!< Stop detected flag */
  95. I2C_FLAG_HEADERSENT = (uint16_t)0x0108, /*!< 10-bit Header sent flag */
  96. I2C_FLAG_TRANSFERFINISHED = (uint16_t)0x0104, /*!< Data Byte Transfer Finished flag */
  97. I2C_FLAG_ADDRESSSENTMATCHED = (uint16_t)0x0102, /*!< Address Sent/Matched (master/slave) flag */
  98. I2C_FLAG_STARTDETECTION = (uint16_t)0x0101, /*!< Start bit sent flag */
  99. /* SR2 register flags */
  100. I2C_FLAG_WAKEUPFROMHALT = (uint16_t)0x0220, /*!< Wake Up From Halt Flag */
  101. I2C_FLAG_OVERRUNUNDERRUN = (uint16_t)0x0208, /*!< Overrun/Underrun flag */
  102. I2C_FLAG_ACKNOWLEDGEFAILURE = (uint16_t)0x0204, /*!< Acknowledge Failure Flag */
  103. I2C_FLAG_ARBITRATIONLOSS = (uint16_t)0x0202, /*!< Arbitration Loss Flag */
  104. I2C_FLAG_BUSERROR = (uint16_t)0x0201, /*!< Misplaced Start or Stop condition */
  105. /* SR3 register flags */
  106. I2C_FLAG_GENERALCALL = (uint16_t)0x0310, /*!< General Call header received Flag */
  107. I2C_FLAG_TRANSMITTERRECEIVER = (uint16_t)0x0304, /*!< Transmitter Receiver Flag */
  108. I2C_FLAG_BUSBUSY = (uint16_t)0x0302, /*!< Bus Busy Flag */
  109. I2C_FLAG_MASTERSLAVE = (uint16_t)0x0301 /*!< Master Slave Flag */
  110. } I2C_Flag_TypeDef;
  111. /**
  112. * @brief I2C Pending bits
  113. * Elements values convention: 0xXYZZ
  114. * X = SRx registers index
  115. * X = 1 : SR1
  116. * X = 2 : SR2
  117. * Y = Position of the corresponding Interrupt
  118. * ZZ = flag mask in the dedicated register(X register)
  119. */
  120. typedef enum
  121. {
  122. /* SR1 register flags */
  123. I2C_ITPENDINGBIT_TXEMPTY = (uint16_t)0x1680, /*!< Transmit Data Register Empty */
  124. I2C_ITPENDINGBIT_RXNOTEMPTY = (uint16_t)0x1640, /*!< Read Data Register Not Empty */
  125. I2C_ITPENDINGBIT_STOPDETECTION = (uint16_t)0x1210, /*!< Stop detected */
  126. I2C_ITPENDINGBIT_HEADERSENT = (uint16_t)0x1208, /*!< 10-bit Header sent */
  127. I2C_ITPENDINGBIT_TRANSFERFINISHED = (uint16_t)0x1204, /*!< Data Byte Transfer Finished */
  128. I2C_ITPENDINGBIT_ADDRESSSENTMATCHED = (uint16_t)0x1202, /*!< Address Sent/Matched (master/slave) */
  129. I2C_ITPENDINGBIT_STARTDETECTION = (uint16_t)0x1201, /*!< Start bit sent */
  130. /* SR2 register flags */
  131. I2C_ITPENDINGBIT_WAKEUPFROMHALT = (uint16_t)0x2220, /*!< Wake Up From Halt */
  132. I2C_ITPENDINGBIT_OVERRUNUNDERRUN = (uint16_t)0x2108, /*!< Overrun/Underrun */
  133. I2C_ITPENDINGBIT_ACKNOWLEDGEFAILURE = (uint16_t)0x2104, /*!< Acknowledge Failure */
  134. I2C_ITPENDINGBIT_ARBITRATIONLOSS = (uint16_t)0x2102, /*!< Arbitration Loss */
  135. I2C_ITPENDINGBIT_BUSERROR = (uint16_t)0x2101 /*!< Misplaced Start or Stop condition */
  136. } I2C_ITPendingBit_TypeDef;
  137. /**
  138. * @brief I2C possible events
  139. * Values convention: 0xXXYY
  140. * XX = Event SR3 corresponding value
  141. * YY = Event SR1 corresponding value
  142. * @note if Event = EV3_2 the rule above does not apply
  143. * YY = Event SR2 corresponding value
  144. */
  145. typedef enum
  146. {
  147. /*========================================
  148. I2C Master Events (Events grouped in order of communication)
  149. ==========================================*/
  150. /**
  151. * @brief Communication start
  152. *
  153. * After sending the START condition (I2C_GenerateSTART() function) the master
  154. * has to wait for this event. It means that the Start condition has been correctly
  155. * released on the I2C bus (the bus is free, no other devices is communicating).
  156. *
  157. */
  158. /* --EV5 */
  159. I2C_EVENT_MASTER_MODE_SELECT = (uint16_t)0x0301, /*!< BUSY, MSL and SB flag */
  160. /**
  161. * @brief Address Acknowledge
  162. *
  163. * After checking on EV5 (start condition correctly released on the bus), the
  164. * master sends the address of the slave(s) with which it will communicate
  165. * (I2C_Send7bitAddress() function, it also determines the direction of the communication:
  166. * Master transmitter or Receiver).
  167. * Then the master has to wait that a slave acknowledges his address.
  168. * If an acknowledge is sent on the bus, one of the following events will
  169. * be set:
  170. *
  171. * 1) In case of Master Receiver (7-bit addressing):
  172. * the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED event is set.
  173. *
  174. * 2) In case of Master Transmitter (7-bit addressing):
  175. * the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED is set
  176. *
  177. * 3) In case of 10-Bit addressing mode, the master (just after generating the START
  178. * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()
  179. * function).
  180. * Then master should wait on EV9. It means that the 10-bit addressing
  181. * header has been correctly sent on the bus.
  182. * Then master should send the second part of the 10-bit address (LSB) using
  183. * the function I2C_Send7bitAddress(). Then master should wait for event EV6.
  184. *
  185. */
  186. /* --EV6 */
  187. I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED = (uint16_t)0x0782, /*!< BUSY, MSL, ADDR, TXE and TRA flags */
  188. I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED = (uint16_t)0x0302, /*!< BUSY, MSL and ADDR flags */
  189. /* --EV9 */
  190. I2C_EVENT_MASTER_MODE_ADDRESS10 = (uint16_t)0x0308, /*!< BUSY, MSL and ADD10 flags */
  191. /**
  192. * @brief Communication events
  193. *
  194. * If a communication is established (START condition generated and slave address
  195. * acknowledged) then the master has to check on one of the following events for
  196. * communication procedures:
  197. *
  198. * 1) Master Receiver mode: The master has to wait on the event EV7 then to read
  199. * the data received from the slave (I2C_ReceiveData() function).
  200. *
  201. * 2) Master Transmitter mode: The master has to send data (I2C_SendData()
  202. * function) then to wait on event EV8 or EV8_2.
  203. * These two events are similar:
  204. * - EV8 means that the data has been written in the data register and is
  205. * being shifted out.
  206. * - EV8_2 means that the data has been physically shifted out and output
  207. * on the bus.
  208. * In most cases, using EV8 is sufficient for the application.
  209. * Using EV8_2 leads to a slower communication but ensures more reliable test.
  210. * EV8_2 is also more suitable than EV8 for testing on the last data transmission
  211. * (before Stop condition generation).
  212. *
  213. * @note In case the user software does not guarantee that this event EV7 is
  214. * managed before the current byte end of transfer, then user may check on EV7
  215. * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
  216. * In this case the communication may be slower.
  217. *
  218. */
  219. /* Master RECEIVER mode -----------------------------*/
  220. /* --EV7 */
  221. I2C_EVENT_MASTER_BYTE_RECEIVED = (uint16_t)0x0340, /*!< BUSY, MSL and RXNE flags */
  222. /* Master TRANSMITTER mode --------------------------*/
  223. /* --EV8 */
  224. I2C_EVENT_MASTER_BYTE_TRANSMITTING = (uint16_t)0x0780, /*!< TRA, BUSY, MSL, TXE flags */
  225. /* --EV8_2 */
  226. I2C_EVENT_MASTER_BYTE_TRANSMITTED = (uint16_t)0x0784, /*!< EV8_2: TRA, BUSY, MSL, TXE and BTF flags */
  227. /*========================================
  228. I2C Slave Events (Events grouped in order of communication)
  229. ==========================================*/
  230. /**
  231. * @brief Communication start events
  232. *
  233. * Wait on one of these events at the start of the communication. It means that
  234. * the I2C peripheral detected a Start condition on the bus (generated by master
  235. * device) followed by the peripheral address.
  236. * The peripheral generates an ACK condition on the bus (if the acknowledge
  237. * feature is enabled through function I2C_AcknowledgeConfig()) and the events
  238. * listed above are set :
  239. *
  240. * 1) In normal case (only one address managed by the slave), when the address
  241. * sent by the master matches the own address of the peripheral (configured by
  242. * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
  243. * (where XXX could be TRANSMITTER or RECEIVER).
  244. *
  245. * 2) In case the address sent by the master is General Call (address 0x00) and
  246. * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
  247. * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
  248. *
  249. */
  250. /* --EV1 (all the events below are variants of EV1) */
  251. /* 1) Case of One Single Address managed by the slave */
  252. I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED = (uint16_t)0x0202, /*!< BUSY and ADDR flags */
  253. I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED = (uint16_t)0x0682, /*!< TRA, BUSY, TXE and ADDR flags */
  254. /* 2) Case of General Call enabled for the slave */
  255. I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED = (uint16_t)0x1200, /*!< EV2: GENCALL and BUSY flags */
  256. /**
  257. * @brief Communication events
  258. *
  259. * Wait on one of these events when EV1 has already been checked :
  260. *
  261. * - Slave RECEIVER mode:
  262. * - EV2: When the application is expecting a data byte to be received.
  263. * - EV4: When the application is expecting the end of the communication:
  264. * master sends a stop condition and data transmission is stopped.
  265. *
  266. * - Slave Transmitter mode:
  267. * - EV3: When a byte has been transmitted by the slave and the application
  268. * is expecting the end of the byte transmission.
  269. * The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and I2C_EVENT_SLAVE_BYTE_TRANSMITTING
  270. * are similar. The second one can optionally be used when the user software
  271. * doesn't guarantee the EV3 is managed before the current byte end of transfer.
  272. * - EV3_2: When the master sends a NACK in order to tell slave that data transmission
  273. * shall end (before sending the STOP condition).
  274. * In this case slave has to stop sending data bytes and expect a Stop
  275. * condition on the bus.
  276. *
  277. * @note In case the user software does not guarantee that the event EV2 is
  278. * managed before the current byte end of transfer, then user may check on EV2
  279. * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
  280. * In this case the communication may be slower.
  281. *
  282. */
  283. /* Slave RECEIVER mode --------------------------*/
  284. /* --EV2 */
  285. I2C_EVENT_SLAVE_BYTE_RECEIVED = (uint16_t)0x0240, /*!< BUSY and RXNE flags */
  286. /* --EV4 */
  287. I2C_EVENT_SLAVE_STOP_DETECTED = (uint16_t)0x0010, /*!< STOPF flag */
  288. /* Slave TRANSMITTER mode -----------------------*/
  289. /* --EV3 */
  290. I2C_EVENT_SLAVE_BYTE_TRANSMITTED = (uint16_t)0x0684, /*!< TRA, BUSY, TXE and BTF flags */
  291. I2C_EVENT_SLAVE_BYTE_TRANSMITTING = (uint16_t)0x0680, /*!< TRA, BUSY and TXE flags */
  292. /* --EV3_2 */
  293. I2C_EVENT_SLAVE_ACK_FAILURE = (uint16_t)0x0004 /*!< AF flag */
  294. } I2C_Event_TypeDef;
  295. /**
  296. * @}
  297. */
  298. /* Exported constants --------------------------------------------------------*/
  299. /** @addtogroup I2C_Exported_Constants
  300. * @{
  301. */
  302. #define I2C_MAX_STANDARD_FREQ ((uint32_t)100000)
  303. #define I2C_MAX_FAST_FREQ ((uint32_t)400000)
  304. #if defined(STM8S208) || defined(STM8S207) || defined(STM8S007)
  305. #define I2C_MAX_INPUT_FREQ ((uint8_t)24)
  306. #else
  307. #define I2C_MAX_INPUT_FREQ ((uint8_t)16)
  308. #endif
  309. /**
  310. * @}
  311. */
  312. /* Exported macros -----------------------------------------------------------*/
  313. /* Private macros ------------------------------------------------------------*/
  314. /** @addtogroup I2C_Private_Macros
  315. * @{
  316. */
  317. /**
  318. * @brief Macro used by the assert function to check the different functions parameters.
  319. */
  320. /**
  321. * @brief Macro used by the assert function to check the different I2C duty cycles.
  322. */
  323. #define IS_I2C_DUTYCYCLE_OK(DUTY) \
  324. (((DUTY) == I2C_DUTYCYCLE_2) || \
  325. ((DUTY) == I2C_DUTYCYCLE_16_9))
  326. /**
  327. * @brief Macro used by the assert function to check the different acknowledgement configuration
  328. */
  329. #define IS_I2C_ACK_OK(ACK) \
  330. (((ACK) == I2C_ACK_NONE) || \
  331. ((ACK) == I2C_ACK_CURR) || \
  332. ((ACK) == I2C_ACK_NEXT))
  333. /**
  334. * @brief Macro used by the assert function to check the different I2C addressing modes.
  335. */
  336. #define IS_I2C_ADDMODE_OK(ADDMODE) \
  337. (((ADDMODE) == I2C_ADDMODE_7BIT) || \
  338. ((ADDMODE) == I2C_ADDMODE_10BIT))
  339. /**
  340. * @brief Macro used by the assert function to check the different I2C interrupt types.
  341. */
  342. #define IS_I2C_INTERRUPT_OK(IT) \
  343. (((IT) == I2C_IT_ERR) || \
  344. ((IT) == I2C_IT_EVT) || \
  345. ((IT) == I2C_IT_BUF) || \
  346. ((IT) == (I2C_IT_ERR | I2C_IT_EVT)) || \
  347. ((IT) == (I2C_IT_ERR | I2C_IT_BUF)) || \
  348. ((IT) == (I2C_IT_EVT | I2C_IT_BUF)) || \
  349. ((IT) == (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR)))
  350. /**
  351. * @brief Macro used by the assert function to check the different I2C communcation direction.
  352. */
  353. #define IS_I2C_DIRECTION_OK(DIR) \
  354. (((DIR) == I2C_DIRECTION_TX) || \
  355. ((DIR) == I2C_DIRECTION_RX))
  356. /**
  357. * @brief Macro used by the assert function to check the different I2C flags.
  358. */
  359. #define IS_I2C_FLAG_OK(FLAG) \
  360. (((FLAG) == I2C_FLAG_TXEMPTY) || \
  361. ((FLAG) == I2C_FLAG_RXNOTEMPTY) || \
  362. ((FLAG) == I2C_FLAG_STOPDETECTION) || \
  363. ((FLAG) == I2C_FLAG_HEADERSENT) || \
  364. ((FLAG) == I2C_FLAG_TRANSFERFINISHED) || \
  365. ((FLAG) == I2C_FLAG_ADDRESSSENTMATCHED) || \
  366. ((FLAG) == I2C_FLAG_STARTDETECTION) || \
  367. ((FLAG) == I2C_FLAG_WAKEUPFROMHALT) || \
  368. ((FLAG) == I2C_FLAG_OVERRUNUNDERRUN) || \
  369. ((FLAG) == I2C_FLAG_ACKNOWLEDGEFAILURE) || \
  370. ((FLAG) == I2C_FLAG_ARBITRATIONLOSS) || \
  371. ((FLAG) == I2C_FLAG_BUSERROR) || \
  372. ((FLAG) == I2C_FLAG_GENERALCALL) || \
  373. ((FLAG) == I2C_FLAG_TRANSMITTERRECEIVER) || \
  374. ((FLAG) == I2C_FLAG_BUSBUSY) || \
  375. ((FLAG) == I2C_FLAG_MASTERSLAVE))
  376. /**
  377. * @brief Macro used by the assert function to check the I2C flags to clear.
  378. */
  379. #define IS_I2C_CLEAR_FLAG_OK(FLAG) ((((uint16_t)(FLAG) & (uint16_t)0xFD00) == 0x00) \
  380. && ((uint16_t)(FLAG) != 0x00))
  381. /**
  382. * @brief Macro used by the assert function to check the different I2C possible pending bits.
  383. */
  384. #define IS_I2C_ITPENDINGBIT_OK(ITPENDINGBIT) \
  385. (((ITPENDINGBIT) == I2C_ITPENDINGBIT_TXEMPTY) || \
  386. ((ITPENDINGBIT) == I2C_ITPENDINGBIT_RXNOTEMPTY) || \
  387. ((ITPENDINGBIT) == I2C_ITPENDINGBIT_STOPDETECTION) || \
  388. ((ITPENDINGBIT) == I2C_ITPENDINGBIT_HEADERSENT) || \
  389. ((ITPENDINGBIT) == I2C_ITPENDINGBIT_TRANSFERFINISHED) || \
  390. ((ITPENDINGBIT) == I2C_ITPENDINGBIT_ADDRESSSENTMATCHED) || \
  391. ((ITPENDINGBIT) == I2C_ITPENDINGBIT_STARTDETECTION) || \
  392. ((ITPENDINGBIT) == I2C_ITPENDINGBIT_WAKEUPFROMHALT) || \
  393. ((ITPENDINGBIT) == I2C_ITPENDINGBIT_OVERRUNUNDERRUN) || \
  394. ((ITPENDINGBIT) == I2C_ITPENDINGBIT_ACKNOWLEDGEFAILURE) || \
  395. ((ITPENDINGBIT) == I2C_ITPENDINGBIT_ARBITRATIONLOSS) || \
  396. ((ITPENDINGBIT) == I2C_ITPENDINGBIT_BUSERROR))
  397. /**
  398. * @brief Macro used by the assert function to check the different I2C possible
  399. * pending bits to clear by writing 0.
  400. */
  401. #define IS_I2C_CLEAR_ITPENDINGBIT_OK(ITPENDINGBIT) \
  402. (((ITPENDINGBIT) == I2C_ITPENDINGBIT_WAKEUPFROMHALT) || \
  403. ((ITPENDINGBIT) == I2C_ITPENDINGBIT_OVERRUNUNDERRUN) || \
  404. ((ITPENDINGBIT) == I2C_ITPENDINGBIT_ACKNOWLEDGEFAILURE) || \
  405. ((ITPENDINGBIT) == I2C_ITPENDINGBIT_ARBITRATIONLOSS) || \
  406. ((ITPENDINGBIT) == I2C_ITPENDINGBIT_BUSERROR))
  407. /**
  408. * @brief Macro used by the assert function to check the different I2C possible events.
  409. */
  410. #define IS_I2C_EVENT_OK(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
  411. ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
  412. ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
  413. ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
  414. ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | (uint16_t)I2C_FLAG_GENERALCALL)) || \
  415. ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
  416. ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | (uint16_t)I2C_FLAG_GENERALCALL)) || \
  417. ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE) || \
  418. ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
  419. ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
  420. ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
  421. ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
  422. ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
  423. ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
  424. ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
  425. ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10))
  426. /**
  427. * @brief Macro used by the assert function to check the different I2C possible own address.
  428. */
  429. #define IS_I2C_OWN_ADDRESS_OK(ADDRESS) \
  430. ((ADDRESS) <= (uint16_t)0x03FF)
  431. /* The address must be even */
  432. #define IS_I2C_ADDRESS_OK(ADD) \
  433. (((ADD) & (uint8_t)0x01) == (uint8_t)0x00)
  434. /**
  435. * @brief Macro used by the assert function to check that I2C Input clock frequency must be between 1MHz and 50MHz.
  436. */
  437. #define IS_I2C_INPUT_CLOCK_FREQ_OK(FREQ) \
  438. (((FREQ) >= (uint8_t)1) && ((FREQ) <= I2C_MAX_INPUT_FREQ))
  439. /**
  440. * @brief Macro used by the assert function to check that I2C Output clock frequency must be between 1Hz and 400kHz.
  441. */
  442. #define IS_I2C_OUTPUT_CLOCK_FREQ_OK(FREQ) \
  443. (((FREQ) >= (uint8_t)1) && ((FREQ) <= I2C_MAX_FAST_FREQ))
  444. /**
  445. * @}
  446. */
  447. /* Exported functions ------------------------------------------------------- */
  448. /** @addtogroup I2C_Exported_Functions
  449. * @{
  450. */
  451. void I2C_DeInit(void);
  452. void I2C_Init(uint32_t OutputClockFrequencyHz, uint16_t OwnAddress,
  453. I2C_DutyCycle_TypeDef I2C_DutyCycle, I2C_Ack_TypeDef Ack,
  454. I2C_AddMode_TypeDef AddMode, uint8_t InputClockFrequencyMHz );
  455. void I2C_Cmd(FunctionalState NewState);
  456. void I2C_GeneralCallCmd(FunctionalState NewState);
  457. void I2C_GenerateSTART(FunctionalState NewState);
  458. void I2C_GenerateSTOP(FunctionalState NewState);
  459. void I2C_SoftwareResetCmd(FunctionalState NewState);
  460. void I2C_StretchClockCmd(FunctionalState NewState);
  461. void I2C_AcknowledgeConfig(I2C_Ack_TypeDef Ack);
  462. void I2C_FastModeDutyCycleConfig(I2C_DutyCycle_TypeDef I2C_DutyCycle);
  463. void I2C_ITConfig(I2C_IT_TypeDef I2C_IT, FunctionalState NewState);
  464. uint8_t I2C_ReceiveData(void);
  465. void I2C_Send7bitAddress(uint8_t Address, I2C_Direction_TypeDef Direction);
  466. void I2C_SendData(uint8_t Data);
  467. /**
  468. * @brief
  469. ****************************************************************************************
  470. *
  471. * I2C State Monitoring Functions
  472. *
  473. ****************************************************************************************
  474. * This I2C driver provides three different ways for I2C state monitoring
  475. * depending on the application requirements and constraints:
  476. *
  477. *
  478. * 1) Basic state monitoring:
  479. * Using I2C_CheckEvent() function:
  480. * It compares the status registers (SR1, SR2 and SR3) content to a given event
  481. * (can be the combination of one or more flags).
  482. * It returns SUCCESS if the current status includes the given flags
  483. * and returns ERROR if one or more flags are missing in the current status.
  484. * - When to use:
  485. * - This function is suitable for most applications as well as for startup
  486. * activity since the events are fully described in the product reference manual
  487. * (RM0016).
  488. * - It is also suitable for users who need to define their own events.
  489. * - Limitations:
  490. * - If an error occurs (ie. error flags are set besides to the monitored flags),
  491. * the I2C_CheckEvent() function may return SUCCESS despite the communication
  492. * hold or corrupted real state.
  493. * In this case, it is advised to use error interrupts to monitor the error
  494. * events and handle them in the interrupt IRQ handler.
  495. *
  496. * @note
  497. * For error management, it is advised to use the following functions:
  498. * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
  499. * - I2C_IRQHandler() which is called when the I2C interrupts occur.
  500. * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the
  501. * I2Cx_IRQHandler() function in order to determine which error occurred.
  502. * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
  503. * and/or I2C_GenerateStop() in order to clear the error flag and
  504. * source and return to correct communication status.
  505. *
  506. *
  507. * 2) Advanced state monitoring:
  508. * Using the function I2C_GetLastEvent() which returns the image of both SR1
  509. * & SR3 status registers in a single word (uint16_t) (Status Register 3 value
  510. * is shifted left by 8 bits and concatenated to Status Register 1).
  511. * - When to use:
  512. * - This function is suitable for the same applications above but it allows to
  513. * overcome the limitations of I2C_GetFlagStatus() function (see below).
  514. * The returned value could be compared to events already defined in the
  515. * library (stm8s_i2c.h) or to custom values defined by user.
  516. * - This function is suitable when multiple flags are monitored at the same time.
  517. * - At the opposite of I2C_CheckEvent() function, this function allows user to
  518. * choose when an event is accepted (when all events flags are set and no
  519. * other flags are set or just when the needed flags are set like
  520. * I2C_CheckEvent() function).
  521. * - Limitations:
  522. * - User may need to define his own events.
  523. * - Same remark concerning the error management is applicable for this
  524. * function if user decides to check only regular communication flags (and
  525. * ignores error flags).
  526. *
  527. *
  528. * 3) Flag-based state monitoring:
  529. * Using the function I2C_GetFlagStatus() which simply returns the status of
  530. * one single flag (ie. I2C_FLAG_RXNE ...).
  531. * - When to use:
  532. * - This function could be used for specific applications or in debug phase.
  533. * - It is suitable when only one flag checking is needed (most I2C events
  534. * are monitored through multiple flags).
  535. * - Limitations:
  536. * - When calling this function, the Status register is accessed. Some flags are
  537. * cleared when the status register is accessed. So checking the status
  538. * of one Flag, may clear other ones.
  539. * - Function may need to be called twice or more in order to monitor one
  540. * single event.
  541. *
  542. */
  543. /**
  544. *
  545. * 1) Basic state monitoring
  546. *******************************************************************************
  547. */
  548. ErrorStatus I2C_CheckEvent(I2C_Event_TypeDef I2C_Event);
  549. /**
  550. *
  551. * 2) Advanced state monitoring
  552. *******************************************************************************
  553. */
  554. I2C_Event_TypeDef I2C_GetLastEvent(void);
  555. /**
  556. *
  557. * 3) Flag-based state monitoring
  558. *******************************************************************************
  559. */
  560. FlagStatus I2C_GetFlagStatus(I2C_Flag_TypeDef I2C_Flag);
  561. /**
  562. *
  563. *******************************************************************************
  564. */
  565. void I2C_ClearFlag(I2C_Flag_TypeDef I2C_FLAG);
  566. ITStatus I2C_GetITStatus(I2C_ITPendingBit_TypeDef I2C_ITPendingBit);
  567. void I2C_ClearITPendingBit(I2C_ITPendingBit_TypeDef I2C_ITPendingBit);
  568. /**
  569. * @}
  570. */
  571. #endif /* __STM8S_I2C_H */
  572. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/