TipsAndTriks/stm32/rcc.c

/**
  * Тактирование STM32
  * http://avr-start.ru/?p=3709
  */

/* Для внешнего кварца: */

  RCC->CR|=RCC_CR_HSEON; //Запускаем генератор HSE.
  while (!(RCC->CR & RCC_CR_HSERDY)) {}; // Ждем готовности
  RCC->CFGR &=~RCC_CFGR_SW; //Сбрасываем биты
  RCC->CFGR |= RCC_CFGR_SW_HSE; // Переходим на HSE


/* Для внутреннего PLL */

  RCC->CFGR |= RCC_CFGR_PLLMULL6;               //HSI / 2 * 6 = 24 MHz
  RCC->CR |= RCC_CR_PLLON;                      //enable PLL
  while((RCC->CR & RCC_CR_PLLRDY) == 0) {}      //wait till PLL is ready
  RCC->CFGR &= ~RCC_CFGR_SW;                    //clear SW bits
  RCC->CFGR |= RCC_CFGR_SW_PLL;                 //select PLL as system clock
  while((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_1) {} //wait till PLL is used


/* Для внешнего PLL */

  RCC->CR |= RCC_CR_HSEON;                      //enable HSE
  while((RCC->CR & RCC_CR_HSERDY) == 0) {}      //wait till HSE is ready
  RCC->CFGR |= RCC_CFGR_HPRE_DIV1  |            //HCLK = SYSCLK
               RCC_CFGR_PPRE2_DIV1 |            //PCLK2 = HCLK
               RCC_CFGR_PPRE1_DIV1;             //PCLK1 = HCLK
  RCC->CFGR &= ~RCC_CFGR_PLLMULL;               //clear PLLMULL bits
  RCC->CFGR |= RCC_CFGR_PLLSRC_PREDIV1 |        //PLL source = PREDIV1
               RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | //HSE / 2 = 4 MHz
               RCC_CFGR_PLLMULL6;               //4 * 6 = 24 MHz
  RCC->CR |= RCC_CR_PLLON;                      //enable PLL
  while((RCC->CR & RCC_CR_PLLRDY) == 0) {}      //wait till PLL is ready
  RCC->CFGR &= ~RCC_CFGR_SW;                    //clear SW bits
  RCC->CFGR |= RCC_CFGR_SW_PLL;                 //select PLL as system clock
  while((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_1) {} //wait till PLL is used