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+/**
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+ ******************************************************************************
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+ * @file i2c_master_poll.c
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+ * @author MCD Application Team
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+ * @version V0.0.3
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+ * @date Oct 2010
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+ * @brief This file contains optimized drivers for I2C master
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+ ******************************************************************************
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+ * @copy
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+ *
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+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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+ *
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+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
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+ */
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+
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+#include "i2c_master_poll.h"
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+
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+/* Таймаут ожидания события I2C */
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+extern __IO uint8_t I2C_timeout;
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+
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+/* flag clearing sequence - uncoment next for peripheral clock under 2MHz */
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+#define dead_time() { /* _asm("nop"); _asm("nop"); */ }
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+#define tout() (I2C_timeout)
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+#define set_tout_ms(a) { I2C_timeout = a; }
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+
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+/******************************************************************************
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+* Function name : I2C_Init
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+* Description : Initialize I2C peripheral
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+* Input param : None
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+* Return : None
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+* See also : None
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+*******************************************************************************/
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+void I2C_Init(void) {
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+ //define SDA, SCL outputs, HiZ, Open drain, Fast
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+ GPIOB->ODR |= (GPIO_PIN_4 | GPIO_PIN_5);
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+ GPIOB->DDR |= (GPIO_PIN_4 | GPIO_PIN_5);
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+ GPIOB->CR2 |= (GPIO_PIN_4 | GPIO_PIN_5);
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+
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+#ifdef FAST_I2C_MODE
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+ I2C->FREQR = 16; // input clock to I2C - 16MHz
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+ I2C->CCRL = 15; // 900/62.5= 15, (SCLhi must be at least 600+300=900ns!)
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+ I2C->CCRH = 0x80; // fast mode, duty 2/1 (bus speed 62.5*3*15~356kHz)
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+ I2C->TRISER = 5; // 300/62.5 + 1= 5 (maximum 300ns)
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+#else
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+ I2C->FREQR = 8; // input clock to I2C - 8MHz
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+ I2C->CCRL = 40; // CCR= 40 - (SCLhi must be at least 4000+1000=5000ns!)
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+ I2C->CCRH = 0; // standard mode, duty 1/1 bus speed 100kHz
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+ I2C->TRISER = 9; // 1000ns/(125ns) + 1 (maximum 1000ns)
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+#endif
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+ I2C->OARL = 0xA0; // own address A0;
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+ I2C->OARH |= 0x40;
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+ I2C->ITR = 1; // enable error interrupts
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+ I2C->CR2 |= 0x04; // ACK=1, Ack enable
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+ I2C->CR1 |= 0x01; // PE=1
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+}
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+
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+/******************************************************************************
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+* Function name : I2C_ReadRegister
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+* Description : Read defined number bytes from slave memory starting with defined offset
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+* Input param : offset in slave memory, number of bytes to read, starting address to store received data
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+* Return : None
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+* See also : None
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+*******************************************************************************/
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+void I2C_ReadRegister(u8 u8_regAddr, u8 u8_NumByteToRead, u8 *ReadBuffer)
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+{
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+ /*--------------- BUSY? -> STOP request ---------------------*/
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+ while(I2C->SR3 & I2C_SR3_BUSY && tout()) // Wait while the bus is busy
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+ {
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+ I2C->CR2 |= I2C_CR2_STOP; // Generate stop here (STOP=1)
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+ while(I2C->CR2 & I2C_CR2_STOP && tout()); // Wait until stop is performed
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+ }
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+ I2C->CR2 |= I2C_CR2_ACK; // ACK=1, Ack enable
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+ /*--------------- Start communication -----------------------*/
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+ I2C->CR2 |= I2C_CR2_START; // START=1, generate start
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+ while((I2C->SR1 & I2C_SR1_SB)==0 && tout()); // Wait for start bit detection (SB)
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+ /*------------------ Address send ---------------------------*/
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+ if(tout())
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+ {
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+ I2C->DR = (u8)(SLAVE_ADDRESS << 1); // Send 7-bit device address & Write (R/W = 0)
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+ }
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+ while(!(I2C->SR1 & I2C_SR1_ADDR) && tout()); // test EV6 - wait for address ack (ADDR)
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+ dead_time(); // ADDR clearing sequence
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+ I2C->SR3;
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+ /*--------------- Register/Command send ----------------------*/
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+ while(!(I2C->SR1 & I2C_SR1_TXE) && tout()); // Wait for TxE
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+ if(tout())
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+ {
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+ I2C->DR = u8_regAddr; // Send register address
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+ } // Wait for TxE & BTF
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+ while((I2C->SR1 & (I2C_SR1_TXE | I2C_SR1_BTF)) != (I2C_SR1_TXE | I2C_SR1_BTF) && tout());
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+ dead_time(); // clearing sequence
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+ /*-------------- Stop/Restart communication -------------------*/
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+ #ifdef NO_RESTART // if 7bit address and NO_RESTART setted
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+ I2C->CR2 |= I2C_CR2_STOP; // STOP=1, generate stop
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+ while(I2C->CR2 & I2C_CR2_STOP && tout()); // wait until stop is performed
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+ #endif // NO_RESTART
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+ /*--------------- Restart communication ---------------------*/
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+ I2C->CR2 |= I2C_CR2_START; // START=1, generate re-start
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+ while((I2C->SR1 & I2C_SR1_SB)==0 && tout()); // Wait for start bit detection (SB)
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+ /*------------------ Address send ---------------------------*/
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+ if(tout())
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+ {
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+ I2C->DR = (u8)(SLAVE_ADDRESS << 1) | 1; // Send 7-bit device address & Write (R/W = 1)
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+ }
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+ while(!(I2C->SR1 & I2C_SR1_ADDR) && tout()); // Wait for address ack (ADDR)
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+ /*------------------- Data Receive --------------------------*/
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+ if (u8_NumByteToRead > 2) // *** more than 2 bytes are received? ***
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+ {
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+ I2C->SR3; // ADDR clearing sequence
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+ while(u8_NumByteToRead > 3 && tout()) // not last three bytes?
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+ {
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+ while(!(I2C->SR1 & I2C_SR1_BTF) && tout()); // Wait for BTF
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+ *ReadBuffer++ = I2C->DR; // Reading next data byte
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+ --u8_NumByteToRead; // Decrease Numbyte to reade by 1
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+ }
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+ //last three bytes should be read
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+ while(!(I2C->SR1 & I2C_SR1_BTF) && tout()); // Wait for BTF
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+ I2C->CR2 &=~I2C_CR2_ACK; // Clear ACK
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+ disableInterrupts(); // Errata workaround (Disable interrupt)
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+ *ReadBuffer++ = I2C->DR; // Read 1st byte
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+ I2C->CR2 |= I2C_CR2_STOP; // Generate stop here (STOP=1)
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+ *ReadBuffer++ = I2C->DR; // Read 2nd byte
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+ enableInterrupts(); // Errata workaround (Enable interrupt)
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+ while(!(I2C->SR1 & I2C_SR1_RXNE) && tout()); // Wait for RXNE
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+ *ReadBuffer++ = I2C->DR; // Read 3rd Data byte
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+ }
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+ else
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+ {
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+ if(u8_NumByteToRead == 2) // *** just two bytes are received? ***
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+ {
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+ I2C->CR2 |= I2C_CR2_POS; // Set POS bit (NACK at next received byte)
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+ disableInterrupts(); // Errata workaround (Disable interrupt)
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+ I2C->SR3; // Clear ADDR Flag
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+ I2C->CR2 &=~I2C_CR2_ACK; // Clear ACK
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+ enableInterrupts(); // Errata workaround (Enable interrupt)
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+ while(!(I2C->SR1 & I2C_SR1_BTF) && tout()); // Wait for BTF
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+ disableInterrupts(); // Errata workaround (Disable interrupt)
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+ I2C->CR2 |= I2C_CR2_STOP; // Generate stop here (STOP=1)
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+ *ReadBuffer++ = I2C->DR; // Read 1st Data byte
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+ enableInterrupts(); // Errata workaround (Enable interrupt)
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+ *ReadBuffer = I2C->DR; // Read 2nd Data byte
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+ }
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+ else // *** only one byte is received ***
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+ {
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+ I2C->CR2 &=~I2C_CR2_ACK;; // Clear ACK
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+ disableInterrupts(); // Errata workaround (Disable interrupt)
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+ I2C->SR3; // Clear ADDR Flag
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+ I2C->CR2 |= I2C_CR2_STOP; // generate stop here (STOP=1)
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+ enableInterrupts(); // Errata workaround (Enable interrupt)
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+ while(!(I2C->SR1 & I2C_SR1_RXNE) && tout()); // test EV7, wait for RxNE
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+ *ReadBuffer = I2C->DR; // Read Data byte
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+ }
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+ }
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+ /*--------------- All Data Received -----------------------*/
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+ while((I2C->CR2 & I2C_CR2_STOP) && tout()); // Wait until stop is performed (STOPF = 1)
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+ I2C->CR2 &=~I2C_CR2_POS; // return POS to default state (POS=0)
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+}
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+
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+/******************************************************************************
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+* Function name : I2C_WriteRegister
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+* Description : write defined number bytes to slave memory starting with defined offset
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+* Input param : offset in slave memory, number of bytes to write, starting address to send
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+* Return : None.
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+* See also : None.
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+*******************************************************************************/
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+void I2C_WriteRegister(u8 u8_regAddr, u8 u8_NumByteToWrite, u8 *ReadBuffer)
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+{
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+ while((I2C->SR3 & 2) && tout()) // Wait while the bus is busy
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+ {
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+ I2C->CR2 |= 2; // STOP=1, generate stop
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+ while((I2C->CR2 & 2) && tout()); // wait until stop is performed
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+ }
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+
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+ I2C->CR2 |= 1; // START=1, generate start
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+ while(((I2C->SR1 & 1)==0) && tout()); // Wait for start bit detection (SB)
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+ dead_time(); // SB clearing sequence
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+ if(tout())
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+ {
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+ I2C->DR = (u8)(SLAVE_ADDRESS << 1); // Send 7-bit device address & Write (R/W = 0)
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+ }
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+ while(!(I2C->SR1 & 2) && tout()); // Wait for address ack (ADDR)
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+ dead_time(); // ADDR clearing sequence
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+ I2C->SR3;
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+ while(!(I2C->SR1 & 0x80) && tout()); // Wait for TxE
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+ if(tout())
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+ {
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+ I2C->DR = u8_regAddr; // send Offset command
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+ }
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+ if(u8_NumByteToWrite)
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+ {
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+ while(u8_NumByteToWrite--)
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+ { // write data loop start
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+ while(!(I2C->SR1 & 0x80) && tout()); // test EV8 - wait for TxE
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+ I2C->DR = *ReadBuffer++; // send next data byte
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+ } // write data loop end
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+ }
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+ while(((I2C->SR1 & 0x84) != 0x84) && tout()); // Wait for TxE & BTF
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+ dead_time(); // clearing sequence
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+
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+ I2C->CR2 |= 2; // generate stop here (STOP=1)
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+ while((I2C->CR2 & 2) && tout()); // wait until stop is performed
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+}
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+
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+/**
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+ * @brief
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+ *
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+ * @param NumByteToRead
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+ * @param ReadBuffer
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+ */
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+void I2C_ReadBytes(const u8 Addr, const u8 NumByteToRead, u8 *ReadBuffer) {
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+ u8 adr = Addr << 1;
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+ u8 n = NumByteToRead;
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+ set_tout_ms(10);
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+
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+ /*--------------- BUSY? -> STOP request ---------------------*/
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+ while(I2C->SR3 & I2C_SR3_BUSY && tout()) // Wait while the bus is busy
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+ {
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+ I2C->CR2 |= I2C_CR2_STOP; // Generate stop here (STOP=1)
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+ while(I2C->CR2 & I2C_CR2_STOP && tout()); // Wait until stop is performed
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+ }
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+ I2C->CR2 |= I2C_CR2_ACK; // ACK=1, Ack enable
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+ /*--------------- Start communication -----------------------*/
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+ I2C->CR2 |= I2C_CR2_START; // START=1, generate start
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+ while((I2C->SR1 & I2C_SR1_SB)==0 && tout()); // Wait for start bit detection (SB)
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+ /*------------------ Address send ---------------------------*/
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+ if(tout())
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+ {
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+ I2C->DR = (adr | 1); // Send 7-bit device address & Write (R/W = 1)
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+ }
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+ while(!(I2C->SR1 & I2C_SR1_ADDR) && tout()); // Wait for address ack (ADDR)
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+ /*------------------- Data Receive --------------------------*/
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+ if (n > 2) // *** more than 2 bytes are received? ***
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+ {
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+ I2C->SR3; // ADDR clearing sequence
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+ while(n > 3 && tout()) // not last three bytes?
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+ {
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+ while(!(I2C->SR1 & I2C_SR1_BTF) && tout()); // Wait for BTF
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+ *ReadBuffer++ = I2C->DR; // Reading next data byte
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+ --n; // Decrease Numbyte to reade by 1
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+ }
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+ //last three bytes should be read
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+ while(!(I2C->SR1 & I2C_SR1_BTF) && tout()); // Wait for BTF
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+ I2C->CR2 &=~I2C_CR2_ACK; // Clear ACK
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+ disableInterrupts(); // Errata workaround (Disable interrupt)
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+ *ReadBuffer++ = I2C->DR; // Read 1st byte
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+ I2C->CR2 |= I2C_CR2_STOP; // Generate stop here (STOP=1)
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+ *ReadBuffer++ = I2C->DR; // Read 2nd byte
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+ enableInterrupts(); // Errata workaround (Enable interrupt)
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+ while(!(I2C->SR1 & I2C_SR1_RXNE) && tout()); // Wait for RXNE
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+ *ReadBuffer++ = I2C->DR; // Read 3rd Data byte
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+ }
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+ else
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+ {
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+ if(n == 2) // *** just two bytes are received? ***
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+ {
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+ I2C->CR2 |= I2C_CR2_POS; // Set POS bit (NACK at next received byte)
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+ disableInterrupts(); // Errata workaround (Disable interrupt)
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+ I2C->SR3; // Clear ADDR Flag
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+ I2C->CR2 &=~I2C_CR2_ACK; // Clear ACK
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+ enableInterrupts(); // Errata workaround (Enable interrupt)
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+ while(!(I2C->SR1 & I2C_SR1_BTF) && tout()); // Wait for BTF
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+ disableInterrupts(); // Errata workaround (Disable interrupt)
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+ I2C->CR2 |= I2C_CR2_STOP; // Generate stop here (STOP=1)
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+ *ReadBuffer++ = I2C->DR; // Read 1st Data byte
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+ enableInterrupts(); // Errata workaround (Enable interrupt)
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+ *ReadBuffer = I2C->DR; // Read 2nd Data byte
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+ }
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+ else // *** only one byte is received ***
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+ {
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+ I2C->CR2 &=~I2C_CR2_ACK;; // Clear ACK
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+ disableInterrupts(); // Errata workaround (Disable interrupt)
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+ I2C->SR3; // Clear ADDR Flag
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+ I2C->CR2 |= I2C_CR2_STOP; // generate stop here (STOP=1)
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+ enableInterrupts(); // Errata workaround (Enable interrupt)
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+ while(!(I2C->SR1 & I2C_SR1_RXNE) && tout()); // test EV7, wait for RxNE
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+ *ReadBuffer = I2C->DR; // Read Data byte
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+ }
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+ }
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+ /*--------------- All Data Received -----------------------*/
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+ while((I2C->CR2 & I2C_CR2_STOP) && tout()); // Wait until stop is performed (STOPF = 1)
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+ I2C->CR2 &= ~I2C_CR2_POS; // return POS to default state (POS=0)
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+}
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+/**
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+ * @brief write defined number bytes to slave device
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+ *
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+ * @param Addr
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+ * @param NumByteToWrite
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+ * @param DataBuffer
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+ */
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+void I2C_WriteBytes(const u8 Addr, const u8 NumByteToWrite, u8 *DataBuffer) {
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+ u8 adr = Addr << 1;
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+ u8 n = NumByteToWrite;
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+ set_tout_ms(10);
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+
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+ while((I2C->SR3 & 2) && tout()) // Wait while the bus is busy
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+ {
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+ I2C->CR2 |= 2; // STOP=1, generate stop
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+ while((I2C->CR2 & 2) && tout()); // wait until stop is performed
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+ }
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+
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+ I2C->CR2 |= 1; // START=1, generate start
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+ while(((I2C->SR1 & 1)==0) && tout()); // Wait for start bit detection (SB)
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+ dead_time(); // SB clearing sequence
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+ if(tout())
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+ {
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+ I2C->DR = adr; // Send 7-bit device address & Write (R/W = 0)
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+ }
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+ while(!(I2C->SR1 & 2) && tout()); // Wait for address ack (ADDR)
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+ dead_time(); // ADDR clearing sequence
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+ I2C->SR3;
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+ if(n)
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+ {
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+ while(n--)
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+ { // write data loop start
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+ while(!(I2C->SR1 & 0x80) && tout()); // test EV8 - wait for TxE
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+ I2C->DR = *DataBuffer++; // send next data byte
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+ } // write data loop end
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+ }
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+ while(((I2C->SR1 & 0x84) != 0x84) && tout()); // Wait for TxE & BTF
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+ dead_time(); // clearing sequence
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+
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+ I2C->CR2 |= 2; // generate stop here (STOP=1)
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+ while((I2C->CR2 & 2) && tout()); // wait until stop is performed
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+}
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