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@@ -0,0 +1,7335 @@
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+/**
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+ ******************************************************************************
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+ * @file stm32g030xx.h
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+ * @author MCD Application Team
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+ * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
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+ * This file contains all the peripheral register's definitions, bits
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+ * definitions and memory mapping for stm32g030xx devices.
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+ *
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+ * This file contains:
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+ * - Data structures and the address mapping for all peripherals
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+ * - Peripheral's registers declarations and bits definition
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+ * - Macros to access peripheral's registers hardware
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+ *
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+ ******************************************************************************
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+ * @attention
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+ *
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+ * Copyright (c) 2018-2021 STMicroelectronics.
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+ * All rights reserved.
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+ *
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+ * This software is licensed under terms that can be found in the LICENSE file
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+ * in the root directory of this software component.
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+ * If no LICENSE file comes with this software, it is provided AS-IS.
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+ *
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+ ******************************************************************************
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+ */
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+/** @addtogroup CMSIS_Device
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+ * @{
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+ */
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+
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+/** @addtogroup stm32g030xx
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+ * @{
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+ */
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+
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+#ifndef STM32G030xx_H
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+#define STM32G030xx_H
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+
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+#ifdef __cplusplus
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+ extern "C" {
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+#endif /* __cplusplus */
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+
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+/** @addtogroup Configuration_section_for_CMSIS
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+ * @{
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+ */
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+
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+/**
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+ * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
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+ */
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+#define __CM0PLUS_REV 0U /*!< Core Revision r0p0 */
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+#define __MPU_PRESENT 1U /*!< STM32G0xx provides an MPU */
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+#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */
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+#define __NVIC_PRIO_BITS 2U /*!< STM32G0xx uses 2 Bits for the Priority Levels */
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+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
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+
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+/**
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+ * @}
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+ */
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+
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+/** @addtogroup Peripheral_interrupt_number_definition
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+ * @{
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+ */
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+
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+/**
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+ * @brief stm32g030xx Interrupt Number Definition, according to the selected device
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+ * in @ref Library_configuration_section
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+ */
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+
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+/*!< Interrupt Number Definition */
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+typedef enum
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+{
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+/****** Cortex-M0+ Processor Exceptions Numbers ***************************************************************/
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+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
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+ HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
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+ SVC_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
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+ PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */
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+ SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */
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+/****** STM32G0xxxx specific Interrupt Numbers ****************************************************************/
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+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
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+ RTC_TAMP_IRQn = 2, /*!< RTC interrupt through the EXTI line 19 & 21 */
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+ FLASH_IRQn = 3, /*!< FLASH global Interrupt */
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+ RCC_IRQn = 4, /*!< RCC global Interrupt */
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+ EXTI0_1_IRQn = 5, /*!< EXTI 0 and 1 Interrupts */
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+ EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
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+ EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
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+ DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
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+ DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
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+ DMA1_Ch4_5_DMAMUX1_OVR_IRQn = 11, /*!< DMA1 Channel 4 to Channel 5 and DMAMUX1 Overrun Interrupts */
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+ ADC1_IRQn = 12, /*!< ADC1 Interrupts */
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+ TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
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+ TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
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+ TIM3_IRQn = 16, /*!< TIM3 global Interrupt */
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+ TIM14_IRQn = 19, /*!< TIM14 global Interrupt */
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+ TIM16_IRQn = 21, /*!< TIM16 global Interrupt */
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+ TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
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+ I2C1_IRQn = 23, /*!< I2C1 Interrupt (combined with EXTI 23) */
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+ I2C2_IRQn = 24, /*!< I2C2 Interrupt */
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+ SPI1_IRQn = 25, /*!< SPI1/I2S1 Interrupt */
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+ SPI2_IRQn = 26, /*!< SPI2 Interrupt */
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+ USART1_IRQn = 27, /*!< USART1 Interrupt */
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+ USART2_IRQn = 28, /*!< USART2 Interrupt */
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+} IRQn_Type;
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+
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+/**
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+ * @}
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+ */
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+
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+#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
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+#include "system_stm32g0xx.h"
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+#include <stdint.h>
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+
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+/** @addtogroup Peripheral_registers_structures
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+ * @{
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+ */
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+
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+/**
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+ * @brief Analog to Digital Converter
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+ */
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+typedef struct
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+{
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+ __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
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+ __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
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+ __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
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+ __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */
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+ __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
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+ __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */
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+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
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+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
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+ __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
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+ __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */
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+ __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */
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+ __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x2C */
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+ uint32_t RESERVED3[4]; /*!< Reserved, 0x30 - 0x3C */
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+ __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
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+ uint32_t RESERVED4[23];/*!< Reserved, 0x44 - 0x9C */
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+ __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */
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+ __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */
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+ uint32_t RESERVED5[3]; /*!< Reserved, 0xA8 - 0xB0 */
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+ __IO uint32_t CALFACT; /*!< ADC Calibration factor register, Address offset: 0xB4 */
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+} ADC_TypeDef;
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+
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+typedef struct
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+{
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+ __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */
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+} ADC_Common_TypeDef;
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+
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+
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+
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+
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+/**
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+ * @brief CRC calculation unit
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+ */
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+typedef struct
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+{
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+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
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+ __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
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+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
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+ uint32_t RESERVED1; /*!< Reserved, 0x0C */
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+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
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+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
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+} CRC_TypeDef;
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+
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+
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+/**
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+ * @brief Debug MCU
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+ */
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+typedef struct
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+{
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+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
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+ __IO uint32_t CR; /*!< Debug configuration register, Address offset: 0x04 */
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+ __IO uint32_t APBFZ1; /*!< Debug APB freeze register 1, Address offset: 0x08 */
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+ __IO uint32_t APBFZ2; /*!< Debug APB freeze register 2, Address offset: 0x0C */
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+} DBG_TypeDef;
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+
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+/**
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+ * @brief DMA Controller
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+ */
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+typedef struct
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+{
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+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
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+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
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+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
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+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
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+} DMA_Channel_TypeDef;
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+
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+typedef struct
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+{
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+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
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+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
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+} DMA_TypeDef;
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+
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+/**
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+ * @brief DMA Multiplexer
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+ */
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+typedef struct
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+{
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+ __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */
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+}DMAMUX_Channel_TypeDef;
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+
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+typedef struct
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+{
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+ __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */
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+ __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */
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+}DMAMUX_ChannelStatus_TypeDef;
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+
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+typedef struct
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+{
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+ __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */
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+}DMAMUX_RequestGen_TypeDef;
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+
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+typedef struct
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+{
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+ __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */
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+ __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */
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+}DMAMUX_RequestGenStatus_TypeDef;
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+
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+/**
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+ * @brief Asynch Interrupt/Event Controller (EXTI)
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+ */
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+typedef struct
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+{
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+ __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */
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+ __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */
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+ __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */
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+ __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */
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+ __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */
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+ uint32_t RESERVED1[3]; /*!< Reserved 1, 0x14 -- 0x1C */
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+ uint32_t RESERVED2[5]; /*!< Reserved 2, 0x20 -- 0x30 */
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+ uint32_t RESERVED3[11]; /*!< Reserved 3, 0x34 -- 0x5C */
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+ __IO uint32_t EXTICR[4]; /*!< EXTI External Interrupt Configuration Register, 0x60 -- 0x6C */
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+ uint32_t RESERVED4[4]; /*!< Reserved 4, 0x70 -- 0x7C */
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+ __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */
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+ __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */
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+} EXTI_TypeDef;
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+
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+/**
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+ * @brief FLASH Registers
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+ */
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+typedef struct
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+{
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+ __IO uint32_t ACR; /*!< FLASH Access Control register, Address offset: 0x00 */
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+ uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */
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+ __IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */
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+ __IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */
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+ __IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */
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+ __IO uint32_t CR; /*!< FLASH Control register, Address offset: 0x14 */
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+ __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */
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+ uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */
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+ __IO uint32_t OPTR; /*!< FLASH Option register, Address offset: 0x20 */
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+ uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x24--0x28 */
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+ __IO uint32_t WRP1AR; /*!< FLASH Bank WRP area A address register, Address offset: 0x2C */
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+ __IO uint32_t WRP1BR; /*!< FLASH Bank WRP area B address register, Address offset: 0x30 */
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+ uint32_t RESERVED4[2]; /*!< Reserved4, Address offset: 0x34--0x38 */
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+} FLASH_TypeDef;
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+
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+/**
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+ * @brief General Purpose I/O
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+ */
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+typedef struct
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+{
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+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
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+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
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+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
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+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
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+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
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+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
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+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
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+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
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+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
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+ __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */
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+} GPIO_TypeDef;
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+
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+
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+/**
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+ * @brief Inter-integrated Circuit Interface
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+ */
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+typedef struct
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+{
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+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
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+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
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+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
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+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
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+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
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+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
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+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
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+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
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+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
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+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
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+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
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+} I2C_TypeDef;
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+
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+/**
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+ * @brief Independent WATCHDOG
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+ */
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+typedef struct
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+{
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+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
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+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
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+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
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+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
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+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
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+} IWDG_TypeDef;
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+
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+
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+
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+/**
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+ * @brief Power Control
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+ */
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+typedef struct
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+{
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+ __IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset: 0x00 */
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+ uint32_t RESERVED0; /*!< Reserved, Address offset: 0x04 */
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+ __IO uint32_t CR3; /*!< PWR Power Control Register 3, Address offset: 0x08 */
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+ __IO uint32_t CR4; /*!< PWR Power Control Register 4, Address offset: 0x0C */
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+ __IO uint32_t SR1; /*!< PWR Power Status Register 1, Address offset: 0x10 */
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+ __IO uint32_t SR2; /*!< PWR Power Status Register 2, Address offset: 0x14 */
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+ __IO uint32_t SCR; /*!< PWR Power Status Clear Register, Address offset: 0x18 */
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+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
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+ __IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset: 0x20 */
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+ __IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset: 0x24 */
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+ __IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset: 0x28 */
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+ __IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset: 0x2C */
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+ __IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset: 0x30 */
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+ __IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset: 0x34 */
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+ __IO uint32_t PUCRD; /*!< PWR Pull-Up Control Register of port D, Address offset: 0x38 */
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+ __IO uint32_t PDCRD; /*!< PWR Pull-Down Control Register of port D, Address offset: 0x3C */
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+ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x40 */
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+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x44 */
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+ __IO uint32_t PUCRF; /*!< PWR Pull-Up Control Register of port F, Address offset: 0x48 */
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+ __IO uint32_t PDCRF; /*!< PWR Pull-Down Control Register of port F, Address offset: 0x4C */
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+} PWR_TypeDef;
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+
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+/**
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+ * @brief Reset and Clock Control
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+ */
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+typedef struct
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+{
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+ __IO uint32_t CR; /*!< RCC Clock Sources Control Register, Address offset: 0x00 */
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+ __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */
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+ __IO uint32_t CFGR; /*!< RCC Regulated Domain Clocks Configuration Register, Address offset: 0x08 */
|
|
|
+ __IO uint32_t PLLCFGR; /*!< RCC System PLL configuration Register, Address offset: 0x0C */
|
|
|
+ __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */
|
|
|
+ __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
|
|
|
+ __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */
|
|
|
+ __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */
|
|
|
+ __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */
|
|
|
+ __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x24 */
|
|
|
+ __IO uint32_t AHBRSTR; /*!< RCC AHB peripherals reset register, Address offset: 0x28 */
|
|
|
+ __IO uint32_t APBRSTR1; /*!< RCC APB peripherals reset register 1, Address offset: 0x2C */
|
|
|
+ __IO uint32_t APBRSTR2; /*!< RCC APB peripherals reset register 2, Address offset: 0x30 */
|
|
|
+ __IO uint32_t IOPENR; /*!< RCC IO port enable register, Address offset: 0x34 */
|
|
|
+ __IO uint32_t AHBENR; /*!< RCC AHB peripherals clock enable register, Address offset: 0x38 */
|
|
|
+ __IO uint32_t APBENR1; /*!< RCC APB peripherals clock enable register1, Address offset: 0x3C */
|
|
|
+ __IO uint32_t APBENR2; /*!< RCC APB peripherals clock enable register2, Address offset: 0x40 */
|
|
|
+ __IO uint32_t IOPSMENR; /*!< RCC IO port clocks enable in sleep mode register, Address offset: 0x44 */
|
|
|
+ __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clocks enable in sleep mode register, Address offset: 0x48 */
|
|
|
+ __IO uint32_t APBSMENR1; /*!< RCC APB peripheral clocks enable in sleep mode register1, Address offset: 0x4C */
|
|
|
+ __IO uint32_t APBSMENR2; /*!< RCC APB peripheral clocks enable in sleep mode register2, Address offset: 0x50 */
|
|
|
+ __IO uint32_t CCIPR; /*!< RCC Peripherals Independent Clocks Configuration Register, Address offset: 0x54 */
|
|
|
+ __IO uint32_t RESERVED2; /*!< Reserved, Address offset: 0x58 */
|
|
|
+ __IO uint32_t BDCR; /*!< RCC Backup Domain Control Register, Address offset: 0x5C */
|
|
|
+ __IO uint32_t CSR; /*!< RCC Unregulated Domain Clock Control and Status Register, Address offset: 0x60 */
|
|
|
+} RCC_TypeDef;
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Real-Time Clock
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
|
|
|
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
|
|
|
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */
|
|
|
+ __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */
|
|
|
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
|
|
|
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
|
|
|
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */
|
|
|
+ uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */
|
|
|
+ uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */
|
|
|
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
|
|
|
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */
|
|
|
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
|
|
|
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
|
|
|
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
|
|
|
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
|
|
|
+ uint32_t RESERVED2; /*!< Reserved Address offset: 0x1C */
|
|
|
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */
|
|
|
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
|
|
|
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */
|
|
|
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */
|
|
|
+ __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */
|
|
|
+ __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */
|
|
|
+ uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */
|
|
|
+ __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */
|
|
|
+ __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */
|
|
|
+} RTC_TypeDef;
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Tamper and backup registers
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */
|
|
|
+ __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */
|
|
|
+ uint32_t RESERVED0; /*!< Reserved Address offset: 0x08 */
|
|
|
+ __IO uint32_t FLTCR; /*!< Reserved Address offset: 0x0C */
|
|
|
+ uint32_t RESERVED1[7]; /*!< Reserved Address offset: 0x10 -- 0x28 */
|
|
|
+ __IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */
|
|
|
+ __IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */
|
|
|
+ __IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register, Address offset: 0x34 */
|
|
|
+ uint32_t RESERVED2; /*!< Reserved Address offset: 0x38 */
|
|
|
+ __IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */
|
|
|
+ uint32_t RESERVED3[48]; /*!< Reserved Address offset: 0x54 -- 0xFC */
|
|
|
+ __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */
|
|
|
+ __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */
|
|
|
+ __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */
|
|
|
+ __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */
|
|
|
+ __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */
|
|
|
+} TAMP_TypeDef;
|
|
|
+
|
|
|
+ /**
|
|
|
+ * @brief Serial Peripheral Interface
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
|
|
|
+ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
|
|
|
+ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
|
|
|
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
|
|
|
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
|
|
|
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
|
|
|
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
|
|
|
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
|
|
|
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
|
|
|
+} SPI_TypeDef;
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief System configuration controller
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
|
|
|
+ uint32_t RESERVED0[5]; /*!< Reserved, 0x04 --0x14 */
|
|
|
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
|
|
|
+ uint32_t RESERVED1[25]; /*!< Reserved 0x1C */
|
|
|
+ __IO uint32_t IT_LINE_SR[32]; /*!< SYSCFG configuration IT_LINE register, Address offset: 0x80 */
|
|
|
+} SYSCFG_TypeDef;
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief TIM
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
|
|
|
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
|
|
|
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
|
|
|
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
|
|
|
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
|
|
|
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
|
|
|
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
|
|
|
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
|
|
|
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
|
|
|
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
|
|
|
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
|
|
|
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
|
|
|
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
|
|
|
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
|
|
|
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
|
|
|
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
|
|
|
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
|
|
|
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
|
|
|
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
|
|
|
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
|
|
|
+ __IO uint32_t OR1; /*!< TIM option register, Address offset: 0x50 */
|
|
|
+ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
|
|
|
+ __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
|
|
|
+ __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
|
|
|
+ __IO uint32_t AF1; /*!< TIM alternate function register 1, Address offset: 0x60 */
|
|
|
+ __IO uint32_t AF2; /*!< TIM alternate function register 2, Address offset: 0x64 */
|
|
|
+ __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */
|
|
|
+} TIM_TypeDef;
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
|
|
|
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
|
|
|
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
|
|
|
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
|
|
|
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
|
|
|
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
|
|
|
+ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
|
|
|
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
|
|
|
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
|
|
|
+ __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
|
|
|
+ __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
|
|
|
+ __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */
|
|
|
+} USART_TypeDef;
|
|
|
+
|
|
|
+
|
|
|
+/**
|
|
|
+ * @brief Window WATCHDOG
|
|
|
+ */
|
|
|
+typedef struct
|
|
|
+{
|
|
|
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
|
|
|
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
|
|
|
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
|
|
|
+} WWDG_TypeDef;
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+/** @addtogroup Peripheral_memory_map
|
|
|
+ * @{
|
|
|
+ */
|
|
|
+#define FLASH_BASE (0x08000000UL) /*!< FLASH base address */
|
|
|
+#define SRAM_BASE (0x20000000UL) /*!< SRAM base address */
|
|
|
+#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */
|
|
|
+#define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */
|
|
|
+#define SRAM_SIZE_MAX (0x00002000UL) /*!< maximum SRAM size (up to 8 KBytes) */
|
|
|
+
|
|
|
+#define FLASH_SIZE (((*((uint32_t *)FLASHSIZE_BASE)) & (0x007FU)) << 10U)
|
|
|
+
|
|
|
+/*!< Peripheral memory map */
|
|
|
+#define APBPERIPH_BASE (PERIPH_BASE)
|
|
|
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)
|
|
|
+
|
|
|
+/*!< APB peripherals */
|
|
|
+
|
|
|
+#define TIM3_BASE (APBPERIPH_BASE + 0x00000400UL)
|
|
|
+#define TIM14_BASE (APBPERIPH_BASE + 0x00002000UL)
|
|
|
+#define RTC_BASE (APBPERIPH_BASE + 0x00002800UL)
|
|
|
+#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL)
|
|
|
+#define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL)
|
|
|
+#define SPI2_BASE (APBPERIPH_BASE + 0x00003800UL)
|
|
|
+#define USART2_BASE (APBPERIPH_BASE + 0x00004400UL)
|
|
|
+#define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL)
|
|
|
+#define I2C2_BASE (APBPERIPH_BASE + 0x00005800UL)
|
|
|
+#define PWR_BASE (APBPERIPH_BASE + 0x00007000UL)
|
|
|
+#define TAMP_BASE (APBPERIPH_BASE + 0x0000B000UL)
|
|
|
+#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL)
|
|
|
+#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL)
|
|
|
+#define ADC1_COMMON_BASE (APBPERIPH_BASE + 0x00012708UL)
|
|
|
+#define ADC_BASE (ADC1_COMMON_BASE) /* Kept for legacy purpose */
|
|
|
+#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00UL)
|
|
|
+#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL)
|
|
|
+#define USART1_BASE (APBPERIPH_BASE + 0x00013800UL)
|
|
|
+#define TIM16_BASE (APBPERIPH_BASE + 0x00014400UL)
|
|
|
+#define TIM17_BASE (APBPERIPH_BASE + 0x00014800UL)
|
|
|
+#define DBG_BASE (APBPERIPH_BASE + 0x00015800UL)
|
|
|
+
|
|
|
+
|
|
|
+/*!< AHB peripherals */
|
|
|
+#define DMA1_BASE (AHBPERIPH_BASE)
|
|
|
+#define DMAMUX1_BASE (AHBPERIPH_BASE + 0x00000800UL)
|
|
|
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL)
|
|
|
+#define EXTI_BASE (AHBPERIPH_BASE + 0x00001800UL)
|
|
|
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL)
|
|
|
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)
|
|
|
+
|
|
|
+
|
|
|
+#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL)
|
|
|
+#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL)
|
|
|
+#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)
|
|
|
+#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)
|
|
|
+#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)
|
|
|
+
|
|
|
+#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
|
|
|
+#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004UL)
|
|
|
+#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008UL)
|
|
|
+#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000CUL)
|
|
|
+#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010UL)
|
|
|
+
|
|
|
+#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100UL)
|
|
|
+#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104UL)
|
|
|
+#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108UL)
|
|
|
+#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010CUL)
|
|
|
+
|
|
|
+#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL)
|
|
|
+#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL)
|
|
|
+
|
|
|
+/*!< IOPORT */
|
|
|
+#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL)
|
|
|
+#define GPIOB_BASE (IOPORT_BASE + 0x00000400UL)
|
|
|
+#define GPIOC_BASE (IOPORT_BASE + 0x00000800UL)
|
|
|
+#define GPIOD_BASE (IOPORT_BASE + 0x00000C00UL)
|
|
|
+#define GPIOF_BASE (IOPORT_BASE + 0x00001400UL)
|
|
|
+
|
|
|
+/*!< Device Electronic Signature */
|
|
|
+#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */
|
|
|
+#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */
|
|
|
+#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @}
|
|
|
+ */
|
|
|
+
|
|
|
+/** @addtogroup Peripheral_declaration
|
|
|
+ * @{
|
|
|
+ */
|
|
|
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
|
|
|
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
|
|
|
+#define RTC ((RTC_TypeDef *) RTC_BASE)
|
|
|
+#define TAMP ((TAMP_TypeDef *) TAMP_BASE)
|
|
|
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
|
|
|
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
|
|
|
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
|
|
|
+#define USART2 ((USART_TypeDef *) USART2_BASE)
|
|
|
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
|
|
|
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
|
|
|
+#define PWR ((PWR_TypeDef *) PWR_BASE)
|
|
|
+#define RCC ((RCC_TypeDef *) RCC_BASE)
|
|
|
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
|
|
|
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
|
|
|
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
|
|
|
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
|
|
|
+#define USART1 ((USART_TypeDef *) USART1_BASE)
|
|
|
+#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
|
|
|
+#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
|
|
|
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
|
|
|
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
|
|
|
+#define CRC ((CRC_TypeDef *) CRC_BASE)
|
|
|
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
|
|
|
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
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+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
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+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
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+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
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+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
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+#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
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+#define ADC (ADC1_COMMON) /* Kept for legacy purpose */
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+
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+
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+
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+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
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+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
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+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
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+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
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+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
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+#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
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+#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
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+#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
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+#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
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+#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
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+#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
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+
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+#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
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+#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
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+#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
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+#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
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+
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+#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
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+#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
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+
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+#define DBG ((DBG_TypeDef *) DBG_BASE)
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+
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+/**
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+ * @}
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+ */
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+
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+/** @addtogroup Exported_constants
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+ * @{
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+ */
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+
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+ /** @addtogroup Hardware_Constant_Definition
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+ * @{
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+ */
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+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
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+
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+ /**
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+ * @}
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+ */
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+
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+ /** @addtogroup Peripheral_Registers_Bits_Definition
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+ * @{
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+ */
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+
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+/******************************************************************************/
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+/* Peripheral Registers Bits Definition */
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+/******************************************************************************/
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+
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+/******************************************************************************/
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+/* */
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+/* Analog to Digital Converter (ADC) */
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+/* */
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+/******************************************************************************/
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+/******************** Bit definition for ADC_ISR register *******************/
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+#define ADC_ISR_ADRDY_Pos (0U)
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+#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
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+#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
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+#define ADC_ISR_EOSMP_Pos (1U)
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+#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
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+#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
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+#define ADC_ISR_EOC_Pos (2U)
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+#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
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+#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
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+#define ADC_ISR_EOS_Pos (3U)
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+#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
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+#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
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+#define ADC_ISR_OVR_Pos (4U)
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+#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
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+#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
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+#define ADC_ISR_AWD1_Pos (7U)
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+#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
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+#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
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+#define ADC_ISR_AWD2_Pos (8U)
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+#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
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+#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */
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+#define ADC_ISR_AWD3_Pos (9U)
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+#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
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+#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */
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+#define ADC_ISR_EOCAL_Pos (11U)
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+#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */
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|
+#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC end of calibration flag */
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+#define ADC_ISR_CCRDY_Pos (13U)
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|
+#define ADC_ISR_CCRDY_Msk (0x1UL << ADC_ISR_CCRDY_Pos) /*!< 0x00002000 */
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|
+#define ADC_ISR_CCRDY ADC_ISR_CCRDY_Msk /*!< ADC channel configuration ready flag */
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+
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|
+/* Legacy defines */
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|
+#define ADC_ISR_EOSEQ (ADC_ISR_EOS)
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+
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|
+/******************** Bit definition for ADC_IER register *******************/
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+#define ADC_IER_ADRDYIE_Pos (0U)
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+#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
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+#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
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|
+#define ADC_IER_EOSMPIE_Pos (1U)
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|
+#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
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|
|
+#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
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|
+#define ADC_IER_EOCIE_Pos (2U)
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|
|
+#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
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|
|
+#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
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|
|
+#define ADC_IER_EOSIE_Pos (3U)
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|
|
+#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
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|
|
+#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
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|
+#define ADC_IER_OVRIE_Pos (4U)
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|
+#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
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|
|
+#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
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|
|
+#define ADC_IER_AWD1IE_Pos (7U)
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|
|
+#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
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|
|
+#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
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|
|
+#define ADC_IER_AWD2IE_Pos (8U)
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|
+#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
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|
+#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */
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|
+#define ADC_IER_AWD3IE_Pos (9U)
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|
+#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
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|
|
+#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */
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|
|
+#define ADC_IER_EOCALIE_Pos (11U)
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|
|
+#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */
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|
|
+#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC end of calibration interrupt */
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|
|
+#define ADC_IER_CCRDYIE_Pos (13U)
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|
+#define ADC_IER_CCRDYIE_Msk (0x1UL << ADC_IER_CCRDYIE_Pos) /*!< 0x00002000 */
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|
|
+#define ADC_IER_CCRDYIE ADC_IER_CCRDYIE_Msk /*!< ADC channel configuration ready interrupt */
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|
|
+
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|
|
+/* Legacy defines */
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|
|
+#define ADC_IER_EOSEQIE (ADC_IER_EOSIE)
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|
|
+
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|
|
+/******************** Bit definition for ADC_CR register ********************/
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|
+#define ADC_CR_ADEN_Pos (0U)
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|
|
+#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
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|
|
+#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
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|
|
+#define ADC_CR_ADDIS_Pos (1U)
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|
|
+#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
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|
|
+#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
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|
+#define ADC_CR_ADSTART_Pos (2U)
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|
+#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
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|
+#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
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|
+#define ADC_CR_ADSTP_Pos (4U)
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|
+#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
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|
|
+#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
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|
+#define ADC_CR_ADVREGEN_Pos (28U)
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|
+#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
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|
+#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */
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|
+#define ADC_CR_ADCAL_Pos (31U)
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|
+#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
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+#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
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|
+
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|
+/******************** Bit definition for ADC_CFGR1 register *****************/
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|
|
+#define ADC_CFGR1_DMAEN_Pos (0U)
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|
+#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */
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|
|
+#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */
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|
+#define ADC_CFGR1_DMACFG_Pos (1U)
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|
+#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */
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|
|
+#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */
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|
+
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|
+#define ADC_CFGR1_SCANDIR_Pos (2U)
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|
+#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */
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|
|
+#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */
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|
+
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|
+#define ADC_CFGR1_RES_Pos (3U)
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|
+#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */
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|
|
+#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */
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|
|
+#define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */
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|
+#define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */
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|
|
+
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|
|
+#define ADC_CFGR1_ALIGN_Pos (5U)
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|
|
+#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
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|
|
+#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */
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|
|
+
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|
|
+#define ADC_CFGR1_EXTSEL_Pos (6U)
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|
|
+#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
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|
|
+#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */
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|
|
+#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
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|
|
+#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
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|
|
+#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */
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|
|
+
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|
|
+#define ADC_CFGR1_EXTEN_Pos (10U)
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|
|
+#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */
|
|
|
+#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */
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|
|
+#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */
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|
|
+#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */
|
|
|
+
|
|
|
+#define ADC_CFGR1_OVRMOD_Pos (12U)
|
|
|
+#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */
|
|
|
+#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */
|
|
|
+#define ADC_CFGR1_CONT_Pos (13U)
|
|
|
+#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */
|
|
|
+#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */
|
|
|
+#define ADC_CFGR1_WAIT_Pos (14U)
|
|
|
+#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */
|
|
|
+#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */
|
|
|
+#define ADC_CFGR1_AUTOFF_Pos (15U)
|
|
|
+#define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */
|
|
|
+#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */
|
|
|
+#define ADC_CFGR1_DISCEN_Pos (16U)
|
|
|
+#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */
|
|
|
+#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
|
|
|
+#define ADC_CFGR1_CHSELRMOD_Pos (21U)
|
|
|
+#define ADC_CFGR1_CHSELRMOD_Msk (0x1UL << ADC_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */
|
|
|
+#define ADC_CFGR1_CHSELRMOD ADC_CFGR1_CHSELRMOD_Msk /*!< ADC group regular sequencer mode */
|
|
|
+
|
|
|
+#define ADC_CFGR1_AWD1SGL_Pos (22U)
|
|
|
+#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */
|
|
|
+#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
|
|
|
+#define ADC_CFGR1_AWD1EN_Pos (23U)
|
|
|
+#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */
|
|
|
+#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
|
|
|
+
|
|
|
+#define ADC_CFGR1_AWD1CH_Pos (26U)
|
|
|
+#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */
|
|
|
+#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
|
|
|
+#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */
|
|
|
+#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */
|
|
|
+#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */
|
|
|
+#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */
|
|
|
+#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */
|
|
|
+
|
|
|
+/* Legacy defines */
|
|
|
+#define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT)
|
|
|
+
|
|
|
+/******************** Bit definition for ADC_CFGR2 register *****************/
|
|
|
+#define ADC_CFGR2_OVSE_Pos (0U)
|
|
|
+#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */
|
|
|
+#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */
|
|
|
+
|
|
|
+#define ADC_CFGR2_OVSR_Pos (2U)
|
|
|
+#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
|
|
|
+#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */
|
|
|
+#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
|
|
|
+#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
|
|
|
+#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
|
|
|
+
|
|
|
+#define ADC_CFGR2_OVSS_Pos (5U)
|
|
|
+#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
|
|
|
+#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */
|
|
|
+#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
|
|
|
+#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
|
|
|
+#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
|
|
|
+#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
|
|
|
+
|
|
|
+#define ADC_CFGR2_TOVS_Pos (9U)
|
|
|
+#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x00000200 */
|
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+#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
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+
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+#define ADC_CFGR2_LFTRIG_Pos (29U)
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+#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */
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+#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */
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+
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+#define ADC_CFGR2_CKMODE_Pos (30U)
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+#define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */
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+#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */
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+#define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */
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+#define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */
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+
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+/******************** Bit definition for ADC_SMPR register ******************/
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+#define ADC_SMPR_SMP1_Pos (0U)
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+#define ADC_SMPR_SMP1_Msk (0x7UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000007 */
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+#define ADC_SMPR_SMP1 ADC_SMPR_SMP1_Msk /*!< ADC group of channels sampling time 1 */
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+#define ADC_SMPR_SMP1_0 (0x1UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000001 */
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+#define ADC_SMPR_SMP1_1 (0x2UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000002 */
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+#define ADC_SMPR_SMP1_2 (0x4UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000004 */
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+
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+#define ADC_SMPR_SMP2_Pos (4U)
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+#define ADC_SMPR_SMP2_Msk (0x7UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000070 */
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+#define ADC_SMPR_SMP2 ADC_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */
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+#define ADC_SMPR_SMP2_0 (0x1UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000010 */
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+#define ADC_SMPR_SMP2_1 (0x2UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000020 */
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+#define ADC_SMPR_SMP2_2 (0x4UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000040 */
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+
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+#define ADC_SMPR_SMPSEL_Pos (8U)
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+#define ADC_SMPR_SMPSEL_Msk (0x7FFFFUL << ADC_SMPR_SMPSEL_Pos) /*!< 0x07FFFF00 */
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+#define ADC_SMPR_SMPSEL ADC_SMPR_SMPSEL_Msk /*!< ADC all channels sampling time selection */
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+#define ADC_SMPR_SMPSEL0_Pos (8U)
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+#define ADC_SMPR_SMPSEL0_Msk (0x1UL << ADC_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */
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+#define ADC_SMPR_SMPSEL0 ADC_SMPR_SMPSEL0_Msk /*!< ADC channel 0 sampling time selection */
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+#define ADC_SMPR_SMPSEL1_Pos (9U)
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+#define ADC_SMPR_SMPSEL1_Msk (0x1UL << ADC_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */
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+#define ADC_SMPR_SMPSEL1 ADC_SMPR_SMPSEL1_Msk /*!< ADC channel 1 sampling time selection */
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+#define ADC_SMPR_SMPSEL2_Pos (10U)
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+#define ADC_SMPR_SMPSEL2_Msk (0x1UL << ADC_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */
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+#define ADC_SMPR_SMPSEL2 ADC_SMPR_SMPSEL2_Msk /*!< ADC channel 2 sampling time selection */
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+#define ADC_SMPR_SMPSEL3_Pos (11U)
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+#define ADC_SMPR_SMPSEL3_Msk (0x1UL << ADC_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */
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+#define ADC_SMPR_SMPSEL3 ADC_SMPR_SMPSEL3_Msk /*!< ADC channel 3 sampling time selection */
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+#define ADC_SMPR_SMPSEL4_Pos (12U)
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+#define ADC_SMPR_SMPSEL4_Msk (0x1UL << ADC_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */
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+#define ADC_SMPR_SMPSEL4 ADC_SMPR_SMPSEL4_Msk /*!< ADC channel 4 sampling time selection */
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+#define ADC_SMPR_SMPSEL5_Pos (13U)
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+#define ADC_SMPR_SMPSEL5_Msk (0x1UL << ADC_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */
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+#define ADC_SMPR_SMPSEL5 ADC_SMPR_SMPSEL5_Msk /*!< ADC channel 5 sampling time selection */
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+#define ADC_SMPR_SMPSEL6_Pos (14U)
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+#define ADC_SMPR_SMPSEL6_Msk (0x1UL << ADC_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */
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+#define ADC_SMPR_SMPSEL6 ADC_SMPR_SMPSEL6_Msk /*!< ADC channel 6 sampling time selection */
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+#define ADC_SMPR_SMPSEL7_Pos (15U)
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+#define ADC_SMPR_SMPSEL7_Msk (0x1UL << ADC_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */
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+#define ADC_SMPR_SMPSEL7 ADC_SMPR_SMPSEL7_Msk /*!< ADC channel 7 sampling time selection */
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+#define ADC_SMPR_SMPSEL8_Pos (16U)
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+#define ADC_SMPR_SMPSEL8_Msk (0x1UL << ADC_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */
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+#define ADC_SMPR_SMPSEL8 ADC_SMPR_SMPSEL8_Msk /*!< ADC channel 8 sampling time selection */
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+#define ADC_SMPR_SMPSEL9_Pos (17U)
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+#define ADC_SMPR_SMPSEL9_Msk (0x1UL << ADC_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */
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+#define ADC_SMPR_SMPSEL9 ADC_SMPR_SMPSEL9_Msk /*!< ADC channel 9 sampling time selection */
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+#define ADC_SMPR_SMPSEL10_Pos (18U)
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+#define ADC_SMPR_SMPSEL10_Msk (0x1UL << ADC_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */
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+#define ADC_SMPR_SMPSEL10 ADC_SMPR_SMPSEL10_Msk /*!< ADC channel 10 sampling time selection */
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+#define ADC_SMPR_SMPSEL11_Pos (19U)
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+#define ADC_SMPR_SMPSEL11_Msk (0x1UL << ADC_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */
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+#define ADC_SMPR_SMPSEL11 ADC_SMPR_SMPSEL11_Msk /*!< ADC channel 11 sampling time selection */
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+#define ADC_SMPR_SMPSEL12_Pos (20U)
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+#define ADC_SMPR_SMPSEL12_Msk (0x1UL << ADC_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */
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+#define ADC_SMPR_SMPSEL12 ADC_SMPR_SMPSEL12_Msk /*!< ADC channel 12 sampling time selection */
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+#define ADC_SMPR_SMPSEL13_Pos (21U)
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+#define ADC_SMPR_SMPSEL13_Msk (0x1UL << ADC_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */
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+#define ADC_SMPR_SMPSEL13 ADC_SMPR_SMPSEL13_Msk /*!< ADC channel 13 sampling time selection */
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+#define ADC_SMPR_SMPSEL14_Pos (22U)
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+#define ADC_SMPR_SMPSEL14_Msk (0x1UL << ADC_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */
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+#define ADC_SMPR_SMPSEL14 ADC_SMPR_SMPSEL14_Msk /*!< ADC channel 14 sampling time selection */
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+#define ADC_SMPR_SMPSEL15_Pos (23U)
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+#define ADC_SMPR_SMPSEL15_Msk (0x1UL << ADC_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */
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+#define ADC_SMPR_SMPSEL15 ADC_SMPR_SMPSEL15_Msk /*!< ADC channel 15 sampling time selection */
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+#define ADC_SMPR_SMPSEL16_Pos (24U)
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+#define ADC_SMPR_SMPSEL16_Msk (0x1UL << ADC_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */
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+#define ADC_SMPR_SMPSEL16 ADC_SMPR_SMPSEL16_Msk /*!< ADC channel 16 sampling time selection */
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+#define ADC_SMPR_SMPSEL17_Pos (25U)
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+#define ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */
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+#define ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk /*!< ADC channel 17 sampling time selection */
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+#define ADC_SMPR_SMPSEL18_Pos (26U)
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+#define ADC_SMPR_SMPSEL18_Msk (0x1UL << ADC_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */
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+#define ADC_SMPR_SMPSEL18 ADC_SMPR_SMPSEL18_Msk /*!< ADC channel 18 sampling time selection */
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+
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+/******************** Bit definition for ADC_TR1 register *******************/
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+#define ADC_TR1_LT1_Pos (0U)
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+#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
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+#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
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+#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */
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+#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */
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+#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */
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+#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */
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+#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */
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+#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */
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+#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */
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+#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */
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+#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */
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+#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */
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+#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */
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+#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */
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+
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+#define ADC_TR1_HT1_Pos (16U)
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+#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
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+#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */
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+#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */
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+#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */
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+#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */
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+#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */
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+#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */
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+#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */
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+#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */
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+#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */
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+#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */
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+#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */
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+#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */
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+#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */
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+
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+/******************** Bit definition for ADC_TR2 register *******************/
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+#define ADC_TR2_LT2_Pos (0U)
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+#define ADC_TR2_LT2_Msk (0xFFFUL << ADC_TR2_LT2_Pos) /*!< 0x00000FFF */
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+#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */
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+#define ADC_TR2_LT2_0 (0x001UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */
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+#define ADC_TR2_LT2_1 (0x002UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */
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+#define ADC_TR2_LT2_2 (0x004UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */
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+#define ADC_TR2_LT2_3 (0x008UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */
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+#define ADC_TR2_LT2_4 (0x010UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */
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+#define ADC_TR2_LT2_5 (0x020UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */
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+#define ADC_TR2_LT2_6 (0x040UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */
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+#define ADC_TR2_LT2_7 (0x080UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */
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+#define ADC_TR2_LT2_8 (0x100UL << ADC_TR2_LT2_Pos) /*!< 0x00000100 */
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+#define ADC_TR2_LT2_9 (0x200UL << ADC_TR2_LT2_Pos) /*!< 0x00000200 */
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+#define ADC_TR2_LT2_10 (0x400UL << ADC_TR2_LT2_Pos) /*!< 0x00000400 */
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+#define ADC_TR2_LT2_11 (0x800UL << ADC_TR2_LT2_Pos) /*!< 0x00000800 */
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+
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+#define ADC_TR2_HT2_Pos (16U)
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+#define ADC_TR2_HT2_Msk (0xFFFUL << ADC_TR2_HT2_Pos) /*!< 0x0FFF0000 */
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+#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */
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+#define ADC_TR2_HT2_0 (0x001UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */
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+#define ADC_TR2_HT2_1 (0x002UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */
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+#define ADC_TR2_HT2_2 (0x004UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */
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+#define ADC_TR2_HT2_3 (0x008UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */
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+#define ADC_TR2_HT2_4 (0x010UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */
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+#define ADC_TR2_HT2_5 (0x020UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */
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+#define ADC_TR2_HT2_6 (0x040UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */
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+#define ADC_TR2_HT2_7 (0x080UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */
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+#define ADC_TR2_HT2_8 (0x100UL << ADC_TR2_HT2_Pos) /*!< 0x01000000 */
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+#define ADC_TR2_HT2_9 (0x200UL << ADC_TR2_HT2_Pos) /*!< 0x02000000 */
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+#define ADC_TR2_HT2_10 (0x400UL << ADC_TR2_HT2_Pos) /*!< 0x04000000 */
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+#define ADC_TR2_HT2_11 (0x800UL << ADC_TR2_HT2_Pos) /*!< 0x08000000 */
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+
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+/******************** Bit definition for ADC_CHSELR register ****************/
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+#define ADC_CHSELR_CHSEL_Pos (0U)
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+#define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */
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+#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */
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+#define ADC_CHSELR_CHSEL18_Pos (18U)
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+#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */
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+#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */
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+#define ADC_CHSELR_CHSEL17_Pos (17U)
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+#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */
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+#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */
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+#define ADC_CHSELR_CHSEL16_Pos (16U)
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+#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */
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+#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */
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+#define ADC_CHSELR_CHSEL15_Pos (15U)
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+#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */
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+#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */
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+#define ADC_CHSELR_CHSEL14_Pos (14U)
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+#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */
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+#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */
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+#define ADC_CHSELR_CHSEL13_Pos (13U)
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+#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */
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+#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */
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+#define ADC_CHSELR_CHSEL12_Pos (12U)
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+#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */
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+#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */
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+#define ADC_CHSELR_CHSEL11_Pos (11U)
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+#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */
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+#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */
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+#define ADC_CHSELR_CHSEL10_Pos (10U)
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+#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */
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+#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */
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+#define ADC_CHSELR_CHSEL9_Pos (9U)
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+#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */
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+#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */
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+#define ADC_CHSELR_CHSEL8_Pos (8U)
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+#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */
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+#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */
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+#define ADC_CHSELR_CHSEL7_Pos (7U)
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+#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */
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+#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */
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+#define ADC_CHSELR_CHSEL6_Pos (6U)
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+#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */
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+#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */
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+#define ADC_CHSELR_CHSEL5_Pos (5U)
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+#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */
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+#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */
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+#define ADC_CHSELR_CHSEL4_Pos (4U)
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+#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */
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+#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */
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+#define ADC_CHSELR_CHSEL3_Pos (3U)
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+#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */
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+#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */
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+#define ADC_CHSELR_CHSEL2_Pos (2U)
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+#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */
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+#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */
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+#define ADC_CHSELR_CHSEL1_Pos (1U)
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+#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */
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+#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */
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+#define ADC_CHSELR_CHSEL0_Pos (0U)
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+#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */
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+#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */
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+
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+#define ADC_CHSELR_SQ_ALL_Pos (0U)
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+#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */
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+#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */
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+
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+#define ADC_CHSELR_SQ8_Pos (28U)
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+#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */
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+#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */
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+#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */
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+#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */
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+#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */
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+#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */
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+
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+#define ADC_CHSELR_SQ7_Pos (24U)
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+#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */
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+#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */
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+#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */
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+#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */
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+#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */
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+#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */
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+
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+#define ADC_CHSELR_SQ6_Pos (20U)
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+#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */
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+#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */
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+#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */
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+#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */
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+#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */
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+#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */
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+
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+#define ADC_CHSELR_SQ5_Pos (16U)
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+#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */
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+#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */
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+#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */
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+#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */
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+#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */
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+#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */
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+
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+#define ADC_CHSELR_SQ4_Pos (12U)
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+#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */
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+#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */
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+#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */
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+#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */
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+#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */
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+#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */
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+
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+#define ADC_CHSELR_SQ3_Pos (8U)
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+#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */
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+#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */
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+#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */
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+#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */
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+#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */
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+#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */
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+
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+#define ADC_CHSELR_SQ2_Pos (4U)
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+#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */
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+#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */
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+#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */
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+#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */
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+#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */
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+#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */
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+
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+#define ADC_CHSELR_SQ1_Pos (0U)
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+#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */
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+#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */
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+#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */
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+#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */
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+#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */
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+#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */
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+
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+/******************** Bit definition for ADC_TR3 register *******************/
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+#define ADC_TR3_LT3_Pos (0U)
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+#define ADC_TR3_LT3_Msk (0xFFFUL << ADC_TR3_LT3_Pos) /*!< 0x00000FFF */
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+#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */
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+#define ADC_TR3_LT3_0 (0x001UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */
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+#define ADC_TR3_LT3_1 (0x002UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */
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+#define ADC_TR3_LT3_2 (0x004UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */
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+#define ADC_TR3_LT3_3 (0x008UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */
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+#define ADC_TR3_LT3_4 (0x010UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */
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+#define ADC_TR3_LT3_5 (0x020UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */
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+#define ADC_TR3_LT3_6 (0x040UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */
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+#define ADC_TR3_LT3_7 (0x080UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */
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+#define ADC_TR3_LT3_8 (0x100UL << ADC_TR3_LT3_Pos) /*!< 0x00000100 */
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+#define ADC_TR3_LT3_9 (0x200UL << ADC_TR3_LT3_Pos) /*!< 0x00000200 */
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+#define ADC_TR3_LT3_10 (0x400UL << ADC_TR3_LT3_Pos) /*!< 0x00000400 */
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+#define ADC_TR3_LT3_11 (0x800UL << ADC_TR3_LT3_Pos) /*!< 0x00000800 */
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+
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+#define ADC_TR3_HT3_Pos (16U)
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+#define ADC_TR3_HT3_Msk (0xFFFUL << ADC_TR3_HT3_Pos) /*!< 0x0FFF0000 */
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+#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */
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+#define ADC_TR3_HT3_0 (0x001UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */
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+#define ADC_TR3_HT3_1 (0x002UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */
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+#define ADC_TR3_HT3_2 (0x004UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */
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+#define ADC_TR3_HT3_3 (0x008UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */
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+#define ADC_TR3_HT3_4 (0x010UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */
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+#define ADC_TR3_HT3_5 (0x020UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */
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+#define ADC_TR3_HT3_6 (0x040UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */
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+#define ADC_TR3_HT3_7 (0x080UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */
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+#define ADC_TR3_HT3_8 (0x100UL << ADC_TR3_HT3_Pos) /*!< 0x01000000 */
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+#define ADC_TR3_HT3_9 (0x200UL << ADC_TR3_HT3_Pos) /*!< 0x02000000 */
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+#define ADC_TR3_HT3_10 (0x400UL << ADC_TR3_HT3_Pos) /*!< 0x04000000 */
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+#define ADC_TR3_HT3_11 (0x800UL << ADC_TR3_HT3_Pos) /*!< 0x08000000 */
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+
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+/******************** Bit definition for ADC_DR register ********************/
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+#define ADC_DR_DATA_Pos (0U)
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+#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
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+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */
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+#define ADC_DR_DATA_0 (0x0001UL << ADC_DR_DATA_Pos) /*!< 0x00000001 */
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+#define ADC_DR_DATA_1 (0x0002UL << ADC_DR_DATA_Pos) /*!< 0x00000002 */
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+#define ADC_DR_DATA_2 (0x0004UL << ADC_DR_DATA_Pos) /*!< 0x00000004 */
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+#define ADC_DR_DATA_3 (0x0008UL << ADC_DR_DATA_Pos) /*!< 0x00000008 */
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+#define ADC_DR_DATA_4 (0x0010UL << ADC_DR_DATA_Pos) /*!< 0x00000010 */
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+#define ADC_DR_DATA_5 (0x0020UL << ADC_DR_DATA_Pos) /*!< 0x00000020 */
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+#define ADC_DR_DATA_6 (0x0040UL << ADC_DR_DATA_Pos) /*!< 0x00000040 */
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+#define ADC_DR_DATA_7 (0x0080UL << ADC_DR_DATA_Pos) /*!< 0x00000080 */
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+#define ADC_DR_DATA_8 (0x0100UL << ADC_DR_DATA_Pos) /*!< 0x00000100 */
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+#define ADC_DR_DATA_9 (0x0200UL << ADC_DR_DATA_Pos) /*!< 0x00000200 */
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+#define ADC_DR_DATA_10 (0x0400UL << ADC_DR_DATA_Pos) /*!< 0x00000400 */
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+#define ADC_DR_DATA_11 (0x0800UL << ADC_DR_DATA_Pos) /*!< 0x00000800 */
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+#define ADC_DR_DATA_12 (0x1000UL << ADC_DR_DATA_Pos) /*!< 0x00001000 */
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+#define ADC_DR_DATA_13 (0x2000UL << ADC_DR_DATA_Pos) /*!< 0x00002000 */
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+#define ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos) /*!< 0x00004000 */
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+#define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos) /*!< 0x00008000 */
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+
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+/******************** Bit definition for ADC_AWD2CR register ****************/
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+#define ADC_AWD2CR_AWD2CH_Pos (0U)
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+#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
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+#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */
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+#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
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+#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
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+#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
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+#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
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+#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
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+#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
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+#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
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+#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
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+#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
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+#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
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+#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
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+#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
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+#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
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+#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
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+#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
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+#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
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+#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
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+#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
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+#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
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+
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+/******************** Bit definition for ADC_AWD3CR register ****************/
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+#define ADC_AWD3CR_AWD3CH_Pos (0U)
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+#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
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+#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */
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+#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
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+#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
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+#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
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+#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
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+#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
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+#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
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+#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
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+#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
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+#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
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+#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
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+#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
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+#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
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+#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
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+#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
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+#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
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+#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
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+#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
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+#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
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+#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
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+
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+/******************** Bit definition for ADC_CALFACT register ***************/
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+#define ADC_CALFACT_CALFACT_Pos (0U)
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+#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */
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+#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */
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+#define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */
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+#define ADC_CALFACT_CALFACT_1 (0x02UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */
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+#define ADC_CALFACT_CALFACT_2 (0x04UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */
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+#define ADC_CALFACT_CALFACT_3 (0x08UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */
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+#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */
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+#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */
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+#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */
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+
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+/************************* ADC Common registers *****************************/
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+/******************** Bit definition for ADC_CCR register *******************/
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+#define ADC_CCR_PRESC_Pos (18U)
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+#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
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+#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */
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+#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
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+#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
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+#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
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+#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
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+
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+#define ADC_CCR_VREFEN_Pos (22U)
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+#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
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+#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
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+#define ADC_CCR_TSEN_Pos (23U)
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+#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
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+#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */
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+#define ADC_CCR_VBATEN_Pos (24U)
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+#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
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+#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
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+
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+/* Legacy */
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+#define ADC_CCR_LFMEN_Pos (25U)
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+#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
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+#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Legacy feature, useless on STM32G0 (ADC common clock low frequency mode is automatically managed by ADC peripheral on STM32G0) */
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+
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+
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+/******************************************************************************/
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+/* */
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+/* CRC calculation unit */
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+/* */
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+/******************************************************************************/
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+/******************* Bit definition for CRC_DR register *********************/
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+#define CRC_DR_DR_Pos (0U)
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+#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
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+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
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+
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+/******************* Bit definition for CRC_IDR register ********************/
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+#define CRC_IDR_IDR_Pos (0U)
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+#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */
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+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */
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+
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+/******************** Bit definition for CRC_CR register ********************/
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+#define CRC_CR_RESET_Pos (0U)
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+#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
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+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
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+#define CRC_CR_POLYSIZE_Pos (3U)
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+#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
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+#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
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+#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
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+#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
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+#define CRC_CR_REV_IN_Pos (5U)
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+#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
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+#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
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+#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
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+#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
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+#define CRC_CR_REV_OUT_Pos (7U)
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+#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
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+#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
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+
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+/******************* Bit definition for CRC_INIT register *******************/
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+#define CRC_INIT_INIT_Pos (0U)
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+#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
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+#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
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+
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+/******************* Bit definition for CRC_POL register ********************/
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+#define CRC_POL_POL_Pos (0U)
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+#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
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+#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
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+
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+
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+
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+/******************************************************************************/
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+/* */
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+/* Debug MCU */
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+/* */
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+/******************************************************************************/
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+
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+/******************************************************************************/
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+/* */
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+/* DMA Controller (DMA) */
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+/* */
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+/******************************************************************************/
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+
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+/******************* Bit definition for DMA_ISR register ********************/
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+#define DMA_ISR_GIF1_Pos (0U)
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+#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
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+#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
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+#define DMA_ISR_TCIF1_Pos (1U)
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+#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
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+#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
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+#define DMA_ISR_HTIF1_Pos (2U)
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+#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
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+#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
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+#define DMA_ISR_TEIF1_Pos (3U)
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+#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
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+#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
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+#define DMA_ISR_GIF2_Pos (4U)
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+#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
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+#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
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+#define DMA_ISR_TCIF2_Pos (5U)
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+#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
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+#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
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+#define DMA_ISR_HTIF2_Pos (6U)
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+#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
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+#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
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+#define DMA_ISR_TEIF2_Pos (7U)
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+#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
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+#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
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+#define DMA_ISR_GIF3_Pos (8U)
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+#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
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+#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
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+#define DMA_ISR_TCIF3_Pos (9U)
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+#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
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+#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
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+#define DMA_ISR_HTIF3_Pos (10U)
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+#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
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+#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
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+#define DMA_ISR_TEIF3_Pos (11U)
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+#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
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+#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
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+#define DMA_ISR_GIF4_Pos (12U)
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+#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
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+#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
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+#define DMA_ISR_TCIF4_Pos (13U)
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+#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
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+#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
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+#define DMA_ISR_HTIF4_Pos (14U)
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+#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
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+#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
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+#define DMA_ISR_TEIF4_Pos (15U)
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+#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
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+#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
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+#define DMA_ISR_GIF5_Pos (16U)
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+#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
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+#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
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+#define DMA_ISR_TCIF5_Pos (17U)
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+#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
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+#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
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+#define DMA_ISR_HTIF5_Pos (18U)
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+#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
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+#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
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+#define DMA_ISR_TEIF5_Pos (19U)
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+#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
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+#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
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+#define DMA_ISR_GIF6_Pos (20U)
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+#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
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+#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
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+#define DMA_ISR_TCIF6_Pos (21U)
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+#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
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+#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
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+#define DMA_ISR_HTIF6_Pos (22U)
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+#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
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+#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
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+#define DMA_ISR_TEIF6_Pos (23U)
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+#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
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+#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
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+#define DMA_ISR_GIF7_Pos (24U)
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+#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
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+#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
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+#define DMA_ISR_TCIF7_Pos (25U)
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+#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
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+#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
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+#define DMA_ISR_HTIF7_Pos (26U)
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+#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
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+#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
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+#define DMA_ISR_TEIF7_Pos (27U)
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+#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
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+#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
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+
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+/******************* Bit definition for DMA_IFCR register *******************/
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+#define DMA_IFCR_CGIF1_Pos (0U)
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+#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
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+#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */
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+#define DMA_IFCR_CTCIF1_Pos (1U)
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+#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
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+#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
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+#define DMA_IFCR_CHTIF1_Pos (2U)
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+#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
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+#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
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+#define DMA_IFCR_CTEIF1_Pos (3U)
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+#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
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+#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
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+#define DMA_IFCR_CGIF2_Pos (4U)
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+#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
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+#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
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+#define DMA_IFCR_CTCIF2_Pos (5U)
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+#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
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+#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
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+#define DMA_IFCR_CHTIF2_Pos (6U)
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+#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
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+#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
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+#define DMA_IFCR_CTEIF2_Pos (7U)
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+#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
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+#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
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+#define DMA_IFCR_CGIF3_Pos (8U)
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+#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
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+#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
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+#define DMA_IFCR_CTCIF3_Pos (9U)
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+#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
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+#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
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+#define DMA_IFCR_CHTIF3_Pos (10U)
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+#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
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+#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
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+#define DMA_IFCR_CTEIF3_Pos (11U)
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+#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
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+#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
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+#define DMA_IFCR_CGIF4_Pos (12U)
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+#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
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+#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
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+#define DMA_IFCR_CTCIF4_Pos (13U)
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+#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
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+#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
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+#define DMA_IFCR_CHTIF4_Pos (14U)
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+#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
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+#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
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+#define DMA_IFCR_CTEIF4_Pos (15U)
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+#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
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+#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
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+#define DMA_IFCR_CGIF5_Pos (16U)
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+#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
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+#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
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+#define DMA_IFCR_CTCIF5_Pos (17U)
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+#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
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+#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
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+#define DMA_IFCR_CHTIF5_Pos (18U)
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+#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
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+#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
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+#define DMA_IFCR_CTEIF5_Pos (19U)
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+#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
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+#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
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+#define DMA_IFCR_CGIF6_Pos (20U)
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+#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
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+#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
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+#define DMA_IFCR_CTCIF6_Pos (21U)
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+#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
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+#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
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+#define DMA_IFCR_CHTIF6_Pos (22U)
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+#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
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+#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
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+#define DMA_IFCR_CTEIF6_Pos (23U)
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+#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
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+#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
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+#define DMA_IFCR_CGIF7_Pos (24U)
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+#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
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+#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
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+#define DMA_IFCR_CTCIF7_Pos (25U)
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+#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
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+#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
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+#define DMA_IFCR_CHTIF7_Pos (26U)
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+#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
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+#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
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+#define DMA_IFCR_CTEIF7_Pos (27U)
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+#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
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+#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
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+
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+/******************* Bit definition for DMA_CCR register ********************/
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+#define DMA_CCR_EN_Pos (0U)
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+#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */
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+#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
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+#define DMA_CCR_TCIE_Pos (1U)
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+#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
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+#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
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+#define DMA_CCR_HTIE_Pos (2U)
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+#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
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+#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
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+#define DMA_CCR_TEIE_Pos (3U)
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+#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
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+#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
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+#define DMA_CCR_DIR_Pos (4U)
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+#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
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+#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
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+#define DMA_CCR_CIRC_Pos (5U)
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+#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
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+#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
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+#define DMA_CCR_PINC_Pos (6U)
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|
+#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
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+#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
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+#define DMA_CCR_MINC_Pos (7U)
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+#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
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+#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
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+
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|
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+#define DMA_CCR_PSIZE_Pos (8U)
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+#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
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+#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
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+#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
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+#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
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+
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|
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+#define DMA_CCR_MSIZE_Pos (10U)
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+#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
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+#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
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+#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
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+#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
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+
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|
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+#define DMA_CCR_PL_Pos (12U)
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+#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */
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+#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
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+#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */
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+#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */
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+
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|
|
+#define DMA_CCR_MEM2MEM_Pos (14U)
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+#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
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+#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
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+
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+/****************** Bit definition for DMA_CNDTR register *******************/
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+#define DMA_CNDTR_NDT_Pos (0U)
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+#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
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+#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
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+
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+/****************** Bit definition for DMA_CPAR register ********************/
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+#define DMA_CPAR_PA_Pos (0U)
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+#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
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+#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
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+
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+/****************** Bit definition for DMA_CMAR register ********************/
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+#define DMA_CMAR_MA_Pos (0U)
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+#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
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+#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
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+
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+/******************************************************************************/
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|
+/* */
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|
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+/* DMAMUX Controller */
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+/* */
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+/******************************************************************************/
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+/******************** Bits definition for DMAMUX_CxCR register **************/
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+#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
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+#define DMAMUX_CxCR_DMAREQ_ID_Msk (0x3FUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x0000003F */
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+#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk /*!< DMA Request ID */
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+#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */
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+#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */
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+#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */
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+#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */
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+#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */
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+#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */
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+#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */
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+#define DMAMUX_CxCR_SOIE_Pos (8U)
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+#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */
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+#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */
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+#define DMAMUX_CxCR_EGE_Pos (9U)
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+#define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos) /*!< 0x00000200 */
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+#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk /*!< Event generation interrupt enable */
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+#define DMAMUX_CxCR_SE_Pos (16U)
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+#define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos) /*!< 0x00010000 */
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+#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk /*!< Synchronization enable */
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+#define DMAMUX_CxCR_SPOL_Pos (17U)
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+#define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */
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+#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk /*!< Synchronization polarity */
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+#define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */
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+#define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */
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+#define DMAMUX_CxCR_NBREQ_Pos (19U)
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+#define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */
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+#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk /*!< Number of request */
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+#define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */
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+#define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */
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+#define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */
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+#define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */
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+#define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */
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+#define DMAMUX_CxCR_SYNC_ID_Pos (24U)
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+#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */
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+#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk /*!< Synchronization ID */
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+#define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */
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+#define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */
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+#define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */
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+#define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */
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+#define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */
|
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+
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|
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+/******************* Bits definition for DMAMUX_CSR register **************/
|
|
|
+#define DMAMUX_CSR_SOF0_Pos (0U)
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+#define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */
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|
+#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk /*!< Synchronization Overrun Flag 0 */
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+#define DMAMUX_CSR_SOF1_Pos (1U)
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+#define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */
|
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+#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk /*!< Synchronization Overrun Flag 1 */
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+#define DMAMUX_CSR_SOF2_Pos (2U)
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+#define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */
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|
+#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk /*!< Synchronization Overrun Flag 2 */
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+#define DMAMUX_CSR_SOF3_Pos (3U)
|
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|
+#define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos) /*!< 0x00000008 */
|
|
|
+#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk /*!< Synchronization Overrun Flag 3 */
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+#define DMAMUX_CSR_SOF4_Pos (4U)
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+#define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos) /*!< 0x00000010 */
|
|
|
+#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk /*!< Synchronization Overrun Flag 4 */
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|
|
+#define DMAMUX_CSR_SOF5_Pos (5U)
|
|
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+#define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos) /*!< 0x00000020 */
|
|
|
+#define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk /*!< Synchronization Overrun Flag 5 */
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|
+#define DMAMUX_CSR_SOF6_Pos (6U)
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|
+#define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos) /*!< 0x00000040 */
|
|
|
+#define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk /*!< Synchronization Overrun Flag 6 */
|
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|
+
|
|
|
+/******************** Bits definition for DMAMUX_CFR register **************/
|
|
|
+#define DMAMUX_CFR_CSOF0_Pos (0U)
|
|
|
+#define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */
|
|
|
+#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk /*!< Clear Overrun Flag 0 */
|
|
|
+#define DMAMUX_CFR_CSOF1_Pos (1U)
|
|
|
+#define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */
|
|
|
+#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk /*!< Clear Overrun Flag 1 */
|
|
|
+#define DMAMUX_CFR_CSOF2_Pos (2U)
|
|
|
+#define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */
|
|
|
+#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk /*!< Clear Overrun Flag 2 */
|
|
|
+#define DMAMUX_CFR_CSOF3_Pos (3U)
|
|
|
+#define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */
|
|
|
+#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk /*!< Clear Overrun Flag 3 */
|
|
|
+#define DMAMUX_CFR_CSOF4_Pos (4U)
|
|
|
+#define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */
|
|
|
+#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk /*!< Clear Overrun Flag 4 */
|
|
|
+#define DMAMUX_CFR_CSOF5_Pos (5U)
|
|
|
+#define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos) /*!< 0x00000020 */
|
|
|
+#define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk /*!< Clear Overrun Flag 5 */
|
|
|
+#define DMAMUX_CFR_CSOF6_Pos (6U)
|
|
|
+#define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */
|
|
|
+#define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk /*!< Clear Overrun Flag 6 */
|
|
|
+
|
|
|
+/******************** Bits definition for DMAMUX_RGxCR register ************/
|
|
|
+#define DMAMUX_RGxCR_SIG_ID_Pos (0U)
|
|
|
+#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */
|
|
|
+#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk /*!< Signal ID */
|
|
|
+#define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */
|
|
|
+#define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */
|
|
|
+#define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */
|
|
|
+#define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */
|
|
|
+#define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */
|
|
|
+#define DMAMUX_RGxCR_OIE_Pos (8U)
|
|
|
+#define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */
|
|
|
+#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk /*!< Overrun interrupt enable */
|
|
|
+#define DMAMUX_RGxCR_GE_Pos (16U)
|
|
|
+#define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos) /*!< 0x00010000 */
|
|
|
+#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk /*!< Generation enable */
|
|
|
+#define DMAMUX_RGxCR_GPOL_Pos (17U)
|
|
|
+#define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */
|
|
|
+#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk /*!< Generation polarity */
|
|
|
+#define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */
|
|
|
+#define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */
|
|
|
+#define DMAMUX_RGxCR_GNBREQ_Pos (19U)
|
|
|
+#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */
|
|
|
+#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk /*!< Number of request */
|
|
|
+#define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */
|
|
|
+#define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */
|
|
|
+#define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */
|
|
|
+#define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */
|
|
|
+#define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */
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|
|
+
|
|
|
+/******************** Bits definition for DMAMUX_RGSR register **************/
|
|
|
+#define DMAMUX_RGSR_OF0_Pos (0U)
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|
|
+#define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos) /*!< 0x00000001 */
|
|
|
+#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk /*!< Overrun flag 0 */
|
|
|
+#define DMAMUX_RGSR_OF1_Pos (1U)
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|
|
+#define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos) /*!< 0x00000002 */
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|
|
+#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk /*!< Overrun flag 1 */
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|
|
+#define DMAMUX_RGSR_OF2_Pos (2U)
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|
|
+#define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos) /*!< 0x00000004 */
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|
|
+#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk /*!< Overrun flag 2 */
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|
|
+#define DMAMUX_RGSR_OF3_Pos (3U)
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|
|
+#define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos) /*!< 0x00000008 */
|
|
|
+#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk /*!< Overrun flag 3 */
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|
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+
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|
|
+/******************** Bits definition for DMAMUX_RGCFR register **************/
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|
|
+#define DMAMUX_RGCFR_COF0_Pos (0U)
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|
|
+#define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */
|
|
|
+#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk /*!< Clear Overrun flag 0 */
|
|
|
+#define DMAMUX_RGCFR_COF1_Pos (1U)
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|
|
+#define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */
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|
|
+#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk /*!< Clear Overrun flag 1 */
|
|
|
+#define DMAMUX_RGCFR_COF2_Pos (2U)
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|
|
+#define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */
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|
|
+#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk /*!< Clear Overrun flag 2 */
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|
|
+#define DMAMUX_RGCFR_COF3_Pos (3U)
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|
|
+#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */
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|
|
+#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Clear Overrun flag 3 */
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|
|
+
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|
|
+/******************************************************************************/
|
|
|
+/* */
|
|
|
+/* External Interrupt/Event Controller */
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|
|
+/* */
|
|
|
+/******************************************************************************/
|
|
|
+/****************** Bit definition for EXTI_RTSR1 register ******************/
|
|
|
+#define EXTI_RTSR1_RT0_Pos (0U)
|
|
|
+#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */
|
|
|
+#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger configuration for input line 0 */
|
|
|
+#define EXTI_RTSR1_RT1_Pos (1U)
|
|
|
+#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */
|
|
|
+#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger configuration for input line 1 */
|
|
|
+#define EXTI_RTSR1_RT2_Pos (2U)
|
|
|
+#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */
|
|
|
+#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger configuration for input line 2 */
|
|
|
+#define EXTI_RTSR1_RT3_Pos (3U)
|
|
|
+#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */
|
|
|
+#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger configuration for input line 3 */
|
|
|
+#define EXTI_RTSR1_RT4_Pos (4U)
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|
|
+#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */
|
|
|
+#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger configuration for input line 4 */
|
|
|
+#define EXTI_RTSR1_RT5_Pos (5U)
|
|
|
+#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */
|
|
|
+#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger configuration for input line 5 */
|
|
|
+#define EXTI_RTSR1_RT6_Pos (6U)
|
|
|
+#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */
|
|
|
+#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger configuration for input line 6 */
|
|
|
+#define EXTI_RTSR1_RT7_Pos (7U)
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|
|
+#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */
|
|
|
+#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger configuration for input line 7 */
|
|
|
+#define EXTI_RTSR1_RT8_Pos (8U)
|
|
|
+#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */
|
|
|
+#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger configuration for input line 8 */
|
|
|
+#define EXTI_RTSR1_RT9_Pos (9U)
|
|
|
+#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */
|
|
|
+#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger configuration for input line 9 */
|
|
|
+#define EXTI_RTSR1_RT10_Pos (10U)
|
|
|
+#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */
|
|
|
+#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger configuration for input line 10 */
|
|
|
+#define EXTI_RTSR1_RT11_Pos (11U)
|
|
|
+#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */
|
|
|
+#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger configuration for input line 11 */
|
|
|
+#define EXTI_RTSR1_RT12_Pos (12U)
|
|
|
+#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */
|
|
|
+#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger configuration for input line 12 */
|
|
|
+#define EXTI_RTSR1_RT13_Pos (13U)
|
|
|
+#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */
|
|
|
+#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger configuration for input line 13 */
|
|
|
+#define EXTI_RTSR1_RT14_Pos (14U)
|
|
|
+#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */
|
|
|
+#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger configuration for input line 14 */
|
|
|
+#define EXTI_RTSR1_RT15_Pos (15U)
|
|
|
+#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */
|
|
|
+#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger configuration for input line 15 */
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|
|
+
|
|
|
+/****************** Bit definition for EXTI_FTSR1 register ******************/
|
|
|
+#define EXTI_FTSR1_FT0_Pos (0U)
|
|
|
+#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */
|
|
|
+#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger configuration for input line 0 */
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|
|
+#define EXTI_FTSR1_FT1_Pos (1U)
|
|
|
+#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */
|
|
|
+#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger configuration for input line 1 */
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|
|
+#define EXTI_FTSR1_FT2_Pos (2U)
|
|
|
+#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */
|
|
|
+#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger configuration for input line 2 */
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|
|
+#define EXTI_FTSR1_FT3_Pos (3U)
|
|
|
+#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */
|
|
|
+#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger configuration for input line 3 */
|
|
|
+#define EXTI_FTSR1_FT4_Pos (4U)
|
|
|
+#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */
|
|
|
+#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger configuration for input line 4 */
|
|
|
+#define EXTI_FTSR1_FT5_Pos (5U)
|
|
|
+#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */
|
|
|
+#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger configuration for input line 5 */
|
|
|
+#define EXTI_FTSR1_FT6_Pos (6U)
|
|
|
+#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */
|
|
|
+#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger configuration for input line 6 */
|
|
|
+#define EXTI_FTSR1_FT7_Pos (7U)
|
|
|
+#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */
|
|
|
+#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger configuration for input line 7 */
|
|
|
+#define EXTI_FTSR1_FT8_Pos (8U)
|
|
|
+#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */
|
|
|
+#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger configuration for input line 8 */
|
|
|
+#define EXTI_FTSR1_FT9_Pos (9U)
|
|
|
+#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */
|
|
|
+#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger configuration for input line 9 */
|
|
|
+#define EXTI_FTSR1_FT10_Pos (10U)
|
|
|
+#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */
|
|
|
+#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger configuration for input line 10 */
|
|
|
+#define EXTI_FTSR1_FT11_Pos (11U)
|
|
|
+#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */
|
|
|
+#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger configuration for input line 11 */
|
|
|
+#define EXTI_FTSR1_FT12_Pos (12U)
|
|
|
+#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */
|
|
|
+#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger configuration for input line 12 */
|
|
|
+#define EXTI_FTSR1_FT13_Pos (13U)
|
|
|
+#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */
|
|
|
+#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger configuration for input line 13 */
|
|
|
+#define EXTI_FTSR1_FT14_Pos (14U)
|
|
|
+#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */
|
|
|
+#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger configuration for input line 14 */
|
|
|
+#define EXTI_FTSR1_FT15_Pos (15U)
|
|
|
+#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */
|
|
|
+#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger configuration for input line 15 */
|
|
|
+
|
|
|
+/****************** Bit definition for EXTI_SWIER1 register *****************/
|
|
|
+#define EXTI_SWIER1_SWI0_Pos (0U)
|
|
|
+#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */
|
|
|
+#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */
|
|
|
+#define EXTI_SWIER1_SWI1_Pos (1U)
|
|
|
+#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */
|
|
|
+#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */
|
|
|
+#define EXTI_SWIER1_SWI2_Pos (2U)
|
|
|
+#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */
|
|
|
+#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */
|
|
|
+#define EXTI_SWIER1_SWI3_Pos (3U)
|
|
|
+#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */
|
|
|
+#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */
|
|
|
+#define EXTI_SWIER1_SWI4_Pos (4U)
|
|
|
+#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */
|
|
|
+#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */
|
|
|
+#define EXTI_SWIER1_SWI5_Pos (5U)
|
|
|
+#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */
|
|
|
+#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */
|
|
|
+#define EXTI_SWIER1_SWI6_Pos (6U)
|
|
|
+#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */
|
|
|
+#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */
|
|
|
+#define EXTI_SWIER1_SWI7_Pos (7U)
|
|
|
+#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */
|
|
|
+#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */
|
|
|
+#define EXTI_SWIER1_SWI8_Pos (8U)
|
|
|
+#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */
|
|
|
+#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */
|
|
|
+#define EXTI_SWIER1_SWI9_Pos (9U)
|
|
|
+#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */
|
|
|
+#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */
|
|
|
+#define EXTI_SWIER1_SWI10_Pos (10U)
|
|
|
+#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */
|
|
|
+#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */
|
|
|
+#define EXTI_SWIER1_SWI11_Pos (11U)
|
|
|
+#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */
|
|
|
+#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */
|
|
|
+#define EXTI_SWIER1_SWI12_Pos (12U)
|
|
|
+#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */
|
|
|
+#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */
|
|
|
+#define EXTI_SWIER1_SWI13_Pos (13U)
|
|
|
+#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */
|
|
|
+#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */
|
|
|
+#define EXTI_SWIER1_SWI14_Pos (14U)
|
|
|
+#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */
|
|
|
+#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */
|
|
|
+#define EXTI_SWIER1_SWI15_Pos (15U)
|
|
|
+#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */
|
|
|
+#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */
|
|
|
+
|
|
|
+/******************* Bit definition for EXTI_RPR1 register ******************/
|
|
|
+#define EXTI_RPR1_RPIF0_Pos (0U)
|
|
|
+#define EXTI_RPR1_RPIF0_Msk (0x1UL << EXTI_RPR1_RPIF0_Pos) /*!< 0x00000001 */
|
|
|
+#define EXTI_RPR1_RPIF0 EXTI_RPR1_RPIF0_Msk /*!< Rising Pending Interrupt Flag on line 0 */
|
|
|
+#define EXTI_RPR1_RPIF1_Pos (1U)
|
|
|
+#define EXTI_RPR1_RPIF1_Msk (0x1UL << EXTI_RPR1_RPIF1_Pos) /*!< 0x00000002 */
|
|
|
+#define EXTI_RPR1_RPIF1 EXTI_RPR1_RPIF1_Msk /*!< Rising Pending Interrupt Flag on line 1 */
|
|
|
+#define EXTI_RPR1_RPIF2_Pos (2U)
|
|
|
+#define EXTI_RPR1_RPIF2_Msk (0x1UL << EXTI_RPR1_RPIF2_Pos) /*!< 0x00000004 */
|
|
|
+#define EXTI_RPR1_RPIF2 EXTI_RPR1_RPIF2_Msk /*!< Rising Pending Interrupt Flag on line 2 */
|
|
|
+#define EXTI_RPR1_RPIF3_Pos (3U)
|
|
|
+#define EXTI_RPR1_RPIF3_Msk (0x1UL << EXTI_RPR1_RPIF3_Pos) /*!< 0x00000008 */
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+#define EXTI_RPR1_RPIF3 EXTI_RPR1_RPIF3_Msk /*!< Rising Pending Interrupt Flag on line 3 */
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+#define EXTI_RPR1_RPIF4_Pos (4U)
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+#define EXTI_RPR1_RPIF4_Msk (0x1UL << EXTI_RPR1_RPIF4_Pos) /*!< 0x00000010 */
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+#define EXTI_RPR1_RPIF4 EXTI_RPR1_RPIF4_Msk /*!< Rising Pending Interrupt Flag on line 4 */
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+#define EXTI_RPR1_RPIF5_Pos (5U)
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+#define EXTI_RPR1_RPIF5_Msk (0x1UL << EXTI_RPR1_RPIF5_Pos) /*!< 0x00000020 */
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+#define EXTI_RPR1_RPIF5 EXTI_RPR1_RPIF5_Msk /*!< Rising Pending Interrupt Flag on line 5 */
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+#define EXTI_RPR1_RPIF6_Pos (6U)
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+#define EXTI_RPR1_RPIF6_Msk (0x1UL << EXTI_RPR1_RPIF6_Pos) /*!< 0x00000040 */
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+#define EXTI_RPR1_RPIF6 EXTI_RPR1_RPIF6_Msk /*!< Rising Pending Interrupt Flag on line 6 */
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+#define EXTI_RPR1_RPIF7_Pos (7U)
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+#define EXTI_RPR1_RPIF7_Msk (0x1UL << EXTI_RPR1_RPIF7_Pos) /*!< 0x00000080 */
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+#define EXTI_RPR1_RPIF7 EXTI_RPR1_RPIF7_Msk /*!< Rising Pending Interrupt Flag on line 7 */
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+#define EXTI_RPR1_RPIF8_Pos (8U)
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+#define EXTI_RPR1_RPIF8_Msk (0x1UL << EXTI_RPR1_RPIF8_Pos) /*!< 0x00000100 */
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+#define EXTI_RPR1_RPIF8 EXTI_RPR1_RPIF8_Msk /*!< Rising Pending Interrupt Flag on line 8 */
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+#define EXTI_RPR1_RPIF9_Pos (9U)
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+#define EXTI_RPR1_RPIF9_Msk (0x1UL << EXTI_RPR1_RPIF9_Pos) /*!< 0x00000200 */
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+#define EXTI_RPR1_RPIF9 EXTI_RPR1_RPIF9_Msk /*!< Rising Pending Interrupt Flag on line 9 */
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+#define EXTI_RPR1_RPIF10_Pos (10U)
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+#define EXTI_RPR1_RPIF10_Msk (0x1UL << EXTI_RPR1_RPIF10_Pos) /*!< 0x00000400 */
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+#define EXTI_RPR1_RPIF10 EXTI_RPR1_RPIF10_Msk /*!< Rising Pending Interrupt Flag on line 10 */
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+#define EXTI_RPR1_RPIF11_Pos (11U)
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+#define EXTI_RPR1_RPIF11_Msk (0x1UL << EXTI_RPR1_RPIF11_Pos) /*!< 0x00000800 */
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+#define EXTI_RPR1_RPIF11 EXTI_RPR1_RPIF11_Msk /*!< Rising Pending Interrupt Flag on line 11 */
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+#define EXTI_RPR1_RPIF12_Pos (12U)
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+#define EXTI_RPR1_RPIF12_Msk (0x1UL << EXTI_RPR1_RPIF12_Pos) /*!< 0x00001000 */
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+#define EXTI_RPR1_RPIF12 EXTI_RPR1_RPIF12_Msk /*!< Rising Pending Interrupt Flag on line 12 */
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+#define EXTI_RPR1_RPIF13_Pos (13U)
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+#define EXTI_RPR1_RPIF13_Msk (0x1UL << EXTI_RPR1_RPIF13_Pos) /*!< 0x00002000 */
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+#define EXTI_RPR1_RPIF13 EXTI_RPR1_RPIF13_Msk /*!< Rising Pending Interrupt Flag on line 13 */
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+#define EXTI_RPR1_RPIF14_Pos (14U)
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+#define EXTI_RPR1_RPIF14_Msk (0x1UL << EXTI_RPR1_RPIF14_Pos) /*!< 0x00004000 */
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+#define EXTI_RPR1_RPIF14 EXTI_RPR1_RPIF14_Msk /*!< Rising Pending Interrupt Flag on line 14 */
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+#define EXTI_RPR1_RPIF15_Pos (15U)
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+#define EXTI_RPR1_RPIF15_Msk (0x1UL << EXTI_RPR1_RPIF15_Pos) /*!< 0x00008000 */
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+#define EXTI_RPR1_RPIF15 EXTI_RPR1_RPIF15_Msk /*!< Rising Pending Interrupt Flag on line 15 */
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+
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+/******************* Bit definition for EXTI_FPR1 register ******************/
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+#define EXTI_FPR1_FPIF0_Pos (0U)
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+#define EXTI_FPR1_FPIF0_Msk (0x1UL << EXTI_FPR1_FPIF0_Pos) /*!< 0x00000001 */
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+#define EXTI_FPR1_FPIF0 EXTI_FPR1_FPIF0_Msk /*!< Falling Pending Interrupt Flag on line 0 */
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+#define EXTI_FPR1_FPIF1_Pos (1U)
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+#define EXTI_FPR1_FPIF1_Msk (0x1UL << EXTI_FPR1_FPIF1_Pos) /*!< 0x00000002 */
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+#define EXTI_FPR1_FPIF1 EXTI_FPR1_FPIF1_Msk /*!< Falling Pending Interrupt Flag on line 1 */
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+#define EXTI_FPR1_FPIF2_Pos (2U)
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+#define EXTI_FPR1_FPIF2_Msk (0x1UL << EXTI_FPR1_FPIF2_Pos) /*!< 0x00000004 */
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+#define EXTI_FPR1_FPIF2 EXTI_FPR1_FPIF2_Msk /*!< Falling Pending Interrupt Flag on line 2 */
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+#define EXTI_FPR1_FPIF3_Pos (3U)
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+#define EXTI_FPR1_FPIF3_Msk (0x1UL << EXTI_FPR1_FPIF3_Pos) /*!< 0x00000008 */
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+#define EXTI_FPR1_FPIF3 EXTI_FPR1_FPIF3_Msk /*!< Falling Pending Interrupt Flag on line 3 */
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+#define EXTI_FPR1_FPIF4_Pos (4U)
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+#define EXTI_FPR1_FPIF4_Msk (0x1UL << EXTI_FPR1_FPIF4_Pos) /*!< 0x00000010 */
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+#define EXTI_FPR1_FPIF4 EXTI_FPR1_FPIF4_Msk /*!< Falling Pending Interrupt Flag on line 4 */
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+#define EXTI_FPR1_FPIF5_Pos (5U)
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+#define EXTI_FPR1_FPIF5_Msk (0x1UL << EXTI_FPR1_FPIF5_Pos) /*!< 0x00000020 */
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+#define EXTI_FPR1_FPIF5 EXTI_FPR1_FPIF5_Msk /*!< Falling Pending Interrupt Flag on line 5 */
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+#define EXTI_FPR1_FPIF6_Pos (6U)
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+#define EXTI_FPR1_FPIF6_Msk (0x1UL << EXTI_FPR1_FPIF6_Pos) /*!< 0x00000040 */
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+#define EXTI_FPR1_FPIF6 EXTI_FPR1_FPIF6_Msk /*!< Falling Pending Interrupt Flag on line 6 */
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+#define EXTI_FPR1_FPIF7_Pos (7U)
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+#define EXTI_FPR1_FPIF7_Msk (0x1UL << EXTI_FPR1_FPIF7_Pos) /*!< 0x00000080 */
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+#define EXTI_FPR1_FPIF7 EXTI_FPR1_FPIF7_Msk /*!< Falling Pending Interrupt Flag on line 7 */
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+#define EXTI_FPR1_FPIF8_Pos (8U)
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+#define EXTI_FPR1_FPIF8_Msk (0x1UL << EXTI_FPR1_FPIF8_Pos) /*!< 0x00000100 */
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+#define EXTI_FPR1_FPIF8 EXTI_FPR1_FPIF8_Msk /*!< Falling Pending Interrupt Flag on line 8 */
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+#define EXTI_FPR1_FPIF9_Pos (9U)
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+#define EXTI_FPR1_FPIF9_Msk (0x1UL << EXTI_FPR1_FPIF9_Pos) /*!< 0x00000200 */
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+#define EXTI_FPR1_FPIF9 EXTI_FPR1_FPIF9_Msk /*!< Falling Pending Interrupt Flag on line 9 */
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+#define EXTI_FPR1_FPIF10_Pos (10U)
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+#define EXTI_FPR1_FPIF10_Msk (0x1UL << EXTI_FPR1_FPIF10_Pos) /*!< 0x00000400 */
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+#define EXTI_FPR1_FPIF10 EXTI_FPR1_FPIF10_Msk /*!< Falling Pending Interrupt Flag on line 10 */
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+#define EXTI_FPR1_FPIF11_Pos (11U)
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+#define EXTI_FPR1_FPIF11_Msk (0x1UL << EXTI_FPR1_FPIF11_Pos) /*!< 0x00000800 */
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+#define EXTI_FPR1_FPIF11 EXTI_FPR1_FPIF11_Msk /*!< Falling Pending Interrupt Flag on line 11 */
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+#define EXTI_FPR1_FPIF12_Pos (12U)
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+#define EXTI_FPR1_FPIF12_Msk (0x1UL << EXTI_FPR1_FPIF12_Pos) /*!< 0x00001000 */
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+#define EXTI_FPR1_FPIF12 EXTI_FPR1_FPIF12_Msk /*!< Falling Pending Interrupt Flag on line 12 */
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+#define EXTI_FPR1_FPIF13_Pos (13U)
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+#define EXTI_FPR1_FPIF13_Msk (0x1UL << EXTI_FPR1_FPIF13_Pos) /*!< 0x00002000 */
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+#define EXTI_FPR1_FPIF13 EXTI_FPR1_FPIF13_Msk /*!< Falling Pending Interrupt Flag on line 13 */
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+#define EXTI_FPR1_FPIF14_Pos (14U)
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+#define EXTI_FPR1_FPIF14_Msk (0x1UL << EXTI_FPR1_FPIF14_Pos) /*!< 0x00004000 */
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+#define EXTI_FPR1_FPIF14 EXTI_FPR1_FPIF14_Msk /*!< Falling Pending Interrupt Flag on line 14 */
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+#define EXTI_FPR1_FPIF15_Pos (15U)
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+#define EXTI_FPR1_FPIF15_Msk (0x1UL << EXTI_FPR1_FPIF15_Pos) /*!< 0x00008000 */
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+#define EXTI_FPR1_FPIF15 EXTI_FPR1_FPIF15_Msk /*!< Falling Pending Interrupt Flag on line 15 */
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+
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+/***************** Bit definition for EXTI_EXTICR1 register **************/
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+#define EXTI_EXTICR1_EXTI0_Pos (0U)
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+#define EXTI_EXTICR1_EXTI0_Msk (0x7UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000007 */
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+#define EXTI_EXTICR1_EXTI0 EXTI_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
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+#define EXTI_EXTICR1_EXTI0_0 (0x1UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000001 */
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+#define EXTI_EXTICR1_EXTI0_1 (0x2UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000002 */
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+#define EXTI_EXTICR1_EXTI0_2 (0x4UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000004 */
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+#define EXTI_EXTICR1_EXTI1_Pos (8U)
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+#define EXTI_EXTICR1_EXTI1_Msk (0x7UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000700 */
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+#define EXTI_EXTICR1_EXTI1 EXTI_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
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+#define EXTI_EXTICR1_EXTI1_0 (0x1UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000100 */
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+#define EXTI_EXTICR1_EXTI1_1 (0x2UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000200 */
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+#define EXTI_EXTICR1_EXTI1_2 (0x4UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000400 */
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+#define EXTI_EXTICR1_EXTI2_Pos (16U)
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+#define EXTI_EXTICR1_EXTI2_Msk (0x7UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00070000 */
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+#define EXTI_EXTICR1_EXTI2 EXTI_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
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+#define EXTI_EXTICR1_EXTI2_0 (0x1UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00010000 */
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+#define EXTI_EXTICR1_EXTI2_1 (0x2UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00020000 */
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+#define EXTI_EXTICR1_EXTI2_2 (0x4UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00040000 */
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+#define EXTI_EXTICR1_EXTI3_Pos (24U)
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+#define EXTI_EXTICR1_EXTI3_Msk (0x7UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x07000000 */
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+#define EXTI_EXTICR1_EXTI3 EXTI_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
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+#define EXTI_EXTICR1_EXTI3_0 (0x1UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x01000000 */
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+#define EXTI_EXTICR1_EXTI3_1 (0x2UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x02000000 */
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+#define EXTI_EXTICR1_EXTI3_2 (0x4UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x04000000 */
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+
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+/***************** Bit definition for EXTI_EXTICR2 register **************/
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+#define EXTI_EXTICR2_EXTI4_Pos (0U)
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+#define EXTI_EXTICR2_EXTI4_Msk (0x7UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000007 */
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+#define EXTI_EXTICR2_EXTI4 EXTI_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
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+#define EXTI_EXTICR2_EXTI4_0 (0x1UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000001 */
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+#define EXTI_EXTICR2_EXTI4_1 (0x2UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000002 */
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+#define EXTI_EXTICR2_EXTI4_2 (0x4UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000004 */
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+#define EXTI_EXTICR2_EXTI5_Pos (8U)
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+#define EXTI_EXTICR2_EXTI5_Msk (0x7UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000700 */
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+#define EXTI_EXTICR2_EXTI5 EXTI_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
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+#define EXTI_EXTICR2_EXTI5_0 (0x1UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000100 */
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+#define EXTI_EXTICR2_EXTI5_1 (0x2UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000200 */
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+#define EXTI_EXTICR2_EXTI5_2 (0x4UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000400 */
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+#define EXTI_EXTICR2_EXTI6_Pos (16U)
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+#define EXTI_EXTICR2_EXTI6_Msk (0x7UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00070000 */
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+#define EXTI_EXTICR2_EXTI6 EXTI_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
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+#define EXTI_EXTICR2_EXTI6_0 (0x1UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00010000 */
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+#define EXTI_EXTICR2_EXTI6_1 (0x2UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00020000 */
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+#define EXTI_EXTICR2_EXTI6_2 (0x4UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00040000 */
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+#define EXTI_EXTICR2_EXTI7_Pos (24U)
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+#define EXTI_EXTICR2_EXTI7_Msk (0x7UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x07000000 */
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+#define EXTI_EXTICR2_EXTI7 EXTI_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
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+#define EXTI_EXTICR2_EXTI7_0 (0x1UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x01000000 */
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+#define EXTI_EXTICR2_EXTI7_1 (0x2UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x02000000 */
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+#define EXTI_EXTICR2_EXTI7_2 (0x4UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x04000000 */
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+
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+/***************** Bit definition for EXTI_EXTICR3 register **************/
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+#define EXTI_EXTICR3_EXTI8_Pos (0U)
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+#define EXTI_EXTICR3_EXTI8_Msk (0x7UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000007 */
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+#define EXTI_EXTICR3_EXTI8 EXTI_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
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+#define EXTI_EXTICR3_EXTI8_0 (0x1UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000001 */
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+#define EXTI_EXTICR3_EXTI8_1 (0x2UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000002 */
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+#define EXTI_EXTICR3_EXTI8_2 (0x4UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000004 */
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+#define EXTI_EXTICR3_EXTI9_Pos (8U)
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+#define EXTI_EXTICR3_EXTI9_Msk (0x7UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000700 */
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+#define EXTI_EXTICR3_EXTI9 EXTI_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
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+#define EXTI_EXTICR3_EXTI9_0 (0x1UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000100 */
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+#define EXTI_EXTICR3_EXTI9_1 (0x2UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000200 */
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+#define EXTI_EXTICR3_EXTI9_2 (0x4UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000400 */
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+#define EXTI_EXTICR3_EXTI10_Pos (16U)
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+#define EXTI_EXTICR3_EXTI10_Msk (0x7UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00070000 */
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+#define EXTI_EXTICR3_EXTI10 EXTI_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
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+#define EXTI_EXTICR3_EXTI10_0 (0x1UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00010000 */
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+#define EXTI_EXTICR3_EXTI10_1 (0x2UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00020000 */
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+#define EXTI_EXTICR3_EXTI10_2 (0x4UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00040000 */
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+#define EXTI_EXTICR3_EXTI11_Pos (24U)
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+#define EXTI_EXTICR3_EXTI11_Msk (0x7UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x07000000 */
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+#define EXTI_EXTICR3_EXTI11 EXTI_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
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+#define EXTI_EXTICR3_EXTI11_0 (0x1UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x01000000 */
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+#define EXTI_EXTICR3_EXTI11_1 (0x2UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x02000000 */
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+#define EXTI_EXTICR3_EXTI11_2 (0x4UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x04000000 */
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+
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+/***************** Bit definition for EXTI_EXTICR4 register **************/
|
|
|
+#define EXTI_EXTICR4_EXTI12_Pos (0U)
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+#define EXTI_EXTICR4_EXTI12_Msk (0x7UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */
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+#define EXTI_EXTICR4_EXTI12 EXTI_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
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+#define EXTI_EXTICR4_EXTI12_0 (0x1UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000001 */
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+#define EXTI_EXTICR4_EXTI12_1 (0x2UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000002 */
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+#define EXTI_EXTICR4_EXTI12_2 (0x4UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000004 */
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|
+#define EXTI_EXTICR4_EXTI13_Pos (8U)
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+#define EXTI_EXTICR4_EXTI13_Msk (0x7UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000700 */
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|
+#define EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
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|
+#define EXTI_EXTICR4_EXTI13_0 (0x1UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000100 */
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|
+#define EXTI_EXTICR4_EXTI13_1 (0x2UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000200 */
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|
+#define EXTI_EXTICR4_EXTI13_2 (0x4UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000400 */
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|
+#define EXTI_EXTICR4_EXTI14_Pos (16U)
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+#define EXTI_EXTICR4_EXTI14_Msk (0x7UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00070000 */
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|
+#define EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
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+#define EXTI_EXTICR4_EXTI14_0 (0x1UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00010000 */
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+#define EXTI_EXTICR4_EXTI14_1 (0x2UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00020000 */
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+#define EXTI_EXTICR4_EXTI14_2 (0x4UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00040000 */
|
|
|
+#define EXTI_EXTICR4_EXTI15_Pos (24U)
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|
|
+#define EXTI_EXTICR4_EXTI15_Msk (0x7UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x07000000 */
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|
|
+#define EXTI_EXTICR4_EXTI15 EXTI_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
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|
|
+#define EXTI_EXTICR4_EXTI15_0 (0x1UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x01000000 */
|
|
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+#define EXTI_EXTICR4_EXTI15_1 (0x2UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x02000000 */
|
|
|
+#define EXTI_EXTICR4_EXTI15_2 (0x4UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x04000000 */
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|
|
+
|
|
|
+/******************* Bit definition for EXTI_IMR1 register ******************/
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|
|
+#define EXTI_IMR1_IM0_Pos (0U)
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|
|
+#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */
|
|
|
+#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */
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|
|
+#define EXTI_IMR1_IM1_Pos (1U)
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|
|
+#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */
|
|
|
+#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */
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|
|
+#define EXTI_IMR1_IM2_Pos (2U)
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|
|
+#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */
|
|
|
+#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */
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|
|
+#define EXTI_IMR1_IM3_Pos (3U)
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|
|
+#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */
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|
|
+#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */
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|
|
+#define EXTI_IMR1_IM4_Pos (4U)
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|
|
+#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */
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|
|
+#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */
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|
|
+#define EXTI_IMR1_IM5_Pos (5U)
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|
|
+#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */
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|
|
+#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */
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|
|
+#define EXTI_IMR1_IM6_Pos (6U)
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|
|
+#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */
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|
|
+#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */
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|
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+#define EXTI_IMR1_IM7_Pos (7U)
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|
+#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */
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|
|
+#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */
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|
|
+#define EXTI_IMR1_IM8_Pos (8U)
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|
|
+#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */
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|
|
+#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */
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|
|
+#define EXTI_IMR1_IM9_Pos (9U)
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|
+#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */
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|
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+#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */
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|
|
+#define EXTI_IMR1_IM10_Pos (10U)
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|
+#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */
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|
|
+#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */
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|
|
+#define EXTI_IMR1_IM11_Pos (11U)
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|
|
+#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */
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|
|
+#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */
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|
|
+#define EXTI_IMR1_IM12_Pos (12U)
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|
|
+#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */
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|
|
+#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */
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|
|
+#define EXTI_IMR1_IM13_Pos (13U)
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|
+#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */
|
|
|
+#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */
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|
|
+#define EXTI_IMR1_IM14_Pos (14U)
|
|
|
+#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */
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|
|
+#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */
|
|
|
+#define EXTI_IMR1_IM15_Pos (15U)
|
|
|
+#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */
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|
|
+#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */
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|
+#define EXTI_IMR1_IM19_Pos (19U)
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|
|
+#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
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|
|
+#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */
|
|
|
+#define EXTI_IMR1_IM21_Pos (21U)
|
|
|
+#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */
|
|
|
+#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */
|
|
|
+#define EXTI_IMR1_IM23_Pos (23U)
|
|
|
+#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
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|
|
+#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */
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|
|
+#define EXTI_IMR1_IM25_Pos (25U)
|
|
|
+#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
|
|
|
+#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */
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|
|
+#define EXTI_IMR1_IM31_Pos (31U)
|
|
|
+#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */
|
|
|
+#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */
|
|
|
+#define EXTI_IMR1_IM_Pos (0U)
|
|
|
+#define EXTI_IMR1_IM_Msk (0x82A8FFFFUL << EXTI_IMR1_IM_Pos) /*!< 0x82A8FFFF */
|
|
|
+#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */
|
|
|
+
|
|
|
+
|
|
|
+/******************* Bit definition for EXTI_EMR1 register ******************/
|
|
|
+#define EXTI_EMR1_EM0_Pos (0U)
|
|
|
+#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */
|
|
|
+#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */
|
|
|
+#define EXTI_EMR1_EM1_Pos (1U)
|
|
|
+#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */
|
|
|
+#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */
|
|
|
+#define EXTI_EMR1_EM2_Pos (2U)
|
|
|
+#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */
|
|
|
+#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */
|
|
|
+#define EXTI_EMR1_EM3_Pos (3U)
|
|
|
+#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */
|
|
|
+#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */
|
|
|
+#define EXTI_EMR1_EM4_Pos (4U)
|
|
|
+#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */
|
|
|
+#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */
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|
|
+#define EXTI_EMR1_EM5_Pos (5U)
|
|
|
+#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */
|
|
|
+#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */
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|
|
+#define EXTI_EMR1_EM6_Pos (6U)
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|
|
+#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */
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|
|
+#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */
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|
+#define EXTI_EMR1_EM7_Pos (7U)
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|
|
+#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */
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|
|
+#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */
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|
|
+#define EXTI_EMR1_EM8_Pos (8U)
|
|
|
+#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */
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|
|
+#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */
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|
|
+#define EXTI_EMR1_EM9_Pos (9U)
|
|
|
+#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */
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|
|
+#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */
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|
|
+#define EXTI_EMR1_EM10_Pos (10U)
|
|
|
+#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */
|
|
|
+#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */
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|
|
+#define EXTI_EMR1_EM11_Pos (11U)
|
|
|
+#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */
|
|
|
+#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */
|
|
|
+#define EXTI_EMR1_EM12_Pos (12U)
|
|
|
+#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */
|
|
|
+#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */
|
|
|
+#define EXTI_EMR1_EM13_Pos (13U)
|
|
|
+#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */
|
|
|
+#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */
|
|
|
+#define EXTI_EMR1_EM14_Pos (14U)
|
|
|
+#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */
|
|
|
+#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */
|
|
|
+#define EXTI_EMR1_EM15_Pos (15U)
|
|
|
+#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */
|
|
|
+#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */
|
|
|
+#define EXTI_EMR1_EM19_Pos (19U)
|
|
|
+#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */
|
|
|
+#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */
|
|
|
+#define EXTI_EMR1_EM21_Pos (21U)
|
|
|
+#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */
|
|
|
+#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */
|
|
|
+#define EXTI_EMR1_EM23_Pos (23U)
|
|
|
+#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */
|
|
|
+#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */
|
|
|
+#define EXTI_EMR1_EM25_Pos (25U)
|
|
|
+#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */
|
|
|
+#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */
|
|
|
+#define EXTI_EMR1_EM31_Pos (31U)
|
|
|
+#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */
|
|
|
+#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
|
|
|
+
|
|
|
+
|
|
|
+/******************************************************************************/
|
|
|
+/* */
|
|
|
+/* FLASH */
|
|
|
+/* */
|
|
|
+/******************************************************************************/
|
|
|
+/* Note: No specific macro feature on this device */
|
|
|
+
|
|
|
+/******************* Bits definition for FLASH_ACR register *****************/
|
|
|
+#define FLASH_ACR_LATENCY_Pos (0U)
|
|
|
+#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
|
|
|
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
|
|
|
+#define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
|
|
|
+#define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */
|
|
|
+#define FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */
|
|
|
+#define FLASH_ACR_PRFTEN_Pos (8U)
|
|
|
+#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
|
|
|
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
|
|
|
+#define FLASH_ACR_ICEN_Pos (9U)
|
|
|
+#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
|
|
|
+#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
|
|
|
+#define FLASH_ACR_ICRST_Pos (11U)
|
|
|
+#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
|
|
|
+#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
|
|
|
+#define FLASH_ACR_PROGEMPTY_Pos (16U)
|
|
|
+#define FLASH_ACR_PROGEMPTY_Msk (0x1UL << FLASH_ACR_PROGEMPTY_Pos) /*!< 0x00010000 */
|
|
|
+#define FLASH_ACR_PROGEMPTY FLASH_ACR_PROGEMPTY_Msk
|
|
|
+
|
|
|
+/******************* Bits definition for FLASH_SR register ******************/
|
|
|
+#define FLASH_SR_EOP_Pos (0U)
|
|
|
+#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
|
|
|
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk
|
|
|
+#define FLASH_SR_OPERR_Pos (1U)
|
|
|
+#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */
|
|
|
+#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
|
|
|
+#define FLASH_SR_PROGERR_Pos (3U)
|
|
|
+#define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */
|
|
|
+#define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk
|
|
|
+#define FLASH_SR_WRPERR_Pos (4U)
|
|
|
+#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
|
|
|
+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
|
|
|
+#define FLASH_SR_PGAERR_Pos (5U)
|
|
|
+#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
|
|
|
+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
|
|
|
+#define FLASH_SR_SIZERR_Pos (6U)
|
|
|
+#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */
|
|
|
+#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk
|
|
|
+#define FLASH_SR_PGSERR_Pos (7U)
|
|
|
+#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
|
|
|
+#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
|
|
|
+#define FLASH_SR_MISERR_Pos (8U)
|
|
|
+#define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */
|
|
|
+#define FLASH_SR_MISERR FLASH_SR_MISERR_Msk
|
|
|
+#define FLASH_SR_FASTERR_Pos (9U)
|
|
|
+#define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */
|
|
|
+#define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk
|
|
|
+#define FLASH_SR_OPTVERR_Pos (15U)
|
|
|
+#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */
|
|
|
+#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk
|
|
|
+#define FLASH_SR_BSY1_Pos (16U)
|
|
|
+#define FLASH_SR_BSY1_Msk (0x1UL << FLASH_SR_BSY1_Pos) /*!< 0x00010000 */
|
|
|
+#define FLASH_SR_BSY1 FLASH_SR_BSY1_Msk
|
|
|
+#define FLASH_SR_CFGBSY_Pos (18U)
|
|
|
+#define FLASH_SR_CFGBSY_Msk (0x1UL << FLASH_SR_CFGBSY_Pos) /*!< 0x00040000 */
|
|
|
+#define FLASH_SR_CFGBSY FLASH_SR_CFGBSY_Msk
|
|
|
+
|
|
|
+/******************* Bits definition for FLASH_CR register ******************/
|
|
|
+#define FLASH_CR_PG_Pos (0U)
|
|
|
+#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */
|
|
|
+#define FLASH_CR_PG FLASH_CR_PG_Msk
|
|
|
+#define FLASH_CR_PER_Pos (1U)
|
|
|
+#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */
|
|
|
+#define FLASH_CR_PER FLASH_CR_PER_Msk
|
|
|
+#define FLASH_CR_MER1_Pos (2U)
|
|
|
+#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
|
|
|
+#define FLASH_CR_MER1 FLASH_CR_MER1_Msk
|
|
|
+#define FLASH_CR_PNB_Pos (3U)
|
|
|
+#define FLASH_CR_PNB_Msk (0x1FUL << FLASH_CR_PNB_Pos) /*!< 0x000000F8 */
|
|
|
+#define FLASH_CR_PNB FLASH_CR_PNB_Msk
|
|
|
+#define FLASH_CR_STRT_Pos (16U)
|
|
|
+#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
|
|
|
+#define FLASH_CR_STRT FLASH_CR_STRT_Msk
|
|
|
+#define FLASH_CR_OPTSTRT_Pos (17U)
|
|
|
+#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */
|
|
|
+#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk
|
|
|
+#define FLASH_CR_FSTPG_Pos (18U)
|
|
|
+#define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */
|
|
|
+#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk
|
|
|
+#define FLASH_CR_EOPIE_Pos (24U)
|
|
|
+#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
|
|
|
+#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
|
|
|
+#define FLASH_CR_ERRIE_Pos (25U)
|
|
|
+#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */
|
|
|
+#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
|
|
|
+#define FLASH_CR_OBL_LAUNCH_Pos (27U)
|
|
|
+#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
|
|
|
+#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk
|
|
|
+#define FLASH_CR_OPTLOCK_Pos (30U)
|
|
|
+#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */
|
|
|
+#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk
|
|
|
+#define FLASH_CR_LOCK_Pos (31U)
|
|
|
+#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
|
|
|
+#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
|
|
|
+
|
|
|
+/******************* Bits definition for FLASH_ECCR register ****************/
|
|
|
+#define FLASH_ECCR_ADDR_ECC_Pos (0U)
|
|
|
+#define FLASH_ECCR_ADDR_ECC_Msk (0x3FFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x00003FFF */
|
|
|
+#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk
|
|
|
+#define FLASH_ECCR_SYSF_ECC_Pos (20U)
|
|
|
+#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */
|
|
|
+#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk
|
|
|
+#define FLASH_ECCR_ECCCIE_Pos (24U)
|
|
|
+#define FLASH_ECCR_ECCCIE_Msk (0x1UL << FLASH_ECCR_ECCCIE_Pos) /*!< 0x01000000 */
|
|
|
+#define FLASH_ECCR_ECCCIE FLASH_ECCR_ECCCIE_Msk
|
|
|
+#define FLASH_ECCR_ECCC_Pos (30U)
|
|
|
+#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */
|
|
|
+#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk
|
|
|
+#define FLASH_ECCR_ECCD_Pos (31U)
|
|
|
+#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */
|
|
|
+#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk
|
|
|
+
|
|
|
+/******************* Bits definition for FLASH_OPTR register ****************/
|
|
|
+#define FLASH_OPTR_RDP_Pos (0U)
|
|
|
+#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */
|
|
|
+#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk
|
|
|
+#define FLASH_OPTR_nRST_STOP_Pos (13U)
|
|
|
+#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00002000 */
|
|
|
+#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk
|
|
|
+#define FLASH_OPTR_nRST_STDBY_Pos (14U)
|
|
|
+#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00004000 */
|
|
|
+#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk
|
|
|
+#define FLASH_OPTR_IWDG_SW_Pos (16U)
|
|
|
+#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */
|
|
|
+#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk
|
|
|
+#define FLASH_OPTR_IWDG_STOP_Pos (17U)
|
|
|
+#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */
|
|
|
+#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk
|
|
|
+#define FLASH_OPTR_IWDG_STDBY_Pos (18U)
|
|
|
+#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
|
|
|
+#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk
|
|
|
+#define FLASH_OPTR_WWDG_SW_Pos (19U)
|
|
|
+#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */
|
|
|
+#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk
|
|
|
+#define FLASH_OPTR_RAM_PARITY_CHECK_Pos (22U)
|
|
|
+#define FLASH_OPTR_RAM_PARITY_CHECK_Msk (0x1UL << FLASH_OPTR_RAM_PARITY_CHECK_Pos) /*!< 0x00400000 */
|
|
|
+#define FLASH_OPTR_RAM_PARITY_CHECK FLASH_OPTR_RAM_PARITY_CHECK_Msk
|
|
|
+#define FLASH_OPTR_nBOOT_SEL_Pos (24U)
|
|
|
+#define FLASH_OPTR_nBOOT_SEL_Msk (0x1UL << FLASH_OPTR_nBOOT_SEL_Pos) /*!< 0x01000000 */
|
|
|
+#define FLASH_OPTR_nBOOT_SEL FLASH_OPTR_nBOOT_SEL_Msk
|
|
|
+#define FLASH_OPTR_nBOOT1_Pos (25U)
|
|
|
+#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x02000000 */
|
|
|
+#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk
|
|
|
+#define FLASH_OPTR_nBOOT0_Pos (26U)
|
|
|
+#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x04000000 */
|
|
|
+#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk
|
|
|
+
|
|
|
+/****************** Bits definition for FLASH_WRP1AR register ***************/
|
|
|
+#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U)
|
|
|
+#define FLASH_WRP1AR_WRP1A_STRT_Msk (0x1FUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x0000001F */
|
|
|
+#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
|
|
|
+#define FLASH_WRP1AR_WRP1A_END_Pos (16U)
|
|
|
+#define FLASH_WRP1AR_WRP1A_END_Msk (0x1FUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x001F0000 */
|
|
|
+#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk
|
|
|
+
|
|
|
+/****************** Bits definition for FLASH_WRP1BR register ***************/
|
|
|
+#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
|
|
|
+#define FLASH_WRP1BR_WRP1B_STRT_Msk (0x1FUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x0000001F */
|
|
|
+#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
|
|
|
+#define FLASH_WRP1BR_WRP1B_END_Pos (16U)
|
|
|
+#define FLASH_WRP1BR_WRP1B_END_Msk (0x1FUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x001F0000 */
|
|
|
+#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk
|
|
|
+
|
|
|
+
|
|
|
+/******************************************************************************/
|
|
|
+/* */
|
|
|
+/* General Purpose I/O */
|
|
|
+/* */
|
|
|
+/******************************************************************************/
|
|
|
+/****************** Bits definition for GPIO_MODER register *****************/
|
|
|
+#define GPIO_MODER_MODE0_Pos (0U)
|
|
|
+#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
|
|
|
+#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
|
|
|
+#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
|
|
|
+#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
|
|
|
+#define GPIO_MODER_MODE1_Pos (2U)
|
|
|
+#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
|
|
|
+#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
|
|
|
+#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
|
|
|
+#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
|
|
|
+#define GPIO_MODER_MODE2_Pos (4U)
|
|
|
+#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
|
|
|
+#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
|
|
|
+#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
|
|
|
+#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
|
|
|
+#define GPIO_MODER_MODE3_Pos (6U)
|
|
|
+#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
|
|
|
+#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
|
|
|
+#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
|
|
|
+#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
|
|
|
+#define GPIO_MODER_MODE4_Pos (8U)
|
|
|
+#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
|
|
|
+#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
|
|
|
+#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
|
|
|
+#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
|
|
|
+#define GPIO_MODER_MODE5_Pos (10U)
|
|
|
+#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
|
|
|
+#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
|
|
|
+#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
|
|
|
+#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
|
|
|
+#define GPIO_MODER_MODE6_Pos (12U)
|
|
|
+#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
|
|
|
+#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
|
|
|
+#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
|
|
|
+#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
|
|
|
+#define GPIO_MODER_MODE7_Pos (14U)
|
|
|
+#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
|
|
|
+#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
|
|
|
+#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
|
|
|
+#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
|
|
|
+#define GPIO_MODER_MODE8_Pos (16U)
|
|
|
+#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
|
|
|
+#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
|
|
|
+#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
|
|
|
+#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
|
|
|
+#define GPIO_MODER_MODE9_Pos (18U)
|
|
|
+#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
|
|
|
+#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
|
|
|
+#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
|
|
|
+#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
|
|
|
+#define GPIO_MODER_MODE10_Pos (20U)
|
|
|
+#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
|
|
|
+#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
|
|
|
+#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
|
|
|
+#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
|
|
|
+#define GPIO_MODER_MODE11_Pos (22U)
|
|
|
+#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
|
|
|
+#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
|
|
|
+#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
|
|
|
+#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
|
|
|
+#define GPIO_MODER_MODE12_Pos (24U)
|
|
|
+#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
|
|
|
+#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
|
|
|
+#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
|
|
|
+#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
|
|
|
+#define GPIO_MODER_MODE13_Pos (26U)
|
|
|
+#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
|
|
|
+#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
|
|
|
+#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
|
|
|
+#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
|
|
|
+#define GPIO_MODER_MODE14_Pos (28U)
|
|
|
+#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
|
|
|
+#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
|
|
|
+#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
|
|
|
+#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
|
|
|
+#define GPIO_MODER_MODE15_Pos (30U)
|
|
|
+#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
|
|
|
+#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
|
|
|
+#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
|
|
|
+#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
|
|
|
+
|
|
|
+/****************** Bits definition for GPIO_OTYPER register ****************/
|
|
|
+#define GPIO_OTYPER_OT0_Pos (0U)
|
|
|
+#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
|
|
|
+#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
|
|
|
+#define GPIO_OTYPER_OT1_Pos (1U)
|
|
|
+#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
|
|
|
+#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
|
|
|
+#define GPIO_OTYPER_OT2_Pos (2U)
|
|
|
+#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
|
|
|
+#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
|
|
|
+#define GPIO_OTYPER_OT3_Pos (3U)
|
|
|
+#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
|
|
|
+#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
|
|
|
+#define GPIO_OTYPER_OT4_Pos (4U)
|
|
|
+#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
|
|
|
+#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
|
|
|
+#define GPIO_OTYPER_OT5_Pos (5U)
|
|
|
+#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
|
|
|
+#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
|
|
|
+#define GPIO_OTYPER_OT6_Pos (6U)
|
|
|
+#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
|
|
|
+#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
|
|
|
+#define GPIO_OTYPER_OT7_Pos (7U)
|
|
|
+#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
|
|
|
+#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
|
|
|
+#define GPIO_OTYPER_OT8_Pos (8U)
|
|
|
+#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
|
|
|
+#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
|
|
|
+#define GPIO_OTYPER_OT9_Pos (9U)
|
|
|
+#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
|
|
|
+#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
|
|
|
+#define GPIO_OTYPER_OT10_Pos (10U)
|
|
|
+#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
|
|
|
+#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
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+#define GPIO_OTYPER_OT11_Pos (11U)
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+#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
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+#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
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+#define GPIO_OTYPER_OT12_Pos (12U)
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+#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
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+#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
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+#define GPIO_OTYPER_OT13_Pos (13U)
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+#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
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+#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
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+#define GPIO_OTYPER_OT14_Pos (14U)
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+#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
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+#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
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+#define GPIO_OTYPER_OT15_Pos (15U)
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+#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
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+#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
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+
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+/****************** Bits definition for GPIO_OSPEEDR register ***************/
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+#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
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+#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
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+#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
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+#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
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+#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
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+#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
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+#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
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+#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
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+#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
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+#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
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+#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
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+#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
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+#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
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+#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
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+#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
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+#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
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+#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
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+#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
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+#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
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+#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
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+#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
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+#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
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+#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
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+#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
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+#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
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+#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
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+#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
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+#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
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+#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
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+#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
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+#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
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+#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
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+#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
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+#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
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+#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
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+#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
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+#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
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+#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
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+#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
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+#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
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+#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
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+#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
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+#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
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+#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
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+#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
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+#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
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+#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
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+#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
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+#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
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+#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
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+#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
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+#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
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+#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
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+#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
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+#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
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+#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
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+#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
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+#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
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+#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
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+#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
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+#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
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+#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
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+#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
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+#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
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+#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
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+#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
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+#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
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+#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
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+#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
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+#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
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+#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
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+#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
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+#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
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+#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
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+#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
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+#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
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+#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
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+#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
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+#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
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+#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
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+
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+/****************** Bits definition for GPIO_PUPDR register *****************/
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+#define GPIO_PUPDR_PUPD0_Pos (0U)
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+#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
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+#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
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+#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
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+#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
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+#define GPIO_PUPDR_PUPD1_Pos (2U)
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+#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
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+#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
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+#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
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+#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
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+#define GPIO_PUPDR_PUPD2_Pos (4U)
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+#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
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+#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
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+#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
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+#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
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+#define GPIO_PUPDR_PUPD3_Pos (6U)
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+#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
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+#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
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+#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
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+#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
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+#define GPIO_PUPDR_PUPD4_Pos (8U)
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+#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
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+#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
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+#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
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+#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
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+#define GPIO_PUPDR_PUPD5_Pos (10U)
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+#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
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+#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
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+#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
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+#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
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+#define GPIO_PUPDR_PUPD6_Pos (12U)
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+#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
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+#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
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+#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
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+#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
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+#define GPIO_PUPDR_PUPD7_Pos (14U)
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+#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
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+#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
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+#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
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+#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
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+#define GPIO_PUPDR_PUPD8_Pos (16U)
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+#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
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+#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
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+#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
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+#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
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+#define GPIO_PUPDR_PUPD9_Pos (18U)
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+#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
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+#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
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+#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
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+#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
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+#define GPIO_PUPDR_PUPD10_Pos (20U)
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+#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
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+#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
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+#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
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+#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
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+#define GPIO_PUPDR_PUPD11_Pos (22U)
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+#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
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+#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
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+#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
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+#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
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+#define GPIO_PUPDR_PUPD12_Pos (24U)
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+#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
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+#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
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+#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
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+#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
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+#define GPIO_PUPDR_PUPD13_Pos (26U)
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+#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
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+#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
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+#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
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+#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
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+#define GPIO_PUPDR_PUPD14_Pos (28U)
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+#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
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+#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
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+#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
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+#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
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+#define GPIO_PUPDR_PUPD15_Pos (30U)
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+#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
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+#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
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+#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
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+#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
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+
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+/****************** Bits definition for GPIO_IDR register *******************/
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|
+#define GPIO_IDR_ID0_Pos (0U)
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+#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
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+#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
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+#define GPIO_IDR_ID1_Pos (1U)
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+#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
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+#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
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+#define GPIO_IDR_ID2_Pos (2U)
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+#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
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+#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
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+#define GPIO_IDR_ID3_Pos (3U)
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+#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
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+#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
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|
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+#define GPIO_IDR_ID4_Pos (4U)
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+#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
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|
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+#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
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|
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+#define GPIO_IDR_ID5_Pos (5U)
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+#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
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|
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+#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
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+#define GPIO_IDR_ID6_Pos (6U)
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+#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
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|
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+#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
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+#define GPIO_IDR_ID7_Pos (7U)
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+#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
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|
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+#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
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+#define GPIO_IDR_ID8_Pos (8U)
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+#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
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|
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+#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
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+#define GPIO_IDR_ID9_Pos (9U)
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+#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
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+#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
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+#define GPIO_IDR_ID10_Pos (10U)
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+#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
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|
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+#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
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+#define GPIO_IDR_ID11_Pos (11U)
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+#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
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|
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+#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
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|
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+#define GPIO_IDR_ID12_Pos (12U)
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+#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
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|
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+#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
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+#define GPIO_IDR_ID13_Pos (13U)
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+#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
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|
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+#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
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|
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+#define GPIO_IDR_ID14_Pos (14U)
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+#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
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|
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+#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
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+#define GPIO_IDR_ID15_Pos (15U)
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+#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
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|
|
+#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
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+
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|
|
+/****************** Bits definition for GPIO_ODR register *******************/
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|
|
+#define GPIO_ODR_OD0_Pos (0U)
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+#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
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|
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+#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
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|
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+#define GPIO_ODR_OD1_Pos (1U)
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|
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+#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
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+#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
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|
|
+#define GPIO_ODR_OD2_Pos (2U)
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+#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
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|
|
+#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
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|
|
+#define GPIO_ODR_OD3_Pos (3U)
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|
+#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
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|
|
+#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
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|
|
+#define GPIO_ODR_OD4_Pos (4U)
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|
|
+#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
|
|
|
+#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
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|
|
+#define GPIO_ODR_OD5_Pos (5U)
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|
|
+#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
|
|
|
+#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
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|
|
+#define GPIO_ODR_OD6_Pos (6U)
|
|
|
+#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
|
|
|
+#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
|
|
|
+#define GPIO_ODR_OD7_Pos (7U)
|
|
|
+#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
|
|
|
+#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
|
|
|
+#define GPIO_ODR_OD8_Pos (8U)
|
|
|
+#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
|
|
|
+#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
|
|
|
+#define GPIO_ODR_OD9_Pos (9U)
|
|
|
+#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
|
|
|
+#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
|
|
|
+#define GPIO_ODR_OD10_Pos (10U)
|
|
|
+#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
|
|
|
+#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
|
|
|
+#define GPIO_ODR_OD11_Pos (11U)
|
|
|
+#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
|
|
|
+#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
|
|
|
+#define GPIO_ODR_OD12_Pos (12U)
|
|
|
+#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
|
|
|
+#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
|
|
|
+#define GPIO_ODR_OD13_Pos (13U)
|
|
|
+#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
|
|
|
+#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
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|
|
+#define GPIO_ODR_OD14_Pos (14U)
|
|
|
+#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
|
|
|
+#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
|
|
|
+#define GPIO_ODR_OD15_Pos (15U)
|
|
|
+#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
|
|
|
+#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
|
|
|
+
|
|
|
+/****************** Bits definition for GPIO_BSRR register ******************/
|
|
|
+#define GPIO_BSRR_BS0_Pos (0U)
|
|
|
+#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
|
|
|
+#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
|
|
|
+#define GPIO_BSRR_BS1_Pos (1U)
|
|
|
+#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
|
|
|
+#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
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|
|
+#define GPIO_BSRR_BS2_Pos (2U)
|
|
|
+#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
|
|
|
+#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
|
|
|
+#define GPIO_BSRR_BS3_Pos (3U)
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|
|
+#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
|
|
|
+#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
|
|
|
+#define GPIO_BSRR_BS4_Pos (4U)
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|
|
+#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
|
|
|
+#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
|
|
|
+#define GPIO_BSRR_BS5_Pos (5U)
|
|
|
+#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
|
|
|
+#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
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|
|
+#define GPIO_BSRR_BS6_Pos (6U)
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|
|
+#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
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|
|
+#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
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|
|
+#define GPIO_BSRR_BS7_Pos (7U)
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|
|
+#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
|
|
|
+#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
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|
|
+#define GPIO_BSRR_BS8_Pos (8U)
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|
|
+#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
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|
|
+#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
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|
|
+#define GPIO_BSRR_BS9_Pos (9U)
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|
|
+#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
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|
|
+#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
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|
|
+#define GPIO_BSRR_BS10_Pos (10U)
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|
+#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
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|
|
+#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
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|
|
+#define GPIO_BSRR_BS11_Pos (11U)
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|
|
+#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
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|
|
+#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
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|
|
+#define GPIO_BSRR_BS12_Pos (12U)
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|
|
+#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
|
|
|
+#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
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|
|
+#define GPIO_BSRR_BS13_Pos (13U)
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|
|
+#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
|
|
|
+#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
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|
|
+#define GPIO_BSRR_BS14_Pos (14U)
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|
|
+#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
|
|
|
+#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
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|
|
+#define GPIO_BSRR_BS15_Pos (15U)
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|
|
+#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
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|
|
+#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
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|
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+#define GPIO_BSRR_BR0_Pos (16U)
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|
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+#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
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|
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+#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
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|
|
+#define GPIO_BSRR_BR1_Pos (17U)
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|
|
+#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
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|
|
+#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
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|
|
+#define GPIO_BSRR_BR2_Pos (18U)
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|
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+#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
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|
|
+#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
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|
|
+#define GPIO_BSRR_BR3_Pos (19U)
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|
|
+#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
|
|
|
+#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
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|
|
+#define GPIO_BSRR_BR4_Pos (20U)
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|
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+#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
|
|
|
+#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
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|
|
+#define GPIO_BSRR_BR5_Pos (21U)
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|
|
+#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
|
|
|
+#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
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|
|
+#define GPIO_BSRR_BR6_Pos (22U)
|
|
|
+#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
|
|
|
+#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
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|
|
+#define GPIO_BSRR_BR7_Pos (23U)
|
|
|
+#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
|
|
|
+#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
|
|
|
+#define GPIO_BSRR_BR8_Pos (24U)
|
|
|
+#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
|
|
|
+#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
|
|
|
+#define GPIO_BSRR_BR9_Pos (25U)
|
|
|
+#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
|
|
|
+#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
|
|
|
+#define GPIO_BSRR_BR10_Pos (26U)
|
|
|
+#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
|
|
|
+#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
|
|
|
+#define GPIO_BSRR_BR11_Pos (27U)
|
|
|
+#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
|
|
|
+#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
|
|
|
+#define GPIO_BSRR_BR12_Pos (28U)
|
|
|
+#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
|
|
|
+#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
|
|
|
+#define GPIO_BSRR_BR13_Pos (29U)
|
|
|
+#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
|
|
|
+#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
|
|
|
+#define GPIO_BSRR_BR14_Pos (30U)
|
|
|
+#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
|
|
|
+#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
|
|
|
+#define GPIO_BSRR_BR15_Pos (31U)
|
|
|
+#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
|
|
|
+#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
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|
|
+
|
|
|
+/****************** Bit definition for GPIO_LCKR register *********************/
|
|
|
+#define GPIO_LCKR_LCK0_Pos (0U)
|
|
|
+#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
|
|
|
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
|
|
|
+#define GPIO_LCKR_LCK1_Pos (1U)
|
|
|
+#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
|
|
|
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
|
|
|
+#define GPIO_LCKR_LCK2_Pos (2U)
|
|
|
+#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
|
|
|
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
|
|
|
+#define GPIO_LCKR_LCK3_Pos (3U)
|
|
|
+#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
|
|
|
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
|
|
|
+#define GPIO_LCKR_LCK4_Pos (4U)
|
|
|
+#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
|
|
|
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
|
|
|
+#define GPIO_LCKR_LCK5_Pos (5U)
|
|
|
+#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
|
|
|
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
|
|
|
+#define GPIO_LCKR_LCK6_Pos (6U)
|
|
|
+#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
|
|
|
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
|
|
|
+#define GPIO_LCKR_LCK7_Pos (7U)
|
|
|
+#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
|
|
|
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
|
|
|
+#define GPIO_LCKR_LCK8_Pos (8U)
|
|
|
+#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
|
|
|
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
|
|
|
+#define GPIO_LCKR_LCK9_Pos (9U)
|
|
|
+#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
|
|
|
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
|
|
|
+#define GPIO_LCKR_LCK10_Pos (10U)
|
|
|
+#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
|
|
|
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
|
|
|
+#define GPIO_LCKR_LCK11_Pos (11U)
|
|
|
+#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
|
|
|
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
|
|
|
+#define GPIO_LCKR_LCK12_Pos (12U)
|
|
|
+#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
|
|
|
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
|
|
|
+#define GPIO_LCKR_LCK13_Pos (13U)
|
|
|
+#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
|
|
|
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
|
|
|
+#define GPIO_LCKR_LCK14_Pos (14U)
|
|
|
+#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
|
|
|
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
|
|
|
+#define GPIO_LCKR_LCK15_Pos (15U)
|
|
|
+#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
|
|
|
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
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|
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+#define GPIO_LCKR_LCKK_Pos (16U)
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+#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
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|
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+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
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+
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|
|
+/****************** Bit definition for GPIO_AFRL register *********************/
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|
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+#define GPIO_AFRL_AFSEL0_Pos (0U)
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+#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
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+#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
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+#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
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+#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
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+#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
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+#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
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+#define GPIO_AFRL_AFSEL1_Pos (4U)
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+#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
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+#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
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+#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
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+#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
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+#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
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+#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
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+#define GPIO_AFRL_AFSEL2_Pos (8U)
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+#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
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+#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
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+#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
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+#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
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+#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
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+#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
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+#define GPIO_AFRL_AFSEL3_Pos (12U)
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+#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
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+#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
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+#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
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+#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
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+#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
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+#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
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+#define GPIO_AFRL_AFSEL4_Pos (16U)
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+#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
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+#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
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+#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
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+#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
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+#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
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+#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
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+#define GPIO_AFRL_AFSEL5_Pos (20U)
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+#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
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+#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
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+#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
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+#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
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+#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
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+#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
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+#define GPIO_AFRL_AFSEL6_Pos (24U)
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+#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
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+#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
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+#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
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+#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
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+#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
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+#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
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+#define GPIO_AFRL_AFSEL7_Pos (28U)
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+#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
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+#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
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+#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
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+#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
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+#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
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+#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
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+
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|
|
+/****************** Bit definition for GPIO_AFRH register *********************/
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|
|
+#define GPIO_AFRH_AFSEL8_Pos (0U)
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|
+#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
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+#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
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+#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
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+#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
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+#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
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+#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
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+#define GPIO_AFRH_AFSEL9_Pos (4U)
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|
+#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
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|
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+#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
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+#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
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|
+#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
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+#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
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|
|
+#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
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|
|
+#define GPIO_AFRH_AFSEL10_Pos (8U)
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|
+#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
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|
|
+#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
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|
+#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
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|
+#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
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+#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
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+#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
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+#define GPIO_AFRH_AFSEL11_Pos (12U)
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|
+#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
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|
|
+#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
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+#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
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+#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
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+#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
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+#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
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+#define GPIO_AFRH_AFSEL12_Pos (16U)
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+#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
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+#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
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+#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
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+#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
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+#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
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+#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
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+#define GPIO_AFRH_AFSEL13_Pos (20U)
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+#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
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+#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
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+#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
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+#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
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+#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
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+#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
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+#define GPIO_AFRH_AFSEL14_Pos (24U)
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+#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
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+#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
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+#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
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+#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
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+#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
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+#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
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+#define GPIO_AFRH_AFSEL15_Pos (28U)
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+#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
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+#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
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+#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
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+#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
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+#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
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+#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
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+
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|
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+/****************** Bits definition for GPIO_BRR register ******************/
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|
|
+#define GPIO_BRR_BR0_Pos (0U)
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+#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
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+#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
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|
|
+#define GPIO_BRR_BR1_Pos (1U)
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+#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
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|
|
+#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
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|
|
+#define GPIO_BRR_BR2_Pos (2U)
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+#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
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|
+#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
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|
|
+#define GPIO_BRR_BR3_Pos (3U)
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|
|
+#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
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|
|
+#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
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+#define GPIO_BRR_BR4_Pos (4U)
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+#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
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+#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
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+#define GPIO_BRR_BR5_Pos (5U)
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+#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
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+#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
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|
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+#define GPIO_BRR_BR6_Pos (6U)
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+#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
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+#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
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+#define GPIO_BRR_BR7_Pos (7U)
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+#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
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+#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
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+#define GPIO_BRR_BR8_Pos (8U)
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|
+#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
|
|
|
+#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
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|
+#define GPIO_BRR_BR9_Pos (9U)
|
|
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+#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
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+#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
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|
+#define GPIO_BRR_BR10_Pos (10U)
|
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|
+#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
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|
+#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
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|
|
+#define GPIO_BRR_BR11_Pos (11U)
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|
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+#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
|
|
|
+#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
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|
+#define GPIO_BRR_BR12_Pos (12U)
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|
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+#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
|
|
|
+#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
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|
|
+#define GPIO_BRR_BR13_Pos (13U)
|
|
|
+#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
|
|
|
+#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
|
|
|
+#define GPIO_BRR_BR14_Pos (14U)
|
|
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+#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
|
|
|
+#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
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|
+#define GPIO_BRR_BR15_Pos (15U)
|
|
|
+#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
|
|
|
+#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
|
|
|
+
|
|
|
+
|
|
|
+/******************************************************************************/
|
|
|
+/* */
|
|
|
+/* Inter-integrated Circuit Interface (I2C) */
|
|
|
+/* */
|
|
|
+/******************************************************************************/
|
|
|
+/******************* Bit definition for I2C_CR1 register *******************/
|
|
|
+#define I2C_CR1_PE_Pos (0U)
|
|
|
+#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
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|
|
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
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|
|
+#define I2C_CR1_TXIE_Pos (1U)
|
|
|
+#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
|
|
|
+#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
|
|
|
+#define I2C_CR1_RXIE_Pos (2U)
|
|
|
+#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
|
|
|
+#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
|
|
|
+#define I2C_CR1_ADDRIE_Pos (3U)
|
|
|
+#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
|
|
|
+#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
|
|
|
+#define I2C_CR1_NACKIE_Pos (4U)
|
|
|
+#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
|
|
|
+#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
|
|
|
+#define I2C_CR1_STOPIE_Pos (5U)
|
|
|
+#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
|
|
|
+#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
|
|
|
+#define I2C_CR1_TCIE_Pos (6U)
|
|
|
+#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
|
|
|
+#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
|
|
|
+#define I2C_CR1_ERRIE_Pos (7U)
|
|
|
+#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
|
|
|
+#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
|
|
|
+#define I2C_CR1_DNF_Pos (8U)
|
|
|
+#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
|
|
|
+#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
|
|
|
+#define I2C_CR1_ANFOFF_Pos (12U)
|
|
|
+#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
|
|
|
+#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
|
|
|
+#define I2C_CR1_SWRST_Pos (13U)
|
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|
+#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
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+#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
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+#define I2C_CR1_TXDMAEN_Pos (14U)
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+#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
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+#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
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+#define I2C_CR1_RXDMAEN_Pos (15U)
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+#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
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+#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
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+#define I2C_CR1_SBC_Pos (16U)
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+#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
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+#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
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+#define I2C_CR1_NOSTRETCH_Pos (17U)
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+#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
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+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
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+#define I2C_CR1_WUPEN_Pos (18U)
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+#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
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+#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
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+#define I2C_CR1_GCEN_Pos (19U)
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+#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
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+#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
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+#define I2C_CR1_SMBHEN_Pos (20U)
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+#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
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+#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
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+#define I2C_CR1_SMBDEN_Pos (21U)
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+#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
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+#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
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+#define I2C_CR1_ALERTEN_Pos (22U)
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+#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
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+#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
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+#define I2C_CR1_PECEN_Pos (23U)
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+#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
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+#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
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+
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+/****************** Bit definition for I2C_CR2 register ********************/
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+#define I2C_CR2_SADD_Pos (0U)
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+#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
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+#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
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+#define I2C_CR2_RD_WRN_Pos (10U)
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+#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
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+#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
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+#define I2C_CR2_ADD10_Pos (11U)
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+#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
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+#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
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+#define I2C_CR2_HEAD10R_Pos (12U)
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+#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
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+#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
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+#define I2C_CR2_START_Pos (13U)
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+#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
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+#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
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+#define I2C_CR2_STOP_Pos (14U)
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+#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
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+#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
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+#define I2C_CR2_NACK_Pos (15U)
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+#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
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+#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
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+#define I2C_CR2_NBYTES_Pos (16U)
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+#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
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+#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
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+#define I2C_CR2_RELOAD_Pos (24U)
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+#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
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+#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
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+#define I2C_CR2_AUTOEND_Pos (25U)
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+#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
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+#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
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+#define I2C_CR2_PECBYTE_Pos (26U)
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+#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
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+#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
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+
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+/******************* Bit definition for I2C_OAR1 register ******************/
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+#define I2C_OAR1_OA1_Pos (0U)
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+#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
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+#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
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+#define I2C_OAR1_OA1MODE_Pos (10U)
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+#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
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+#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
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+#define I2C_OAR1_OA1EN_Pos (15U)
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+#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
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+#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
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+
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+/******************* Bit definition for I2C_OAR2 register ******************/
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+#define I2C_OAR2_OA2_Pos (1U)
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+#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
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+#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
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+#define I2C_OAR2_OA2MSK_Pos (8U)
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+#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
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+#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
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+#define I2C_OAR2_OA2NOMASK (0U) /*!< No mask */
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+#define I2C_OAR2_OA2MASK01_Pos (8U)
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+#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
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+#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
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+#define I2C_OAR2_OA2MASK02_Pos (9U)
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+#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
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+#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
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+#define I2C_OAR2_OA2MASK03_Pos (8U)
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+#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
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+#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
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+#define I2C_OAR2_OA2MASK04_Pos (10U)
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+#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
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+#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
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+#define I2C_OAR2_OA2MASK05_Pos (8U)
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+#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
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+#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
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+#define I2C_OAR2_OA2MASK06_Pos (9U)
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+#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
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+#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
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+#define I2C_OAR2_OA2MASK07_Pos (8U)
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+#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
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+#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
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+#define I2C_OAR2_OA2EN_Pos (15U)
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+#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
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+#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
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+
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+/******************* Bit definition for I2C_TIMINGR register *******************/
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+#define I2C_TIMINGR_SCLL_Pos (0U)
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+#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
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+#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
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+#define I2C_TIMINGR_SCLH_Pos (8U)
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+#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
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+#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
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+#define I2C_TIMINGR_SDADEL_Pos (16U)
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+#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
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+#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
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+#define I2C_TIMINGR_SCLDEL_Pos (20U)
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+#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
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+#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
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+#define I2C_TIMINGR_PRESC_Pos (28U)
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+#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
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+#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
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+
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+/******************* Bit definition for I2C_TIMEOUTR register *******************/
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+#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
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+#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
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+#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
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+#define I2C_TIMEOUTR_TIDLE_Pos (12U)
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+#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
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+#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
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+#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
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+#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
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+#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
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+#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
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+#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
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+#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
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+#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
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+#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
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+#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
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+
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+/****************** Bit definition for I2C_ISR register *********************/
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+#define I2C_ISR_TXE_Pos (0U)
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+#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
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+#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
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+#define I2C_ISR_TXIS_Pos (1U)
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+#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
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+#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
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+#define I2C_ISR_RXNE_Pos (2U)
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+#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
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+#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
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+#define I2C_ISR_ADDR_Pos (3U)
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+#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
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+#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
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+#define I2C_ISR_NACKF_Pos (4U)
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+#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
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+#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
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+#define I2C_ISR_STOPF_Pos (5U)
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+#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
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+#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
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+#define I2C_ISR_TC_Pos (6U)
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+#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
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+#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
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+#define I2C_ISR_TCR_Pos (7U)
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+#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
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+#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
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+#define I2C_ISR_BERR_Pos (8U)
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+#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
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+#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
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+#define I2C_ISR_ARLO_Pos (9U)
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+#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
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+#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
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+#define I2C_ISR_OVR_Pos (10U)
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+#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
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+#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
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+#define I2C_ISR_PECERR_Pos (11U)
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+#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
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+#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
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+#define I2C_ISR_TIMEOUT_Pos (12U)
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+#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
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+#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
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+#define I2C_ISR_ALERT_Pos (13U)
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+#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
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+#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
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+#define I2C_ISR_BUSY_Pos (15U)
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+#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
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+#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
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+#define I2C_ISR_DIR_Pos (16U)
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+#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
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+#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
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+#define I2C_ISR_ADDCODE_Pos (17U)
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+#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
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+#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
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+
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+/****************** Bit definition for I2C_ICR register *********************/
|
|
|
+#define I2C_ICR_ADDRCF_Pos (3U)
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|
|
+#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
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|
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+#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
|
|
|
+#define I2C_ICR_NACKCF_Pos (4U)
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|
|
+#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
|
|
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+#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
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|
|
+#define I2C_ICR_STOPCF_Pos (5U)
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|
|
+#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
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|
|
+#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
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|
|
+#define I2C_ICR_BERRCF_Pos (8U)
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+#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
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|
|
+#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
|
|
|
+#define I2C_ICR_ARLOCF_Pos (9U)
|
|
|
+#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
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|
|
+#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
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|
|
+#define I2C_ICR_OVRCF_Pos (10U)
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|
+#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
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|
|
+#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
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|
|
+#define I2C_ICR_PECCF_Pos (11U)
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|
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+#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
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|
|
+#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
|
|
|
+#define I2C_ICR_TIMOUTCF_Pos (12U)
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|
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+#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
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|
|
+#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
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|
|
+#define I2C_ICR_ALERTCF_Pos (13U)
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|
|
+#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
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|
|
+#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
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|
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+
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|
|
+/****************** Bit definition for I2C_PECR register *********************/
|
|
|
+#define I2C_PECR_PEC_Pos (0U)
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+#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
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|
|
+#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
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|
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+
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|
|
+/****************** Bit definition for I2C_RXDR register *********************/
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|
|
+#define I2C_RXDR_RXDATA_Pos (0U)
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|
+#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
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|
|
+#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
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|
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+
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|
|
+/****************** Bit definition for I2C_TXDR register *********************/
|
|
|
+#define I2C_TXDR_TXDATA_Pos (0U)
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+#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
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|
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+#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
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|
|
+
|
|
|
+
|
|
|
+/******************************************************************************/
|
|
|
+/* */
|
|
|
+/* Independent WATCHDOG (IWDG) */
|
|
|
+/* */
|
|
|
+/******************************************************************************/
|
|
|
+/******************* Bit definition for IWDG_KR register ********************/
|
|
|
+#define IWDG_KR_KEY_Pos (0U)
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|
|
+#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
|
|
|
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
|
|
|
+
|
|
|
+/******************* Bit definition for IWDG_PR register ********************/
|
|
|
+#define IWDG_PR_PR_Pos (0U)
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|
|
+#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
|
|
|
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
|
|
|
+#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */
|
|
|
+#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */
|
|
|
+#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */
|
|
|
+
|
|
|
+/******************* Bit definition for IWDG_RLR register *******************/
|
|
|
+#define IWDG_RLR_RL_Pos (0U)
|
|
|
+#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
|
|
|
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
|
|
|
+
|
|
|
+/******************* Bit definition for IWDG_SR register ********************/
|
|
|
+#define IWDG_SR_PVU_Pos (0U)
|
|
|
+#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
|
|
|
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
|
|
|
+#define IWDG_SR_RVU_Pos (1U)
|
|
|
+#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
|
|
|
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
|
|
|
+#define IWDG_SR_WVU_Pos (2U)
|
|
|
+#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
|
|
|
+#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
|
|
|
+
|
|
|
+/******************* Bit definition for IWDG_KR register ********************/
|
|
|
+#define IWDG_WINR_WIN_Pos (0U)
|
|
|
+#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
|
|
|
+#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
|
|
|
+
|
|
|
+
|
|
|
+/******************************************************************************/
|
|
|
+/* */
|
|
|
+/* Power Control */
|
|
|
+/* */
|
|
|
+/******************************************************************************/
|
|
|
+/* Note: No specific macro feature on this device */
|
|
|
+
|
|
|
+/******************** Bit definition for PWR_CR1 register ********************/
|
|
|
+#define PWR_CR1_LPMS_Pos (0U)
|
|
|
+#define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
|
|
|
+#define PWR_CR1_LPMS PWR_CR1_LPMS_Msk /*!< Low Power Mode Selection */
|
|
|
+#define PWR_CR1_LPMS_0 (0x1UL << PWR_CR1_LPMS_Pos) /*!< 0x00000001 */
|
|
|
+#define PWR_CR1_LPMS_1 (0x2UL << PWR_CR1_LPMS_Pos) /*!< 0x00000002 */
|
|
|
+#define PWR_CR1_FPD_STOP_Pos (3U)
|
|
|
+#define PWR_CR1_FPD_STOP_Msk (0x1UL << PWR_CR1_FPD_STOP_Pos) /*!< 0x00000008 */
|
|
|
+#define PWR_CR1_FPD_STOP PWR_CR1_FPD_STOP_Msk /*!< Flash power down mode during stop */
|
|
|
+#define PWR_CR1_FPD_LPRUN_Pos (4U)
|
|
|
+#define PWR_CR1_FPD_LPRUN_Msk (0x1UL << PWR_CR1_FPD_LPRUN_Pos) /*!< 0x00000010 */
|
|
|
+#define PWR_CR1_FPD_LPRUN PWR_CR1_FPD_LPRUN_Msk /*!< Flash power down mode during run */
|
|
|
+#define PWR_CR1_FPD_LPSLP_Pos (5U)
|
|
|
+#define PWR_CR1_FPD_LPSLP_Msk (0x1UL << PWR_CR1_FPD_LPSLP_Pos) /*!< 0x00000020 */
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|
|
+#define PWR_CR1_FPD_LPSLP PWR_CR1_FPD_LPSLP_Msk /*!< Flash power down mode during sleep */
|
|
|
+#define PWR_CR1_DBP_Pos (8U)
|
|
|
+#define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos) /*!< 0x00000100 */
|
|
|
+#define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Backup Domain write protection */
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|
|
+#define PWR_CR1_VOS_Pos (9U)
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|
|
+#define PWR_CR1_VOS_Msk (0x3UL << PWR_CR1_VOS_Pos) /*!< 0x00000600 */
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|
|
+#define PWR_CR1_VOS PWR_CR1_VOS_Msk /*!< Voltage scaling */
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|
|
+#define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_Pos) /*!< Voltage scaling bit 0 */
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|
|
+#define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_Pos) /*!< Voltage scaling bit 1 */
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|
+#define PWR_CR1_LPR_Pos (14U)
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|
|
+#define PWR_CR1_LPR_Msk (0x1UL << PWR_CR1_LPR_Pos) /*!< 0x00004000 */
|
|
|
+#define PWR_CR1_LPR PWR_CR1_LPR_Msk /*!< Regulator Low-Power Run mode */
|
|
|
+
|
|
|
+
|
|
|
+/******************** Bit definition for PWR_CR3 register ********************/
|
|
|
+#define PWR_CR3_EWUP_Pos (0U)
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|
|
+#define PWR_CR3_EWUP_Msk (0x2BUL << PWR_CR3_EWUP_Pos) /*!< 0x0000002B */
|
|
|
+#define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable all Wake-Up Pins */
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|
|
+#define PWR_CR3_EWUP1_Pos (0U)
|
|
|
+#define PWR_CR3_EWUP1_Msk (0x1UL << PWR_CR3_EWUP1_Pos) /*!< 0x00000001 */
|
|
|
+#define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk /*!< Enable WKUP pin 1 */
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|
|
+#define PWR_CR3_EWUP2_Pos (1U)
|
|
|
+#define PWR_CR3_EWUP2_Msk (0x1UL << PWR_CR3_EWUP2_Pos) /*!< 0x00000002 */
|
|
|
+#define PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk /*!< Enable WKUP pin 2 */
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|
|
+#define PWR_CR3_EWUP4_Pos (3U)
|
|
|
+#define PWR_CR3_EWUP4_Msk (0x1UL << PWR_CR3_EWUP4_Pos) /*!< 0x00000008 */
|
|
|
+#define PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk /*!< Enable WKUP pin 4 */
|
|
|
+#define PWR_CR3_EWUP6_Pos (5U)
|
|
|
+#define PWR_CR3_EWUP6_Msk (0x1UL << PWR_CR3_EWUP6_Pos) /*!< 0x00000020 */
|
|
|
+#define PWR_CR3_EWUP6 PWR_CR3_EWUP6_Msk /*!< Enable WKUP pin 6 */
|
|
|
+#define PWR_CR3_APC_Pos (10U)
|
|
|
+#define PWR_CR3_APC_Msk (0x1UL << PWR_CR3_APC_Pos) /*!< 0x00000400 */
|
|
|
+#define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */
|
|
|
+#define PWR_CR3_EIWUL_Pos (15U)
|
|
|
+#define PWR_CR3_EIWUL_Msk (0x1UL << PWR_CR3_EIWUL_Pos) /*!< 0x00008000 */
|
|
|
+#define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Enable Internal Wake-up line */
|
|
|
+
|
|
|
+/******************** Bit definition for PWR_CR4 register ********************/
|
|
|
+#define PWR_CR4_WP_Pos (0U)
|
|
|
+#define PWR_CR4_WP_Msk (0x2BUL << PWR_CR4_WP_Pos) /*!< 0x0000002B */
|
|
|
+#define PWR_CR4_WP PWR_CR4_WP_Msk /*!< all Wake-Up Pin polarity */
|
|
|
+#define PWR_CR4_WP1_Pos (0U)
|
|
|
+#define PWR_CR4_WP1_Msk (0x1UL << PWR_CR4_WP1_Pos) /*!< 0x00000001 */
|
|
|
+#define PWR_CR4_WP1 PWR_CR4_WP1_Msk /*!< Wake-Up Pin 1 polarity */
|
|
|
+#define PWR_CR4_WP2_Pos (1U)
|
|
|
+#define PWR_CR4_WP2_Msk (0x1UL << PWR_CR4_WP2_Pos) /*!< 0x00000002 */
|
|
|
+#define PWR_CR4_WP2 PWR_CR4_WP2_Msk /*!< Wake-Up Pin 2 polarity */
|
|
|
+#define PWR_CR4_WP4_Pos (3U)
|
|
|
+#define PWR_CR4_WP4_Msk (0x1UL << PWR_CR4_WP4_Pos) /*!< 0x00000008 */
|
|
|
+#define PWR_CR4_WP4 PWR_CR4_WP4_Msk /*!< Wake-Up Pin 4 polarity */
|
|
|
+#define PWR_CR4_WP6_Pos (5U)
|
|
|
+#define PWR_CR4_WP6_Msk (0x1UL << PWR_CR4_WP6_Pos) /*!< 0x00000020 */
|
|
|
+#define PWR_CR4_WP6 PWR_CR4_WP6_Msk /*!< Wake-Up Pin 6 polarity */
|
|
|
+#define PWR_CR4_VBE_Pos (8U)
|
|
|
+#define PWR_CR4_VBE_Msk (0x1UL << PWR_CR4_VBE_Pos) /*!< 0x00000100 */
|
|
|
+#define PWR_CR4_VBE PWR_CR4_VBE_Msk /*!< VBAT Battery charging Enable */
|
|
|
+#define PWR_CR4_VBRS_Pos (9U)
|
|
|
+#define PWR_CR4_VBRS_Msk (0x1UL << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */
|
|
|
+#define PWR_CR4_VBRS PWR_CR4_VBRS_Msk /*!< VBAT Battery charging Resistor Selection */
|
|
|
+
|
|
|
+/******************** Bit definition for PWR_SR1 register ********************/
|
|
|
+#define PWR_SR1_WUF_Pos (0U)
|
|
|
+#define PWR_SR1_WUF_Msk (0x2BUL << PWR_SR1_WUF_Pos) /*!< 0x0000002B */
|
|
|
+#define PWR_SR1_WUF PWR_SR1_WUF_Msk /*!< Wakeup Flags */
|
|
|
+#define PWR_SR1_WUF1_Pos (0U)
|
|
|
+#define PWR_SR1_WUF1_Msk (0x1UL << PWR_SR1_WUF1_Pos) /*!< 0x00000001 */
|
|
|
+#define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk /*!< Wakeup Flag 1 */
|
|
|
+#define PWR_SR1_WUF2_Pos (1U)
|
|
|
+#define PWR_SR1_WUF2_Msk (0x1UL << PWR_SR1_WUF2_Pos) /*!< 0x00000002 */
|
|
|
+#define PWR_SR1_WUF2 PWR_SR1_WUF2_Msk /*!< Wakeup Flag 2 */
|
|
|
+#define PWR_SR1_WUF4_Pos (3U)
|
|
|
+#define PWR_SR1_WUF4_Msk (0x1UL << PWR_SR1_WUF4_Pos) /*!< 0x00000008 */
|
|
|
+#define PWR_SR1_WUF4 PWR_SR1_WUF4_Msk /*!< Wakeup Flag 4 */
|
|
|
+#define PWR_SR1_WUF6_Pos (5U)
|
|
|
+#define PWR_SR1_WUF6_Msk (0x1UL << PWR_SR1_WUF6_Pos) /*!< 0x00000020 */
|
|
|
+#define PWR_SR1_WUF6 PWR_SR1_WUF6_Msk /*!< Wakeup Flag 6 */
|
|
|
+#define PWR_SR1_SBF_Pos (8U)
|
|
|
+#define PWR_SR1_SBF_Msk (0x1UL << PWR_SR1_SBF_Pos) /*!< 0x00000100 */
|
|
|
+#define PWR_SR1_SBF PWR_SR1_SBF_Msk /*!< Standby Flag */
|
|
|
+#define PWR_SR1_WUFI_Pos (15U)
|
|
|
+#define PWR_SR1_WUFI_Msk (0x1UL << PWR_SR1_WUFI_Pos) /*!< 0x00008000 */
|
|
|
+#define PWR_SR1_WUFI PWR_SR1_WUFI_Msk /*!< Wakeup Flag Internal */
|
|
|
+
|
|
|
+/******************** Bit definition for PWR_SR2 register ********************/
|
|
|
+#define PWR_SR2_FLASH_RDY_Pos (7U)
|
|
|
+#define PWR_SR2_FLASH_RDY_Msk (0x1UL << PWR_SR2_FLASH_RDY_Pos) /*!< 0x00000080 */
|
|
|
+#define PWR_SR2_FLASH_RDY PWR_SR2_FLASH_RDY_Msk /*!< Flash Ready */
|
|
|
+#define PWR_SR2_REGLPS_Pos (8U)
|
|
|
+#define PWR_SR2_REGLPS_Msk (0x1UL << PWR_SR2_REGLPS_Pos) /*!< 0x00000100 */
|
|
|
+#define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk /*!< Regulator Low Power started */
|
|
|
+#define PWR_SR2_REGLPF_Pos (9U)
|
|
|
+#define PWR_SR2_REGLPF_Msk (0x1UL << PWR_SR2_REGLPF_Pos) /*!< 0x00000200 */
|
|
|
+#define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk /*!< Regulator Low Power flag */
|
|
|
+#define PWR_SR2_VOSF_Pos (10U)
|
|
|
+#define PWR_SR2_VOSF_Msk (0x1UL << PWR_SR2_VOSF_Pos) /*!< 0x00000400 */
|
|
|
+#define PWR_SR2_VOSF PWR_SR2_VOSF_Msk /*!< Voltage Scaling Flag */
|
|
|
+
|
|
|
+/******************** Bit definition for PWR_SCR register ********************/
|
|
|
+#define PWR_SCR_CWUF_Pos (0U)
|
|
|
+#define PWR_SCR_CWUF_Msk (0x2BUL << PWR_SCR_CWUF_Pos) /*!< 0x0000002B */
|
|
|
+#define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up Flags */
|
|
|
+#define PWR_SCR_CWUF1_Pos (0U)
|
|
|
+#define PWR_SCR_CWUF1_Msk (0x1UL << PWR_SCR_CWUF1_Pos) /*!< 0x00000001 */
|
|
|
+#define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk /*!< Clear Wake-up Flag 1 */
|
|
|
+#define PWR_SCR_CWUF2_Pos (1U)
|
|
|
+#define PWR_SCR_CWUF2_Msk (0x1UL << PWR_SCR_CWUF2_Pos) /*!< 0x00000002 */
|
|
|
+#define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk /*!< Clear Wake-up Flag 2 */
|
|
|
+#define PWR_SCR_CWUF4_Pos (3U)
|
|
|
+#define PWR_SCR_CWUF4_Msk (0x1UL << PWR_SCR_CWUF4_Pos) /*!< 0x00000008 */
|
|
|
+#define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk /*!< Clear Wake-up Flag 4 */
|
|
|
+#define PWR_SCR_CWUF6_Pos (5U)
|
|
|
+#define PWR_SCR_CWUF6_Msk (0x1UL << PWR_SCR_CWUF6_Pos) /*!< 0x00000020 */
|
|
|
+#define PWR_SCR_CWUF6 PWR_SCR_CWUF6_Msk /*!< Clear Wake-up Flag 6 */
|
|
|
+#define PWR_SCR_CSBF_Pos (8U)
|
|
|
+#define PWR_SCR_CSBF_Msk (0x1UL << PWR_SCR_CSBF_Pos) /*!< 0x00000100 */
|
|
|
+#define PWR_SCR_CSBF PWR_SCR_CSBF_Msk /*!< Clear Standby Flag */
|
|
|
+
|
|
|
+/******************** Bit definition for PWR_PUCRA register *****************/
|
|
|
+#define PWR_PUCRA_PU0_Pos (0U)
|
|
|
+#define PWR_PUCRA_PU0_Msk (0x1UL << PWR_PUCRA_PU0_Pos) /*!< 0x00000001 */
|
|
|
+#define PWR_PUCRA_PU0 PWR_PUCRA_PU0_Msk /*!< Pin PA0 Pull-Up set */
|
|
|
+#define PWR_PUCRA_PU1_Pos (1U)
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+#define PWR_PUCRA_PU1_Msk (0x1UL << PWR_PUCRA_PU1_Pos) /*!< 0x00000002 */
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+#define PWR_PUCRA_PU1 PWR_PUCRA_PU1_Msk /*!< Pin PA1 Pull-Up set */
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+#define PWR_PUCRA_PU2_Pos (2U)
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+#define PWR_PUCRA_PU2_Msk (0x1UL << PWR_PUCRA_PU2_Pos) /*!< 0x00000004 */
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+#define PWR_PUCRA_PU2 PWR_PUCRA_PU2_Msk /*!< Pin PA2 Pull-Up set */
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+#define PWR_PUCRA_PU3_Pos (3U)
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+#define PWR_PUCRA_PU3_Msk (0x1UL << PWR_PUCRA_PU3_Pos) /*!< 0x00000008 */
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+#define PWR_PUCRA_PU3 PWR_PUCRA_PU3_Msk /*!< Pin PA3 Pull-Up set */
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+#define PWR_PUCRA_PU4_Pos (4U)
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+#define PWR_PUCRA_PU4_Msk (0x1UL << PWR_PUCRA_PU4_Pos) /*!< 0x00000010 */
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+#define PWR_PUCRA_PU4 PWR_PUCRA_PU4_Msk /*!< Pin PA4 Pull-Up set */
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+#define PWR_PUCRA_PU5_Pos (5U)
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+#define PWR_PUCRA_PU5_Msk (0x1UL << PWR_PUCRA_PU5_Pos) /*!< 0x00000020 */
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+#define PWR_PUCRA_PU5 PWR_PUCRA_PU5_Msk /*!< Pin PA5 Pull-Up set */
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+#define PWR_PUCRA_PU6_Pos (6U)
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+#define PWR_PUCRA_PU6_Msk (0x1UL << PWR_PUCRA_PU6_Pos) /*!< 0x00000040 */
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+#define PWR_PUCRA_PU6 PWR_PUCRA_PU6_Msk /*!< Pin PA6 Pull-Up set */
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+#define PWR_PUCRA_PU7_Pos (7U)
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+#define PWR_PUCRA_PU7_Msk (0x1UL << PWR_PUCRA_PU7_Pos) /*!< 0x00000080 */
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+#define PWR_PUCRA_PU7 PWR_PUCRA_PU7_Msk /*!< Pin PA7 Pull-Up set */
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+#define PWR_PUCRA_PU8_Pos (8U)
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+#define PWR_PUCRA_PU8_Msk (0x1UL << PWR_PUCRA_PU8_Pos) /*!< 0x00000100 */
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+#define PWR_PUCRA_PU8 PWR_PUCRA_PU8_Msk /*!< Pin PA8 Pull-Up set */
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+#define PWR_PUCRA_PU9_Pos (9U)
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+#define PWR_PUCRA_PU9_Msk (0x1UL << PWR_PUCRA_PU9_Pos) /*!< 0x00000200 */
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+#define PWR_PUCRA_PU9 PWR_PUCRA_PU9_Msk /*!< Pin PA9 Pull-Up set */
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+#define PWR_PUCRA_PU10_Pos (10U)
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+#define PWR_PUCRA_PU10_Msk (0x1UL << PWR_PUCRA_PU10_Pos) /*!< 0x00000400 */
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+#define PWR_PUCRA_PU10 PWR_PUCRA_PU10_Msk /*!< Pin PA10 Pull-Up set */
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+#define PWR_PUCRA_PU11_Pos (11U)
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+#define PWR_PUCRA_PU11_Msk (0x1UL << PWR_PUCRA_PU11_Pos) /*!< 0x00000800 */
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+#define PWR_PUCRA_PU11 PWR_PUCRA_PU11_Msk /*!< Pin PA11 Pull-Up set */
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+#define PWR_PUCRA_PU12_Pos (12U)
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+#define PWR_PUCRA_PU12_Msk (0x1UL << PWR_PUCRA_PU12_Pos) /*!< 0x00001000 */
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+#define PWR_PUCRA_PU12 PWR_PUCRA_PU12_Msk /*!< Pin PA12 Pull-Up set */
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+#define PWR_PUCRA_PU13_Pos (13U)
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+#define PWR_PUCRA_PU13_Msk (0x1UL << PWR_PUCRA_PU13_Pos) /*!< 0x00002000 */
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+#define PWR_PUCRA_PU13 PWR_PUCRA_PU13_Msk /*!< Pin PA13 Pull-Up set */
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+#define PWR_PUCRA_PU14_Pos (14U)
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+#define PWR_PUCRA_PU14_Msk (0x1UL << PWR_PUCRA_PU14_Pos) /*!< 0x00004000 */
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+#define PWR_PUCRA_PU14 PWR_PUCRA_PU14_Msk /*!< Pin PA14 Pull-Up set */
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+#define PWR_PUCRA_PU15_Pos (15U)
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+#define PWR_PUCRA_PU15_Msk (0x1UL << PWR_PUCRA_PU15_Pos) /*!< 0x00008000 */
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+#define PWR_PUCRA_PU15 PWR_PUCRA_PU15_Msk /*!< Pin PA15 Pull-Up set */
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+
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|
+/******************** Bit definition for PWR_PDCRA register *****************/
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+#define PWR_PDCRA_PD0_Pos (0U)
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+#define PWR_PDCRA_PD0_Msk (0x1UL << PWR_PDCRA_PD0_Pos) /*!< 0x00000001 */
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+#define PWR_PDCRA_PD0 PWR_PDCRA_PD0_Msk /*!< Pin PA0 Pull-Down set */
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+#define PWR_PDCRA_PD1_Pos (1U)
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+#define PWR_PDCRA_PD1_Msk (0x1UL << PWR_PDCRA_PD1_Pos) /*!< 0x00000002 */
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+#define PWR_PDCRA_PD1 PWR_PDCRA_PD1_Msk /*!< Pin PA1 Pull-Down set */
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+#define PWR_PDCRA_PD2_Pos (2U)
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+#define PWR_PDCRA_PD2_Msk (0x1UL << PWR_PDCRA_PD2_Pos) /*!< 0x00000004 */
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+#define PWR_PDCRA_PD2 PWR_PDCRA_PD2_Msk /*!< Pin PA2 Pull-Down set */
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+#define PWR_PDCRA_PD3_Pos (3U)
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+#define PWR_PDCRA_PD3_Msk (0x1UL << PWR_PDCRA_PD3_Pos) /*!< 0x00000008 */
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+#define PWR_PDCRA_PD3 PWR_PDCRA_PD3_Msk /*!< Pin PA3 Pull-Down set */
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+#define PWR_PDCRA_PD4_Pos (4U)
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+#define PWR_PDCRA_PD4_Msk (0x1UL << PWR_PDCRA_PD4_Pos) /*!< 0x00000010 */
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+#define PWR_PDCRA_PD4 PWR_PDCRA_PD4_Msk /*!< Pin PA4 Pull-Down set */
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+#define PWR_PDCRA_PD5_Pos (5U)
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+#define PWR_PDCRA_PD5_Msk (0x1UL << PWR_PDCRA_PD5_Pos) /*!< 0x00000020 */
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+#define PWR_PDCRA_PD5 PWR_PDCRA_PD5_Msk /*!< Pin PA5 Pull-Down set */
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+#define PWR_PDCRA_PD6_Pos (6U)
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+#define PWR_PDCRA_PD6_Msk (0x1UL << PWR_PDCRA_PD6_Pos) /*!< 0x00000040 */
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+#define PWR_PDCRA_PD6 PWR_PDCRA_PD6_Msk /*!< Pin PA6 Pull-Down set */
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+#define PWR_PDCRA_PD7_Pos (7U)
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+#define PWR_PDCRA_PD7_Msk (0x1UL << PWR_PDCRA_PD7_Pos) /*!< 0x00000080 */
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|
+#define PWR_PDCRA_PD7 PWR_PDCRA_PD7_Msk /*!< Pin PA7 Pull-Down set */
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+#define PWR_PDCRA_PD8_Pos (8U)
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+#define PWR_PDCRA_PD8_Msk (0x1UL << PWR_PDCRA_PD8_Pos) /*!< 0x00000100 */
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|
|
+#define PWR_PDCRA_PD8 PWR_PDCRA_PD8_Msk /*!< Pin PA8 Pull-Down set */
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+#define PWR_PDCRA_PD9_Pos (9U)
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+#define PWR_PDCRA_PD9_Msk (0x1UL << PWR_PDCRA_PD9_Pos) /*!< 0x00000200 */
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|
|
+#define PWR_PDCRA_PD9 PWR_PDCRA_PD9_Msk /*!< Pin PA9 Pull-Down set */
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|
|
+#define PWR_PDCRA_PD10_Pos (10U)
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+#define PWR_PDCRA_PD10_Msk (0x1UL << PWR_PDCRA_PD10_Pos) /*!< 0x00000400 */
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|
|
+#define PWR_PDCRA_PD10 PWR_PDCRA_PD10_Msk /*!< Pin PA10 Pull-Down set */
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+#define PWR_PDCRA_PD11_Pos (11U)
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+#define PWR_PDCRA_PD11_Msk (0x1UL << PWR_PDCRA_PD11_Pos) /*!< 0x00000800 */
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+#define PWR_PDCRA_PD11 PWR_PDCRA_PD11_Msk /*!< Pin PA11 Pull-Down set */
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+#define PWR_PDCRA_PD12_Pos (12U)
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+#define PWR_PDCRA_PD12_Msk (0x1UL << PWR_PDCRA_PD12_Pos) /*!< 0x00001000 */
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+#define PWR_PDCRA_PD12 PWR_PDCRA_PD12_Msk /*!< Pin PA12 Pull-Down set */
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+#define PWR_PDCRA_PD13_Pos (13U)
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+#define PWR_PDCRA_PD13_Msk (0x1UL << PWR_PDCRA_PD13_Pos) /*!< 0x00002000 */
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+#define PWR_PDCRA_PD13 PWR_PDCRA_PD13_Msk /*!< Pin PA13 Pull-Down set */
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+#define PWR_PDCRA_PD14_Pos (14U)
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+#define PWR_PDCRA_PD14_Msk (0x1UL << PWR_PDCRA_PD14_Pos) /*!< 0x00004000 */
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+#define PWR_PDCRA_PD14 PWR_PDCRA_PD14_Msk /*!< Pin PA14 Pull-Down set */
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+#define PWR_PDCRA_PD15_Pos (15U)
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+#define PWR_PDCRA_PD15_Msk (0x1UL << PWR_PDCRA_PD15_Pos) /*!< 0x00008000 */
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+#define PWR_PDCRA_PD15 PWR_PDCRA_PD15_Msk /*!< Pin PA15 Pull-Down set */
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+
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|
+/******************** Bit definition for PWR_PUCRB register *****************/
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+#define PWR_PUCRB_PU0_Pos (0U)
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+#define PWR_PUCRB_PU0_Msk (0x1UL << PWR_PUCRB_PU0_Pos) /*!< 0x00000001 */
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+#define PWR_PUCRB_PU0 PWR_PUCRB_PU0_Msk /*!< Pin PB0 Pull-Up set */
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+#define PWR_PUCRB_PU1_Pos (1U)
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+#define PWR_PUCRB_PU1_Msk (0x1UL << PWR_PUCRB_PU1_Pos) /*!< 0x00000002 */
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+#define PWR_PUCRB_PU1 PWR_PUCRB_PU1_Msk /*!< Pin PB1 Pull-Up set */
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+#define PWR_PUCRB_PU2_Pos (2U)
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+#define PWR_PUCRB_PU2_Msk (0x1UL << PWR_PUCRB_PU2_Pos) /*!< 0x00000004 */
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+#define PWR_PUCRB_PU2 PWR_PUCRB_PU2_Msk /*!< Pin PB2 Pull-Up set */
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+#define PWR_PUCRB_PU3_Pos (3U)
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+#define PWR_PUCRB_PU3_Msk (0x1UL << PWR_PUCRB_PU3_Pos) /*!< 0x00000008 */
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+#define PWR_PUCRB_PU3 PWR_PUCRB_PU3_Msk /*!< Pin PB3 Pull-Up set */
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+#define PWR_PUCRB_PU4_Pos (4U)
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+#define PWR_PUCRB_PU4_Msk (0x1UL << PWR_PUCRB_PU4_Pos) /*!< 0x00000010 */
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+#define PWR_PUCRB_PU4 PWR_PUCRB_PU4_Msk /*!< Pin PB4 Pull-Up set */
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+#define PWR_PUCRB_PU5_Pos (5U)
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+#define PWR_PUCRB_PU5_Msk (0x1UL << PWR_PUCRB_PU5_Pos) /*!< 0x00000020 */
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+#define PWR_PUCRB_PU5 PWR_PUCRB_PU5_Msk /*!< Pin PB5 Pull-Up set */
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+#define PWR_PUCRB_PU6_Pos (6U)
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+#define PWR_PUCRB_PU6_Msk (0x1UL << PWR_PUCRB_PU6_Pos) /*!< 0x00000040 */
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+#define PWR_PUCRB_PU6 PWR_PUCRB_PU6_Msk /*!< Pin PB6 Pull-Up set */
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+#define PWR_PUCRB_PU7_Pos (7U)
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+#define PWR_PUCRB_PU7_Msk (0x1UL << PWR_PUCRB_PU7_Pos) /*!< 0x00000080 */
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+#define PWR_PUCRB_PU7 PWR_PUCRB_PU7_Msk /*!< Pin PB7 Pull-Up set */
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+#define PWR_PUCRB_PU8_Pos (8U)
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+#define PWR_PUCRB_PU8_Msk (0x1UL << PWR_PUCRB_PU8_Pos) /*!< 0x00000100 */
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+#define PWR_PUCRB_PU8 PWR_PUCRB_PU8_Msk /*!< Pin PB8 Pull-Up set */
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+#define PWR_PUCRB_PU9_Pos (9U)
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+#define PWR_PUCRB_PU9_Msk (0x1UL << PWR_PUCRB_PU9_Pos) /*!< 0x00000200 */
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+#define PWR_PUCRB_PU9 PWR_PUCRB_PU9_Msk /*!< Pin PB9 Pull-Up set */
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+#define PWR_PUCRB_PU10_Pos (10U)
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+#define PWR_PUCRB_PU10_Msk (0x1UL << PWR_PUCRB_PU10_Pos) /*!< 0x00000400 */
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+#define PWR_PUCRB_PU10 PWR_PUCRB_PU10_Msk /*!< Pin PB10 Pull-Up set */
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+#define PWR_PUCRB_PU11_Pos (11U)
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+#define PWR_PUCRB_PU11_Msk (0x1UL << PWR_PUCRB_PU11_Pos) /*!< 0x00000800 */
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|
|
+#define PWR_PUCRB_PU11 PWR_PUCRB_PU11_Msk /*!< Pin PB11 Pull-Up set */
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+#define PWR_PUCRB_PU12_Pos (12U)
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|
+#define PWR_PUCRB_PU12_Msk (0x1UL << PWR_PUCRB_PU12_Pos) /*!< 0x00001000 */
|
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|
+#define PWR_PUCRB_PU12 PWR_PUCRB_PU12_Msk /*!< Pin PB12 Pull-Up set */
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+#define PWR_PUCRB_PU13_Pos (13U)
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|
+#define PWR_PUCRB_PU13_Msk (0x1UL << PWR_PUCRB_PU13_Pos) /*!< 0x00002000 */
|
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|
+#define PWR_PUCRB_PU13 PWR_PUCRB_PU13_Msk /*!< Pin PB13 Pull-Up set */
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+#define PWR_PUCRB_PU14_Pos (14U)
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|
+#define PWR_PUCRB_PU14_Msk (0x1UL << PWR_PUCRB_PU14_Pos) /*!< 0x00004000 */
|
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|
+#define PWR_PUCRB_PU14 PWR_PUCRB_PU14_Msk /*!< Pin PB14 Pull-Up set */
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+#define PWR_PUCRB_PU15_Pos (15U)
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|
|
+#define PWR_PUCRB_PU15_Msk (0x1UL << PWR_PUCRB_PU15_Pos) /*!< 0x00008000 */
|
|
|
+#define PWR_PUCRB_PU15 PWR_PUCRB_PU15_Msk /*!< Pin PB15 Pull-Up set */
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|
|
+
|
|
|
+/******************** Bit definition for PWR_PDCRB register *****************/
|
|
|
+#define PWR_PDCRB_PD0_Pos (0U)
|
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|
+#define PWR_PDCRB_PD0_Msk (0x1UL << PWR_PDCRB_PD0_Pos) /*!< 0x00000001 */
|
|
|
+#define PWR_PDCRB_PD0 PWR_PDCRB_PD0_Msk /*!< Pin PB0 Pull-Down set */
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|
+#define PWR_PDCRB_PD1_Pos (1U)
|
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|
+#define PWR_PDCRB_PD1_Msk (0x1UL << PWR_PDCRB_PD1_Pos) /*!< 0x00000002 */
|
|
|
+#define PWR_PDCRB_PD1 PWR_PDCRB_PD1_Msk /*!< Pin PB1 Pull-Down set */
|
|
|
+#define PWR_PDCRB_PD2_Pos (2U)
|
|
|
+#define PWR_PDCRB_PD2_Msk (0x1UL << PWR_PDCRB_PD2_Pos) /*!< 0x00000004 */
|
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|
+#define PWR_PDCRB_PD2 PWR_PDCRB_PD2_Msk /*!< Pin PB2 Pull-Down set */
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|
+#define PWR_PDCRB_PD3_Pos (3U)
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|
+#define PWR_PDCRB_PD3_Msk (0x1UL << PWR_PDCRB_PD3_Pos) /*!< 0x00000008 */
|
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|
+#define PWR_PDCRB_PD3 PWR_PDCRB_PD3_Msk /*!< Pin PB3 Pull-Down set */
|
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+#define PWR_PDCRB_PD4_Pos (4U)
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|
+#define PWR_PDCRB_PD4_Msk (0x1UL << PWR_PDCRB_PD4_Pos) /*!< 0x00000010 */
|
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|
+#define PWR_PDCRB_PD4 PWR_PDCRB_PD4_Msk /*!< Pin PB4 Pull-Down set */
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+#define PWR_PDCRB_PD5_Pos (5U)
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+#define PWR_PDCRB_PD5_Msk (0x1UL << PWR_PDCRB_PD5_Pos) /*!< 0x00000020 */
|
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+#define PWR_PDCRB_PD5 PWR_PDCRB_PD5_Msk /*!< Pin PB5 Pull-Down set */
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+#define PWR_PDCRB_PD6_Pos (6U)
|
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|
+#define PWR_PDCRB_PD6_Msk (0x1UL << PWR_PDCRB_PD6_Pos) /*!< 0x00000040 */
|
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|
+#define PWR_PDCRB_PD6 PWR_PDCRB_PD6_Msk /*!< Pin PB6 Pull-Down set */
|
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+#define PWR_PDCRB_PD7_Pos (7U)
|
|
|
+#define PWR_PDCRB_PD7_Msk (0x1UL << PWR_PDCRB_PD7_Pos) /*!< 0x00000080 */
|
|
|
+#define PWR_PDCRB_PD7 PWR_PDCRB_PD7_Msk /*!< Pin PB7 Pull-Down set */
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+#define PWR_PDCRB_PD8_Pos (8U)
|
|
|
+#define PWR_PDCRB_PD8_Msk (0x1UL << PWR_PDCRB_PD8_Pos) /*!< 0x00000100 */
|
|
|
+#define PWR_PDCRB_PD8 PWR_PDCRB_PD8_Msk /*!< Pin PB8 Pull-Down set */
|
|
|
+#define PWR_PDCRB_PD9_Pos (9U)
|
|
|
+#define PWR_PDCRB_PD9_Msk (0x1UL << PWR_PDCRB_PD9_Pos) /*!< 0x00000200 */
|
|
|
+#define PWR_PDCRB_PD9 PWR_PDCRB_PD9_Msk /*!< Pin PB9 Pull-Down set */
|
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|
+#define PWR_PDCRB_PD10_Pos (10U)
|
|
|
+#define PWR_PDCRB_PD10_Msk (0x1UL << PWR_PDCRB_PD10_Pos) /*!< 0x00000400 */
|
|
|
+#define PWR_PDCRB_PD10 PWR_PDCRB_PD10_Msk /*!< Pin PB10 Pull-Down set */
|
|
|
+#define PWR_PDCRB_PD11_Pos (11U)
|
|
|
+#define PWR_PDCRB_PD11_Msk (0x1UL << PWR_PDCRB_PD11_Pos) /*!< 0x00000800 */
|
|
|
+#define PWR_PDCRB_PD11 PWR_PDCRB_PD11_Msk /*!< Pin PB11 Pull-Down set */
|
|
|
+#define PWR_PDCRB_PD12_Pos (12U)
|
|
|
+#define PWR_PDCRB_PD12_Msk (0x1UL << PWR_PDCRB_PD12_Pos) /*!< 0x00001000 */
|
|
|
+#define PWR_PDCRB_PD12 PWR_PDCRB_PD12_Msk /*!< Pin PB12 Pull-Down set */
|
|
|
+#define PWR_PDCRB_PD13_Pos (13U)
|
|
|
+#define PWR_PDCRB_PD13_Msk (0x1UL << PWR_PDCRB_PD13_Pos) /*!< 0x00002000 */
|
|
|
+#define PWR_PDCRB_PD13 PWR_PDCRB_PD13_Msk /*!< Pin PB13 Pull-Down set */
|
|
|
+#define PWR_PDCRB_PD14_Pos (14U)
|
|
|
+#define PWR_PDCRB_PD14_Msk (0x1UL << PWR_PDCRB_PD14_Pos) /*!< 0x00004000 */
|
|
|
+#define PWR_PDCRB_PD14 PWR_PDCRB_PD14_Msk /*!< Pin PB14 Pull-Down set */
|
|
|
+#define PWR_PDCRB_PD15_Pos (15U)
|
|
|
+#define PWR_PDCRB_PD15_Msk (0x1UL << PWR_PDCRB_PD15_Pos) /*!< 0x00008000 */
|
|
|
+#define PWR_PDCRB_PD15 PWR_PDCRB_PD15_Msk /*!< Pin PB15 Pull-Down set */
|
|
|
+
|
|
|
+/******************** Bit definition for PWR_PUCRC register *****************/
|
|
|
+#define PWR_PUCRC_PU6_Pos (6U)
|
|
|
+#define PWR_PUCRC_PU6_Msk (0x1UL << PWR_PUCRC_PU6_Pos) /*!< 0x00000040 */
|
|
|
+#define PWR_PUCRC_PU6 PWR_PUCRC_PU6_Msk /*!< Pin PC6 Pull-Up set */
|
|
|
+#define PWR_PUCRC_PU7_Pos (7U)
|
|
|
+#define PWR_PUCRC_PU7_Msk (0x1UL << PWR_PUCRC_PU7_Pos) /*!< 0x00000080 */
|
|
|
+#define PWR_PUCRC_PU7 PWR_PUCRC_PU7_Msk /*!< Pin PC7 Pull-Up set */
|
|
|
+#define PWR_PUCRC_PU13_Pos (13U)
|
|
|
+#define PWR_PUCRC_PU13_Msk (0x1UL << PWR_PUCRC_PU13_Pos) /*!< 0x00002000 */
|
|
|
+#define PWR_PUCRC_PU13 PWR_PUCRC_PU13_Msk /*!< Pin PC13 Pull-Up set */
|
|
|
+#define PWR_PUCRC_PU14_Pos (14U)
|
|
|
+#define PWR_PUCRC_PU14_Msk (0x1UL << PWR_PUCRC_PU14_Pos) /*!< 0x00004000 */
|
|
|
+#define PWR_PUCRC_PU14 PWR_PUCRC_PU14_Msk /*!< Pin PC14 Pull-Up set */
|
|
|
+#define PWR_PUCRC_PU15_Pos (15U)
|
|
|
+#define PWR_PUCRC_PU15_Msk (0x1UL << PWR_PUCRC_PU15_Pos) /*!< 0x00008000 */
|
|
|
+#define PWR_PUCRC_PU15 PWR_PUCRC_PU15_Msk /*!< Pin PC15 Pull-Up set */
|
|
|
+
|
|
|
+/******************** Bit definition for PWR_PDCRC register *****************/
|
|
|
+#define PWR_PDCRC_PD6_Pos (6U)
|
|
|
+#define PWR_PDCRC_PD6_Msk (0x1UL << PWR_PDCRC_PD6_Pos) /*!< 0x00000040 */
|
|
|
+#define PWR_PDCRC_PD6 PWR_PDCRC_PD6_Msk /*!< Pin PC6 Pull-Down set */
|
|
|
+#define PWR_PDCRC_PD7_Pos (7U)
|
|
|
+#define PWR_PDCRC_PD7_Msk (0x1UL << PWR_PDCRC_PD7_Pos) /*!< 0x00000080 */
|
|
|
+#define PWR_PDCRC_PD7 PWR_PDCRC_PD7_Msk /*!< Pin PC7 Pull-Down set */
|
|
|
+#define PWR_PDCRC_PD13_Pos (13U)
|
|
|
+#define PWR_PDCRC_PD13_Msk (0x1UL << PWR_PDCRC_PD13_Pos) /*!< 0x00002000 */
|
|
|
+#define PWR_PDCRC_PD13 PWR_PDCRC_PD13_Msk /*!< Pin PC13 Pull-Down set */
|
|
|
+#define PWR_PDCRC_PD14_Pos (14U)
|
|
|
+#define PWR_PDCRC_PD14_Msk (0x1UL << PWR_PDCRC_PD14_Pos) /*!< 0x00004000 */
|
|
|
+#define PWR_PDCRC_PD14 PWR_PDCRC_PD14_Msk /*!< Pin PC14 Pull-Down set */
|
|
|
+#define PWR_PDCRC_PD15_Pos (15U)
|
|
|
+#define PWR_PDCRC_PD15_Msk (0x1UL << PWR_PDCRC_PD15_Pos) /*!< 0x00008000 */
|
|
|
+#define PWR_PDCRC_PD15 PWR_PDCRC_PD15_Msk /*!< Pin PC15 Pull-Down set */
|
|
|
+
|
|
|
+/******************** Bit definition for PWR_PUCRD register *****************/
|
|
|
+#define PWR_PUCRD_PU0_Pos (0U)
|
|
|
+#define PWR_PUCRD_PU0_Msk (0x1UL << PWR_PUCRD_PU0_Pos) /*!< 0x00000001 */
|
|
|
+#define PWR_PUCRD_PU0 PWR_PUCRD_PU0_Msk /*!< Pin PD0 Pull-Up set */
|
|
|
+#define PWR_PUCRD_PU1_Pos (1U)
|
|
|
+#define PWR_PUCRD_PU1_Msk (0x1UL << PWR_PUCRD_PU1_Pos) /*!< 0x00000002 */
|
|
|
+#define PWR_PUCRD_PU1 PWR_PUCRD_PU1_Msk /*!< Pin PD1 Pull-Up set */
|
|
|
+#define PWR_PUCRD_PU2_Pos (2U)
|
|
|
+#define PWR_PUCRD_PU2_Msk (0x1UL << PWR_PUCRD_PU2_Pos) /*!< 0x00000004 */
|
|
|
+#define PWR_PUCRD_PU2 PWR_PUCRD_PU2_Msk /*!< Pin PD2 Pull-Up set */
|
|
|
+#define PWR_PUCRD_PU3_Pos (3U)
|
|
|
+#define PWR_PUCRD_PU3_Msk (0x1UL << PWR_PUCRD_PU3_Pos) /*!< 0x00000008 */
|
|
|
+#define PWR_PUCRD_PU3 PWR_PUCRD_PU3_Msk /*!< Pin PD3 Pull-Up set */
|
|
|
+
|
|
|
+/******************** Bit definition for PWR_PDCRD register *****************/
|
|
|
+#define PWR_PDCRD_PD0_Pos (0U)
|
|
|
+#define PWR_PDCRD_PD0_Msk (0x1UL << PWR_PDCRD_PD0_Pos) /*!< 0x00000001 */
|
|
|
+#define PWR_PDCRD_PD0 PWR_PDCRD_PD0_Msk /*!< Pin PD0 Pull-Down set */
|
|
|
+#define PWR_PDCRD_PD1_Pos (1U)
|
|
|
+#define PWR_PDCRD_PD1_Msk (0x1UL << PWR_PDCRD_PD1_Pos) /*!< 0x00000002 */
|
|
|
+#define PWR_PDCRD_PD1 PWR_PDCRD_PD1_Msk /*!< Pin PD1 Pull-Down set */
|
|
|
+#define PWR_PDCRD_PD2_Pos (2U)
|
|
|
+#define PWR_PDCRD_PD2_Msk (0x1UL << PWR_PDCRD_PD2_Pos) /*!< 0x00000004 */
|
|
|
+#define PWR_PDCRD_PD2 PWR_PDCRD_PD2_Msk /*!< Pin PD2 Pull-Down set */
|
|
|
+#define PWR_PDCRD_PD3_Pos (3U)
|
|
|
+#define PWR_PDCRD_PD3_Msk (0x1UL << PWR_PDCRD_PD3_Pos) /*!< 0x00000008 */
|
|
|
+#define PWR_PDCRD_PD3 PWR_PDCRD_PD3_Msk /*!< Pin PD3 Pull-Down set */
|
|
|
+
|
|
|
+/******************** Bit definition for PWR_PUCRF register *****************/
|
|
|
+#define PWR_PUCRF_PU0_Pos (0U)
|
|
|
+#define PWR_PUCRF_PU0_Msk (0x1UL << PWR_PUCRF_PU0_Pos) /*!< 0x00000001 */
|
|
|
+#define PWR_PUCRF_PU0 PWR_PUCRF_PU0_Msk /*!< Pin PF0 Pull-Up set */
|
|
|
+#define PWR_PUCRF_PU1_Pos (1U)
|
|
|
+#define PWR_PUCRF_PU1_Msk (0x1UL << PWR_PUCRF_PU1_Pos) /*!< 0x00000002 */
|
|
|
+#define PWR_PUCRF_PU1 PWR_PUCRF_PU1_Msk /*!< Pin PF1 Pull-Up set */
|
|
|
+#define PWR_PUCRF_PU2_Pos (2U)
|
|
|
+#define PWR_PUCRF_PU2_Msk (0x1UL << PWR_PUCRF_PU2_Pos) /*!< 0x00000004 */
|
|
|
+#define PWR_PUCRF_PU2 PWR_PUCRF_PU2_Msk /*!< Pin PF2 Pull-Up set */
|
|
|
+
|
|
|
+/******************** Bit definition for PWR_PDCRF register *****************/
|
|
|
+#define PWR_PDCRF_PD0_Pos (0U)
|
|
|
+#define PWR_PDCRF_PD0_Msk (0x1UL << PWR_PDCRF_PD0_Pos) /*!< 0x00000001 */
|
|
|
+#define PWR_PDCRF_PD0 PWR_PDCRF_PD0_Msk /*!< Pin PF0 Pull-Down set */
|
|
|
+#define PWR_PDCRF_PD1_Pos (1U)
|
|
|
+#define PWR_PDCRF_PD1_Msk (0x1UL << PWR_PDCRF_PD1_Pos) /*!< 0x00000002 */
|
|
|
+#define PWR_PDCRF_PD1 PWR_PDCRF_PD1_Msk /*!< Pin PF1 Pull-Down set */
|
|
|
+#define PWR_PDCRF_PD2_Pos (2U)
|
|
|
+#define PWR_PDCRF_PD2_Msk (0x1UL << PWR_PDCRF_PD2_Pos) /*!< 0x00000004 */
|
|
|
+#define PWR_PDCRF_PD2 PWR_PDCRF_PD2_Msk /*!< Pin PF2 Pull-Down set */
|
|
|
+
|
|
|
+/******************************************************************************/
|
|
|
+/* */
|
|
|
+/* Reset and Clock Control */
|
|
|
+/* */
|
|
|
+/******************************************************************************/
|
|
|
+/*
|
|
|
+* @brief Specific device feature definitions (not present on all devices in the STM32G0 series)
|
|
|
+*/
|
|
|
+
|
|
|
+/******************** Bit definition for RCC_CR register *****************/
|
|
|
+#define RCC_CR_HSION_Pos (8U)
|
|
|
+#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000100 */
|
|
|
+#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
|
|
|
+#define RCC_CR_HSIKERON_Pos (9U)
|
|
|
+#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000200 */
|
|
|
+#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */
|
|
|
+#define RCC_CR_HSIRDY_Pos (10U)
|
|
|
+#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */
|
|
|
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
|
|
|
+#define RCC_CR_HSIDIV_Pos (11U)
|
|
|
+#define RCC_CR_HSIDIV_Msk (0x7UL << RCC_CR_HSIDIV_Pos) /*!< 0x00003800 */
|
|
|
+#define RCC_CR_HSIDIV RCC_CR_HSIDIV_Msk /*!< HSIDIV[13:11] Internal High Speed clock division factor */
|
|
|
+#define RCC_CR_HSIDIV_0 (0x1UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000800 */
|
|
|
+#define RCC_CR_HSIDIV_1 (0x2UL << RCC_CR_HSIDIV_Pos) /*!< 0x00001000 */
|
|
|
+#define RCC_CR_HSIDIV_2 (0x4UL << RCC_CR_HSIDIV_Pos) /*!< 0x00002000 */
|
|
|
+#define RCC_CR_HSEON_Pos (16U)
|
|
|
+#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
|
|
|
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
|
|
|
+#define RCC_CR_HSERDY_Pos (17U)
|
|
|
+#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
|
|
|
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready */
|
|
|
+#define RCC_CR_HSEBYP_Pos (18U)
|
|
|
+#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
|
|
|
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
|
|
|
+#define RCC_CR_CSSON_Pos (19U)
|
|
|
+#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
|
|
|
+#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< HSE Clock Security System enable */
|
|
|
+
|
|
|
+#define RCC_CR_PLLON_Pos (24U)
|
|
|
+#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
|
|
|
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */
|
|
|
+#define RCC_CR_PLLRDY_Pos (25U)
|
|
|
+#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
|
|
|
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */
|
|
|
+
|
|
|
+/******************** Bit definition for RCC_ICSCR register ***************/
|
|
|
+/*!< HSICAL configuration */
|
|
|
+#define RCC_ICSCR_HSICAL_Pos (0U)
|
|
|
+#define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */
|
|
|
+#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< HSICAL[7:0] bits */
|
|
|
+#define RCC_ICSCR_HSICAL_0 (0x01UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000001 */
|
|
|
+#define RCC_ICSCR_HSICAL_1 (0x02UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000002 */
|
|
|
+#define RCC_ICSCR_HSICAL_2 (0x04UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000004 */
|
|
|
+#define RCC_ICSCR_HSICAL_3 (0x08UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000008 */
|
|
|
+#define RCC_ICSCR_HSICAL_4 (0x10UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000010 */
|
|
|
+#define RCC_ICSCR_HSICAL_5 (0x20UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000020 */
|
|
|
+#define RCC_ICSCR_HSICAL_6 (0x40UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000040 */
|
|
|
+#define RCC_ICSCR_HSICAL_7 (0x80UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000080 */
|
|
|
+
|
|
|
+/*!< HSITRIM configuration */
|
|
|
+#define RCC_ICSCR_HSITRIM_Pos (8U)
|
|
|
+#define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00007F00 */
|
|
|
+#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[14:8] bits */
|
|
|
+#define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00000100 */
|
|
|
+#define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00000200 */
|
|
|
+#define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00000400 */
|
|
|
+#define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00000800 */
|
|
|
+#define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001000 */
|
|
|
+#define RCC_ICSCR_HSITRIM_5 (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00002000 */
|
|
|
+#define RCC_ICSCR_HSITRIM_6 (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00004000 */
|
|
|
+
|
|
|
+/******************** Bit definition for RCC_CFGR register ***************/
|
|
|
+/*!< SW configuration */
|
|
|
+#define RCC_CFGR_SW_Pos (0U)
|
|
|
+#define RCC_CFGR_SW_Msk (0x7UL << RCC_CFGR_SW_Pos) /*!< 0x00000007 */
|
|
|
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[2:0] bits (System clock Switch) */
|
|
|
+#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
|
|
|
+#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
|
|
|
+#define RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos) /*!< 0x00000004 */
|
|
|
+
|
|
|
+/*!< SWS configuration */
|
|
|
+#define RCC_CFGR_SWS_Pos (3U)
|
|
|
+#define RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos) /*!< 0x00000038 */
|
|
|
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[2:0] bits (System Clock Switch Status) */
|
|
|
+#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
|
|
|
+#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */
|
|
|
+#define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */
|
|
|
+
|
|
|
+/*!< HPRE configuration */
|
|
|
+#define RCC_CFGR_HPRE_Pos (8U)
|
|
|
+#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */
|
|
|
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
|
|
|
+#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000100 */
|
|
|
+#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000200 */
|
|
|
+#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000400 */
|
|
|
+#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000800 */
|
|
|
+
|
|
|
+/*!< PPRE configuration */
|
|
|
+#define RCC_CFGR_PPRE_Pos (12U)
|
|
|
+#define RCC_CFGR_PPRE_Msk (0x7UL << RCC_CFGR_PPRE_Pos) /*!< 0x00007000 */
|
|
|
+#define RCC_CFGR_PPRE RCC_CFGR_PPRE_Msk /*!< PRE1[2:0] bits (APB prescaler) */
|
|
|
+#define RCC_CFGR_PPRE_0 (0x1UL << RCC_CFGR_PPRE_Pos) /*!< 0x00001000 */
|
|
|
+#define RCC_CFGR_PPRE_1 (0x2UL << RCC_CFGR_PPRE_Pos) /*!< 0x00002000 */
|
|
|
+#define RCC_CFGR_PPRE_2 (0x4UL << RCC_CFGR_PPRE_Pos) /*!< 0x00004000 */
|
|
|
+
|
|
|
+
|
|
|
+/*!< MCOSEL configuration */
|
|
|
+#define RCC_CFGR_MCOSEL_Pos (24U)
|
|
|
+#define RCC_CFGR_MCOSEL_Msk (0x7UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x07000000 */
|
|
|
+#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCOSEL [2:0] bits (Clock output selection) */
|
|
|
+#define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
|
|
|
+#define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
|
|
|
+#define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
|
|
|
+
|
|
|
+/*!< MCO Prescaler configuration */
|
|
|
+#define RCC_CFGR_MCOPRE_Pos (28U)
|
|
|
+#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
|
|
|
+#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler [2:0] */
|
|
|
+#define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
|
|
|
+#define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
|
|
|
+#define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
|
|
|
+
|
|
|
+/******************** Bit definition for RCC_PLLCFGR register ***************/
|
|
|
+#define RCC_PLLCFGR_PLLSRC_Pos (0U)
|
|
|
+#define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
|
|
|
+#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
|
|
|
+#define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */
|
|
|
+#define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */
|
|
|
+
|
|
|
+#define RCC_PLLCFGR_PLLSRC_NONE (0x00000000UL) /*!< No clock sent to PLL */
|
|
|
+#define RCC_PLLCFGR_PLLSRC_HSI_Pos (1U)
|
|
|
+#define RCC_PLLCFGR_PLLSRC_HSI_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSI_Pos) /*!< 0x00000002 */
|
|
|
+#define RCC_PLLCFGR_PLLSRC_HSI RCC_PLLCFGR_PLLSRC_HSI_Msk /*!< HSI source clock selected */
|
|
|
+#define RCC_PLLCFGR_PLLSRC_HSE_Pos (0U)
|
|
|
+#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00000003 */
|
|
|
+#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk /*!< HSE source clock selected */
|
|
|
+
|
|
|
+#define RCC_PLLCFGR_PLLM_Pos (4U)
|
|
|
+#define RCC_PLLCFGR_PLLM_Msk (0x7UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000070 */
|
|
|
+#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
|
|
|
+#define RCC_PLLCFGR_PLLM_0 (0x1UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
|
|
|
+#define RCC_PLLCFGR_PLLM_1 (0x2UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
|
|
|
+#define RCC_PLLCFGR_PLLM_2 (0x4UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000040 */
|
|
|
+
|
|
|
+#define RCC_PLLCFGR_PLLN_Pos (8U)
|
|
|
+#define RCC_PLLCFGR_PLLN_Msk (0x7FUL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007F00 */
|
|
|
+#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
|
|
|
+#define RCC_PLLCFGR_PLLN_0 (0x01UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
|
|
|
+#define RCC_PLLCFGR_PLLN_1 (0x02UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
|
|
|
+#define RCC_PLLCFGR_PLLN_2 (0x04UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
|
|
|
+#define RCC_PLLCFGR_PLLN_3 (0x08UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
|
|
|
+#define RCC_PLLCFGR_PLLN_4 (0x10UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
|
|
|
+#define RCC_PLLCFGR_PLLN_5 (0x20UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
|
|
|
+#define RCC_PLLCFGR_PLLN_6 (0x40UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
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+
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|
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+#define RCC_PLLCFGR_PLLPEN_Pos (16U)
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+#define RCC_PLLCFGR_PLLPEN_Msk (0x1UL << RCC_PLLCFGR_PLLPEN_Pos) /*!< 0x00010000 */
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+#define RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk
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+
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|
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+#define RCC_PLLCFGR_PLLP_Pos (17U)
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+#define RCC_PLLCFGR_PLLP_Msk (0x1FUL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x003E0000 */
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|
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+#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
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+#define RCC_PLLCFGR_PLLP_0 (0x01UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
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+#define RCC_PLLCFGR_PLLP_1 (0x02UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00040000 */
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+#define RCC_PLLCFGR_PLLP_2 (0x04UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00080000 */
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+#define RCC_PLLCFGR_PLLP_3 (0x08UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00100000 */
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+#define RCC_PLLCFGR_PLLP_4 (0x10UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00200000 */
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+
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+
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|
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+#define RCC_PLLCFGR_PLLREN_Pos (28U)
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+#define RCC_PLLCFGR_PLLREN_Msk (0x1UL << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x10000000 */
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+#define RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk
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+
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|
|
+#define RCC_PLLCFGR_PLLR_Pos (29U)
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+#define RCC_PLLCFGR_PLLR_Msk (0x7UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0xE0000000 */
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+#define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
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+#define RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x20000000 */
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+#define RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x40000000 */
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+#define RCC_PLLCFGR_PLLR_2 (0x4UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x80000000 */
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+
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|
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+/******************** Bit definition for RCC_CIER register ******************/
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+#define RCC_CIER_LSIRDYIE_Pos (0U)
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+#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
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+#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
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+#define RCC_CIER_LSERDYIE_Pos (1U)
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+#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
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+#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
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+#define RCC_CIER_HSIRDYIE_Pos (3U)
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+#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */
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|
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+#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
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+#define RCC_CIER_HSERDYIE_Pos (4U)
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+#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */
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|
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+#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
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|
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+#define RCC_CIER_PLLRDYIE_Pos (5U)
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+#define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000020 */
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+#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk
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+
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|
|
+/******************** Bit definition for RCC_CIFR register ******************/
|
|
|
+#define RCC_CIFR_LSIRDYF_Pos (0U)
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+#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
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+#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
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|
|
+#define RCC_CIFR_LSERDYF_Pos (1U)
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+#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
|
|
|
+#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
|
|
|
+#define RCC_CIFR_HSIRDYF_Pos (3U)
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|
+#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */
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|
|
+#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
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|
|
+#define RCC_CIFR_HSERDYF_Pos (4U)
|
|
|
+#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */
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|
|
+#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
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|
|
+#define RCC_CIFR_PLLRDYF_Pos (5U)
|
|
|
+#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000020 */
|
|
|
+#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
|
|
|
+#define RCC_CIFR_CSSF_Pos (8U)
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|
|
+#define RCC_CIFR_CSSF_Msk (0x1UL << RCC_CIFR_CSSF_Pos) /*!< 0x00000100 */
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|
|
+#define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk
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|
|
+#define RCC_CIFR_LSECSSF_Pos (9U)
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|
|
+#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */
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|
|
+#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
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|
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+
|
|
|
+/******************** Bit definition for RCC_CICR register ******************/
|
|
|
+#define RCC_CICR_LSIRDYC_Pos (0U)
|
|
|
+#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
|
|
|
+#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
|
|
|
+#define RCC_CICR_LSERDYC_Pos (1U)
|
|
|
+#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
|
|
|
+#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
|
|
|
+#define RCC_CICR_HSIRDYC_Pos (3U)
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|
|
+#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */
|
|
|
+#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
|
|
|
+#define RCC_CICR_HSERDYC_Pos (4U)
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|
|
+#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */
|
|
|
+#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
|
|
|
+#define RCC_CICR_PLLRDYC_Pos (5U)
|
|
|
+#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000020 */
|
|
|
+#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
|
|
|
+#define RCC_CICR_CSSC_Pos (8U)
|
|
|
+#define RCC_CICR_CSSC_Msk (0x1UL << RCC_CICR_CSSC_Pos) /*!< 0x00000100 */
|
|
|
+#define RCC_CICR_CSSC RCC_CICR_CSSC_Msk
|
|
|
+#define RCC_CICR_LSECSSC_Pos (9U)
|
|
|
+#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */
|
|
|
+#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
|
|
|
+
|
|
|
+/******************** Bit definition for RCC_IOPRSTR register ****************/
|
|
|
+#define RCC_IOPRSTR_GPIOARST_Pos (0U)
|
|
|
+#define RCC_IOPRSTR_GPIOARST_Msk (0x1UL << RCC_IOPRSTR_GPIOARST_Pos) /*!< 0x00000001 */
|
|
|
+#define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_GPIOARST_Msk
|
|
|
+#define RCC_IOPRSTR_GPIOBRST_Pos (1U)
|
|
|
+#define RCC_IOPRSTR_GPIOBRST_Msk (0x1UL << RCC_IOPRSTR_GPIOBRST_Pos) /*!< 0x00000002 */
|
|
|
+#define RCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_GPIOBRST_Msk
|
|
|
+#define RCC_IOPRSTR_GPIOCRST_Pos (2U)
|
|
|
+#define RCC_IOPRSTR_GPIOCRST_Msk (0x1UL << RCC_IOPRSTR_GPIOCRST_Pos) /*!< 0x00000004 */
|
|
|
+#define RCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_GPIOCRST_Msk
|
|
|
+#define RCC_IOPRSTR_GPIODRST_Pos (3U)
|
|
|
+#define RCC_IOPRSTR_GPIODRST_Msk (0x1UL << RCC_IOPRSTR_GPIODRST_Pos) /*!< 0x00000008 */
|
|
|
+#define RCC_IOPRSTR_GPIODRST RCC_IOPRSTR_GPIODRST_Msk
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|
|
+#define RCC_IOPRSTR_GPIOFRST_Pos (5U)
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|
+#define RCC_IOPRSTR_GPIOFRST_Msk (0x1UL << RCC_IOPRSTR_GPIOFRST_Pos) /*!< 0x00000020 */
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|
|
+#define RCC_IOPRSTR_GPIOFRST RCC_IOPRSTR_GPIOFRST_Msk
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|
|
+
|
|
|
+/******************** Bit definition for RCC_AHBRSTR register ***************/
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|
|
+#define RCC_AHBRSTR_DMA1RST_Pos (0U)
|
|
|
+#define RCC_AHBRSTR_DMA1RST_Msk (0x1UL << RCC_AHBRSTR_DMA1RST_Pos) /*!< 0x00000001 */
|
|
|
+#define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMA1RST_Msk
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|
|
+#define RCC_AHBRSTR_FLASHRST_Pos (8U)
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|
|
+#define RCC_AHBRSTR_FLASHRST_Msk (0x1UL << RCC_AHBRSTR_FLASHRST_Pos) /*!< 0x00000100 */
|
|
|
+#define RCC_AHBRSTR_FLASHRST RCC_AHBRSTR_FLASHRST_Msk
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|
|
+#define RCC_AHBRSTR_CRCRST_Pos (12U)
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|
|
+#define RCC_AHBRSTR_CRCRST_Msk (0x1UL << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */
|
|
|
+#define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk
|
|
|
+
|
|
|
+/******************** Bit definition for RCC_APBRSTR1 register **************/
|
|
|
+#define RCC_APBRSTR1_TIM3RST_Pos (1U)
|
|
|
+#define RCC_APBRSTR1_TIM3RST_Msk (0x1UL << RCC_APBRSTR1_TIM3RST_Pos) /*!< 0x00000002 */
|
|
|
+#define RCC_APBRSTR1_TIM3RST RCC_APBRSTR1_TIM3RST_Msk
|
|
|
+#define RCC_APBRSTR1_SPI2RST_Pos (14U)
|
|
|
+#define RCC_APBRSTR1_SPI2RST_Msk (0x1UL << RCC_APBRSTR1_SPI2RST_Pos) /*!< 0x00004000 */
|
|
|
+#define RCC_APBRSTR1_SPI2RST RCC_APBRSTR1_SPI2RST_Msk
|
|
|
+#define RCC_APBRSTR1_USART2RST_Pos (17U)
|
|
|
+#define RCC_APBRSTR1_USART2RST_Msk (0x1UL << RCC_APBRSTR1_USART2RST_Pos) /*!< 0x00020000 */
|
|
|
+#define RCC_APBRSTR1_USART2RST RCC_APBRSTR1_USART2RST_Msk
|
|
|
+#define RCC_APBRSTR1_I2C1RST_Pos (21U)
|
|
|
+#define RCC_APBRSTR1_I2C1RST_Msk (0x1UL << RCC_APBRSTR1_I2C1RST_Pos) /*!< 0x00200000 */
|
|
|
+#define RCC_APBRSTR1_I2C1RST RCC_APBRSTR1_I2C1RST_Msk
|
|
|
+#define RCC_APBRSTR1_I2C2RST_Pos (22U)
|
|
|
+#define RCC_APBRSTR1_I2C2RST_Msk (0x1UL << RCC_APBRSTR1_I2C2RST_Pos) /*!< 0x00400000 */
|
|
|
+#define RCC_APBRSTR1_I2C2RST RCC_APBRSTR1_I2C2RST_Msk
|
|
|
+#define RCC_APBRSTR1_DBGRST_Pos (27U)
|
|
|
+#define RCC_APBRSTR1_DBGRST_Msk (0x1UL << RCC_APBRSTR1_DBGRST_Pos) /*!< 0x08000000 */
|
|
|
+#define RCC_APBRSTR1_DBGRST RCC_APBRSTR1_DBGRST_Msk
|
|
|
+#define RCC_APBRSTR1_PWRRST_Pos (28U)
|
|
|
+#define RCC_APBRSTR1_PWRRST_Msk (0x1UL << RCC_APBRSTR1_PWRRST_Pos) /*!< 0x10000000 */
|
|
|
+#define RCC_APBRSTR1_PWRRST RCC_APBRSTR1_PWRRST_Msk
|
|
|
+
|
|
|
+/******************** Bit definition for RCC_APBRSTR2 register **************/
|
|
|
+#define RCC_APBRSTR2_SYSCFGRST_Pos (0U)
|
|
|
+#define RCC_APBRSTR2_SYSCFGRST_Msk (0x1UL << RCC_APBRSTR2_SYSCFGRST_Pos) /*!< 0x00000001 */
|
|
|
+#define RCC_APBRSTR2_SYSCFGRST RCC_APBRSTR2_SYSCFGRST_Msk
|
|
|
+#define RCC_APBRSTR2_TIM1RST_Pos (11U)
|
|
|
+#define RCC_APBRSTR2_TIM1RST_Msk (0x1UL << RCC_APBRSTR2_TIM1RST_Pos) /*!< 0x00000800 */
|
|
|
+#define RCC_APBRSTR2_TIM1RST RCC_APBRSTR2_TIM1RST_Msk
|
|
|
+#define RCC_APBRSTR2_SPI1RST_Pos (12U)
|
|
|
+#define RCC_APBRSTR2_SPI1RST_Msk (0x1UL << RCC_APBRSTR2_SPI1RST_Pos) /*!< 0x00001000 */
|
|
|
+#define RCC_APBRSTR2_SPI1RST RCC_APBRSTR2_SPI1RST_Msk
|
|
|
+#define RCC_APBRSTR2_USART1RST_Pos (14U)
|
|
|
+#define RCC_APBRSTR2_USART1RST_Msk (0x1UL << RCC_APBRSTR2_USART1RST_Pos) /*!< 0x00004000 */
|
|
|
+#define RCC_APBRSTR2_USART1RST RCC_APBRSTR2_USART1RST_Msk
|
|
|
+#define RCC_APBRSTR2_TIM14RST_Pos (15U)
|
|
|
+#define RCC_APBRSTR2_TIM14RST_Msk (0x1UL << RCC_APBRSTR2_TIM14RST_Pos) /*!< 0x00008000 */
|
|
|
+#define RCC_APBRSTR2_TIM14RST RCC_APBRSTR2_TIM14RST_Msk
|
|
|
+#define RCC_APBRSTR2_TIM16RST_Pos (17U)
|
|
|
+#define RCC_APBRSTR2_TIM16RST_Msk (0x1UL << RCC_APBRSTR2_TIM16RST_Pos) /*!< 0x00020000 */
|
|
|
+#define RCC_APBRSTR2_TIM16RST RCC_APBRSTR2_TIM16RST_Msk
|
|
|
+#define RCC_APBRSTR2_TIM17RST_Pos (18U)
|
|
|
+#define RCC_APBRSTR2_TIM17RST_Msk (0x1UL << RCC_APBRSTR2_TIM17RST_Pos) /*!< 0x00040000 */
|
|
|
+#define RCC_APBRSTR2_TIM17RST RCC_APBRSTR2_TIM17RST_Msk
|
|
|
+#define RCC_APBRSTR2_ADCRST_Pos (20U)
|
|
|
+#define RCC_APBRSTR2_ADCRST_Msk (0x1UL << RCC_APBRSTR2_ADCRST_Pos) /*!< 0x00100000 */
|
|
|
+#define RCC_APBRSTR2_ADCRST RCC_APBRSTR2_ADCRST_Msk
|
|
|
+
|
|
|
+/******************** Bit definition for RCC_IOPENR register ****************/
|
|
|
+#define RCC_IOPENR_GPIOAEN_Pos (0U)
|
|
|
+#define RCC_IOPENR_GPIOAEN_Msk (0x1UL << RCC_IOPENR_GPIOAEN_Pos) /*!< 0x00000001 */
|
|
|
+#define RCC_IOPENR_GPIOAEN RCC_IOPENR_GPIOAEN_Msk
|
|
|
+#define RCC_IOPENR_GPIOBEN_Pos (1U)
|
|
|
+#define RCC_IOPENR_GPIOBEN_Msk (0x1UL << RCC_IOPENR_GPIOBEN_Pos) /*!< 0x00000002 */
|
|
|
+#define RCC_IOPENR_GPIOBEN RCC_IOPENR_GPIOBEN_Msk
|
|
|
+#define RCC_IOPENR_GPIOCEN_Pos (2U)
|
|
|
+#define RCC_IOPENR_GPIOCEN_Msk (0x1UL << RCC_IOPENR_GPIOCEN_Pos) /*!< 0x00000004 */
|
|
|
+#define RCC_IOPENR_GPIOCEN RCC_IOPENR_GPIOCEN_Msk
|
|
|
+#define RCC_IOPENR_GPIODEN_Pos (3U)
|
|
|
+#define RCC_IOPENR_GPIODEN_Msk (0x1UL << RCC_IOPENR_GPIODEN_Pos) /*!< 0x00000008 */
|
|
|
+#define RCC_IOPENR_GPIODEN RCC_IOPENR_GPIODEN_Msk
|
|
|
+#define RCC_IOPENR_GPIOFEN_Pos (5U)
|
|
|
+#define RCC_IOPENR_GPIOFEN_Msk (0x1UL << RCC_IOPENR_GPIOFEN_Pos) /*!< 0x00000020 */
|
|
|
+#define RCC_IOPENR_GPIOFEN RCC_IOPENR_GPIOFEN_Msk
|
|
|
+
|
|
|
+/******************** Bit definition for RCC_AHBENR register ****************/
|
|
|
+#define RCC_AHBENR_DMA1EN_Pos (0U)
|
|
|
+#define RCC_AHBENR_DMA1EN_Msk (0x1UL << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */
|
|
|
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk
|
|
|
+#define RCC_AHBENR_FLASHEN_Pos (8U)
|
|
|
+#define RCC_AHBENR_FLASHEN_Msk (0x1UL << RCC_AHBENR_FLASHEN_Pos) /*!< 0x00000100 */
|
|
|
+#define RCC_AHBENR_FLASHEN RCC_AHBENR_FLASHEN_Msk
|
|
|
+#define RCC_AHBENR_CRCEN_Pos (12U)
|
|
|
+#define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */
|
|
|
+#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk
|
|
|
+
|
|
|
+/******************** Bit definition for RCC_APBENR1 register ***************/
|
|
|
+#define RCC_APBENR1_TIM3EN_Pos (1U)
|
|
|
+#define RCC_APBENR1_TIM3EN_Msk (0x1UL << RCC_APBENR1_TIM3EN_Pos) /*!< 0x00000002 */
|
|
|
+#define RCC_APBENR1_TIM3EN RCC_APBENR1_TIM3EN_Msk
|
|
|
+#define RCC_APBENR1_RTCAPBEN_Pos (10U)
|
|
|
+#define RCC_APBENR1_RTCAPBEN_Msk (0x1UL << RCC_APBENR1_RTCAPBEN_Pos) /*!< 0x00000400 */
|
|
|
+#define RCC_APBENR1_RTCAPBEN RCC_APBENR1_RTCAPBEN_Msk
|
|
|
+#define RCC_APBENR1_WWDGEN_Pos (11U)
|
|
|
+#define RCC_APBENR1_WWDGEN_Msk (0x1UL << RCC_APBENR1_WWDGEN_Pos) /*!< 0x00000800 */
|
|
|
+#define RCC_APBENR1_WWDGEN RCC_APBENR1_WWDGEN_Msk
|
|
|
+#define RCC_APBENR1_SPI2EN_Pos (14U)
|
|
|
+#define RCC_APBENR1_SPI2EN_Msk (0x1UL << RCC_APBENR1_SPI2EN_Pos) /*!< 0x00004000 */
|
|
|
+#define RCC_APBENR1_SPI2EN RCC_APBENR1_SPI2EN_Msk
|
|
|
+#define RCC_APBENR1_USART2EN_Pos (17U)
|
|
|
+#define RCC_APBENR1_USART2EN_Msk (0x1UL << RCC_APBENR1_USART2EN_Pos) /*!< 0x00020000 */
|
|
|
+#define RCC_APBENR1_USART2EN RCC_APBENR1_USART2EN_Msk
|
|
|
+#define RCC_APBENR1_I2C1EN_Pos (21U)
|
|
|
+#define RCC_APBENR1_I2C1EN_Msk (0x1UL << RCC_APBENR1_I2C1EN_Pos) /*!< 0x00200000 */
|
|
|
+#define RCC_APBENR1_I2C1EN RCC_APBENR1_I2C1EN_Msk
|
|
|
+#define RCC_APBENR1_I2C2EN_Pos (22U)
|
|
|
+#define RCC_APBENR1_I2C2EN_Msk (0x1UL << RCC_APBENR1_I2C2EN_Pos) /*!< 0x00400000 */
|
|
|
+#define RCC_APBENR1_I2C2EN RCC_APBENR1_I2C2EN_Msk
|
|
|
+#define RCC_APBENR1_DBGEN_Pos (27U)
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+#define RCC_APBENR1_DBGEN_Msk (0x1UL << RCC_APBENR1_DBGEN_Pos) /*!< 0x08000000 */
|
|
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+#define RCC_APBENR1_DBGEN RCC_APBENR1_DBGEN_Msk
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+#define RCC_APBENR1_PWREN_Pos (28U)
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+#define RCC_APBENR1_PWREN_Msk (0x1UL << RCC_APBENR1_PWREN_Pos) /*!< 0x10000000 */
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|
|
+#define RCC_APBENR1_PWREN RCC_APBENR1_PWREN_Msk
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|
|
+
|
|
|
+/******************** Bit definition for RCC_APBENR2 register **************/
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|
|
+#define RCC_APBENR2_SYSCFGEN_Pos (0U)
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+#define RCC_APBENR2_SYSCFGEN_Msk (0x1UL << RCC_APBENR2_SYSCFGEN_Pos) /*!< 0x00000001 */
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+#define RCC_APBENR2_SYSCFGEN RCC_APBENR2_SYSCFGEN_Msk
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|
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+#define RCC_APBENR2_TIM1EN_Pos (11U)
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+#define RCC_APBENR2_TIM1EN_Msk (0x1UL << RCC_APBENR2_TIM1EN_Pos) /*!< 0x00000800 */
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|
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+#define RCC_APBENR2_TIM1EN RCC_APBENR2_TIM1EN_Msk
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|
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+#define RCC_APBENR2_SPI1EN_Pos (12U)
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+#define RCC_APBENR2_SPI1EN_Msk (0x1UL << RCC_APBENR2_SPI1EN_Pos) /*!< 0x00001000 */
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+#define RCC_APBENR2_SPI1EN RCC_APBENR2_SPI1EN_Msk
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+#define RCC_APBENR2_USART1EN_Pos (14U)
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+#define RCC_APBENR2_USART1EN_Msk (0x1UL << RCC_APBENR2_USART1EN_Pos) /*!< 0x00004000 */
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+#define RCC_APBENR2_USART1EN RCC_APBENR2_USART1EN_Msk
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+#define RCC_APBENR2_TIM14EN_Pos (15U)
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+#define RCC_APBENR2_TIM14EN_Msk (0x1UL << RCC_APBENR2_TIM14EN_Pos) /*!< 0x00008000 */
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+#define RCC_APBENR2_TIM14EN RCC_APBENR2_TIM14EN_Msk
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+#define RCC_APBENR2_TIM16EN_Pos (17U)
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+#define RCC_APBENR2_TIM16EN_Msk (0x1UL << RCC_APBENR2_TIM16EN_Pos) /*!< 0x00020000 */
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+#define RCC_APBENR2_TIM16EN RCC_APBENR2_TIM16EN_Msk
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+#define RCC_APBENR2_TIM17EN_Pos (18U)
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+#define RCC_APBENR2_TIM17EN_Msk (0x1UL << RCC_APBENR2_TIM17EN_Pos) /*!< 0x00040000 */
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+#define RCC_APBENR2_TIM17EN RCC_APBENR2_TIM17EN_Msk
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+#define RCC_APBENR2_ADCEN_Pos (20U)
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+#define RCC_APBENR2_ADCEN_Msk (0x1UL << RCC_APBENR2_ADCEN_Pos) /*!< 0x00100000 */
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+#define RCC_APBENR2_ADCEN RCC_APBENR2_ADCEN_Msk
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+
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|
|
+/******************** Bit definition for RCC_IOPSMENR register *************/
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+#define RCC_IOPSMENR_GPIOASMEN_Pos (0U)
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+#define RCC_IOPSMENR_GPIOASMEN_Msk (0x1UL << RCC_IOPSMENR_GPIOASMEN_Pos) /*!< 0x00000001 */
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+#define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_GPIOASMEN_Msk
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+#define RCC_IOPSMENR_GPIOBSMEN_Pos (1U)
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+#define RCC_IOPSMENR_GPIOBSMEN_Msk (0x1UL << RCC_IOPSMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */
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+#define RCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_GPIOBSMEN_Msk
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+#define RCC_IOPSMENR_GPIOCSMEN_Pos (2U)
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+#define RCC_IOPSMENR_GPIOCSMEN_Msk (0x1UL << RCC_IOPSMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */
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+#define RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_GPIOCSMEN_Msk
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+#define RCC_IOPSMENR_GPIODSMEN_Pos (3U)
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+#define RCC_IOPSMENR_GPIODSMEN_Msk (0x1UL << RCC_IOPSMENR_GPIODSMEN_Pos) /*!< 0x00000008 */
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+#define RCC_IOPSMENR_GPIODSMEN RCC_IOPSMENR_GPIODSMEN_Msk
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+#define RCC_IOPSMENR_GPIOFSMEN_Pos (5U)
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+#define RCC_IOPSMENR_GPIOFSMEN_Msk (0x1UL << RCC_IOPSMENR_GPIOFSMEN_Pos) /*!< 0x00000020 */
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+#define RCC_IOPSMENR_GPIOFSMEN RCC_IOPSMENR_GPIOFSMEN_Msk
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+
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|
|
+/******************** Bit definition for RCC_AHBSMENR register *************/
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|
+#define RCC_AHBSMENR_DMA1SMEN_Pos (0U)
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+#define RCC_AHBSMENR_DMA1SMEN_Msk (0x1UL << RCC_AHBSMENR_DMA1SMEN_Pos) /*!< 0x00000001 */
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|
+#define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMA1SMEN_Msk
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|
+#define RCC_AHBSMENR_FLASHSMEN_Pos (8U)
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+#define RCC_AHBSMENR_FLASHSMEN_Msk (0x1UL << RCC_AHBSMENR_FLASHSMEN_Pos) /*!< 0x00000100 */
|
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|
+#define RCC_AHBSMENR_FLASHSMEN RCC_AHBSMENR_FLASHSMEN_Msk
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|
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+#define RCC_AHBSMENR_SRAMSMEN_Pos (9U)
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+#define RCC_AHBSMENR_SRAMSMEN_Msk (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos) /*!< 0x00000200 */
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|
+#define RCC_AHBSMENR_SRAMSMEN RCC_AHBSMENR_SRAMSMEN_Msk
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+#define RCC_AHBSMENR_CRCSMEN_Pos (12U)
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+#define RCC_AHBSMENR_CRCSMEN_Msk (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos) /*!< 0x00001000 */
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|
+#define RCC_AHBSMENR_CRCSMEN RCC_AHBSMENR_CRCSMEN_Msk
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+
|
|
|
+/******************** Bit definition for RCC_APBSMENR1 register *************/
|
|
|
+#define RCC_APBSMENR1_TIM3SMEN_Pos (1U)
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|
+#define RCC_APBSMENR1_TIM3SMEN_Msk (0x1UL << RCC_APBSMENR1_TIM3SMEN_Pos) /*!< 0x00000002 */
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|
|
+#define RCC_APBSMENR1_TIM3SMEN RCC_APBSMENR1_TIM3SMEN_Msk
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|
|
+#define RCC_APBSMENR1_RTCAPBSMEN_Pos (10U)
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|
|
+#define RCC_APBSMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APBSMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */
|
|
|
+#define RCC_APBSMENR1_RTCAPBSMEN RCC_APBSMENR1_RTCAPBSMEN_Msk
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|
|
+#define RCC_APBSMENR1_WWDGSMEN_Pos (11U)
|
|
|
+#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
|
|
|
+#define RCC_APBSMENR1_WWDGSMEN RCC_APBSMENR1_WWDGSMEN_Msk
|
|
|
+#define RCC_APBSMENR1_SPI2SMEN_Pos (14U)
|
|
|
+#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
|
|
|
+#define RCC_APBSMENR1_SPI2SMEN RCC_APBSMENR1_SPI2SMEN_Msk
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|
|
+#define RCC_APBSMENR1_USART2SMEN_Pos (17U)
|
|
|
+#define RCC_APBSMENR1_USART2SMEN_Msk (0x1UL << RCC_APBSMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
|
|
|
+#define RCC_APBSMENR1_USART2SMEN RCC_APBSMENR1_USART2SMEN_Msk
|
|
|
+#define RCC_APBSMENR1_I2C1SMEN_Pos (21U)
|
|
|
+#define RCC_APBSMENR1_I2C1SMEN_Msk (0x1UL << RCC_APBSMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */
|
|
|
+#define RCC_APBSMENR1_I2C1SMEN RCC_APBSMENR1_I2C1SMEN_Msk
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|
|
+#define RCC_APBSMENR1_I2C2SMEN_Pos (22U)
|
|
|
+#define RCC_APBSMENR1_I2C2SMEN_Msk (0x1UL << RCC_APBSMENR1_I2C2SMEN_Pos) /*!< 0x00400000 */
|
|
|
+#define RCC_APBSMENR1_I2C2SMEN RCC_APBSMENR1_I2C2SMEN_Msk
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|
|
+#define RCC_APBSMENR1_DBGSMEN_Pos (27U)
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|
+#define RCC_APBSMENR1_DBGSMEN_Msk (0x1UL << RCC_APBSMENR1_DBGSMEN_Pos) /*!< 0x08000000 */
|
|
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+#define RCC_APBSMENR1_DBGSMEN RCC_APBSMENR1_DBGSMEN_Msk
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|
|
+#define RCC_APBSMENR1_PWRSMEN_Pos (28U)
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|
|
+#define RCC_APBSMENR1_PWRSMEN_Msk (0x1UL << RCC_APBSMENR1_PWRSMEN_Pos) /*!< 0x10000000 */
|
|
|
+#define RCC_APBSMENR1_PWRSMEN RCC_APBSMENR1_PWRSMEN_Msk
|
|
|
+
|
|
|
+/******************** Bit definition for RCC_APBSMENR2 register *************/
|
|
|
+#define RCC_APBSMENR2_SYSCFGSMEN_Pos (0U)
|
|
|
+#define RCC_APBSMENR2_SYSCFGSMEN_Msk (0x1UL << RCC_APBSMENR2_SYSCFGSMEN_Pos) /*!< 0x00000001 */
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|
|
+#define RCC_APBSMENR2_SYSCFGSMEN RCC_APBSMENR2_SYSCFGSMEN_Msk
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|
|
+#define RCC_APBSMENR2_TIM1SMEN_Pos (11U)
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|
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+#define RCC_APBSMENR2_TIM1SMEN_Msk (0x1UL << RCC_APBSMENR2_TIM1SMEN_Pos) /*!< 0x00000800 */
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|
|
+#define RCC_APBSMENR2_TIM1SMEN RCC_APBSMENR2_TIM1SMEN_Msk
|
|
|
+#define RCC_APBSMENR2_SPI1SMEN_Pos (12U)
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|
+#define RCC_APBSMENR2_SPI1SMEN_Msk (0x1UL << RCC_APBSMENR2_SPI1SMEN_Pos) /*!< 0x00001000 */
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|
|
+#define RCC_APBSMENR2_SPI1SMEN RCC_APBSMENR2_SPI1SMEN_Msk
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|
|
+#define RCC_APBSMENR2_USART1SMEN_Pos (14U)
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|
+#define RCC_APBSMENR2_USART1SMEN_Msk (0x1UL << RCC_APBSMENR2_USART1SMEN_Pos) /*!< 0x00004000 */
|
|
|
+#define RCC_APBSMENR2_USART1SMEN RCC_APBSMENR2_USART1SMEN_Msk
|
|
|
+#define RCC_APBSMENR2_TIM14SMEN_Pos (15U)
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|
|
+#define RCC_APBSMENR2_TIM14SMEN_Msk (0x1UL << RCC_APBSMENR2_TIM14SMEN_Pos) /*!< 0x00008000 */
|
|
|
+#define RCC_APBSMENR2_TIM14SMEN RCC_APBSMENR2_TIM14SMEN_Msk
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|
+#define RCC_APBSMENR2_TIM16SMEN_Pos (17U)
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|
+#define RCC_APBSMENR2_TIM16SMEN_Msk (0x1UL << RCC_APBSMENR2_TIM16SMEN_Pos) /*!< 0x00020000 */
|
|
|
+#define RCC_APBSMENR2_TIM16SMEN RCC_APBSMENR2_TIM16SMEN_Msk
|
|
|
+#define RCC_APBSMENR2_TIM17SMEN_Pos (18U)
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|
+#define RCC_APBSMENR2_TIM17SMEN_Msk (0x1UL << RCC_APBSMENR2_TIM17SMEN_Pos) /*!< 0x00040000 */
|
|
|
+#define RCC_APBSMENR2_TIM17SMEN RCC_APBSMENR2_TIM17SMEN_Msk
|
|
|
+#define RCC_APBSMENR2_ADCSMEN_Pos (20U)
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|
+#define RCC_APBSMENR2_ADCSMEN_Msk (0x1UL << RCC_APBSMENR2_ADCSMEN_Pos) /*!< 0x00100000 */
|
|
|
+#define RCC_APBSMENR2_ADCSMEN RCC_APBSMENR2_ADCSMEN_Msk
|
|
|
+
|
|
|
+/******************** Bit definition for RCC_CCIPR register ******************/
|
|
|
+#define RCC_CCIPR_USART1SEL_Pos (0U)
|
|
|
+#define RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */
|
|
|
+#define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk
|
|
|
+#define RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */
|
|
|
+#define RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+#define RCC_CCIPR_I2C1SEL_Pos (12U)
|
|
|
+#define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
|
|
|
+#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk
|
|
|
+#define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
|
|
|
+#define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
|
|
|
+
|
|
|
+#define RCC_CCIPR_I2S1SEL_Pos (14U)
|
|
|
+#define RCC_CCIPR_I2S1SEL_Msk (0x3UL << RCC_CCIPR_I2S1SEL_Pos) /*!< 0x0000C000 */
|
|
|
+#define RCC_CCIPR_I2S1SEL RCC_CCIPR_I2S1SEL_Msk
|
|
|
+#define RCC_CCIPR_I2S1SEL_0 (0x1UL << RCC_CCIPR_I2S1SEL_Pos) /*!< 0x00004000 */
|
|
|
+#define RCC_CCIPR_I2S1SEL_1 (0x2UL << RCC_CCIPR_I2S1SEL_Pos) /*!< 0x00008000 */
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+#define RCC_CCIPR_ADCSEL_Pos (30U)
|
|
|
+#define RCC_CCIPR_ADCSEL_Msk (0x3UL << RCC_CCIPR_ADCSEL_Pos) /*!< 0xC0000000 */
|
|
|
+#define RCC_CCIPR_ADCSEL RCC_CCIPR_ADCSEL_Msk
|
|
|
+#define RCC_CCIPR_ADCSEL_0 (0x1UL << RCC_CCIPR_ADCSEL_Pos) /*!< 0x40000000 */
|
|
|
+#define RCC_CCIPR_ADCSEL_1 (0x2UL << RCC_CCIPR_ADCSEL_Pos) /*!< 0x80000000 */
|
|
|
+
|
|
|
+/******************** Bit definition for RCC_BDCR register ******************/
|
|
|
+#define RCC_BDCR_LSEON_Pos (0U)
|
|
|
+#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
|
|
|
+#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
|
|
|
+#define RCC_BDCR_LSERDY_Pos (1U)
|
|
|
+#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
|
|
|
+#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
|
|
|
+#define RCC_BDCR_LSEBYP_Pos (2U)
|
|
|
+#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
|
|
|
+#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
|
|
|
+
|
|
|
+#define RCC_BDCR_LSEDRV_Pos (3U)
|
|
|
+#define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
|
|
|
+#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
|
|
|
+#define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
|
|
|
+#define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
|
|
|
+
|
|
|
+#define RCC_BDCR_LSECSSON_Pos (5U)
|
|
|
+#define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */
|
|
|
+#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
|
|
|
+#define RCC_BDCR_LSECSSD_Pos (6U)
|
|
|
+#define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */
|
|
|
+#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
|
|
|
+
|
|
|
+#define RCC_BDCR_RTCSEL_Pos (8U)
|
|
|
+#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
|
|
|
+#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
|
|
|
+#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
|
|
|
+#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
|
|
|
+
|
|
|
+#define RCC_BDCR_RTCEN_Pos (15U)
|
|
|
+#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
|
|
|
+#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
|
|
|
+#define RCC_BDCR_BDRST_Pos (16U)
|
|
|
+#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
|
|
|
+#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
|
|
|
+
|
|
|
+#define RCC_BDCR_LSCOEN_Pos (24U)
|
|
|
+#define RCC_BDCR_LSCOEN_Msk (0x1UL << RCC_BDCR_LSCOEN_Pos) /*!< 0x01000000 */
|
|
|
+#define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk
|
|
|
+#define RCC_BDCR_LSCOSEL_Pos (25U)
|
|
|
+#define RCC_BDCR_LSCOSEL_Msk (0x1UL << RCC_BDCR_LSCOSEL_Pos) /*!< 0x02000000 */
|
|
|
+#define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk
|
|
|
+
|
|
|
+/******************** Bit definition for RCC_CSR register *******************/
|
|
|
+#define RCC_CSR_LSION_Pos (0U)
|
|
|
+#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
|
|
|
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk
|
|
|
+#define RCC_CSR_LSIRDY_Pos (1U)
|
|
|
+#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
|
|
|
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
|
|
|
+
|
|
|
+#define RCC_CSR_RMVF_Pos (23U)
|
|
|
+#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
|
|
|
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
|
|
|
+#define RCC_CSR_OBLRSTF_Pos (25U)
|
|
|
+#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
|
|
|
+#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk
|
|
|
+#define RCC_CSR_PINRSTF_Pos (26U)
|
|
|
+#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
|
|
|
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
|
|
|
+#define RCC_CSR_PWRRSTF_Pos (27U)
|
|
|
+#define RCC_CSR_PWRRSTF_Msk (0x1UL << RCC_CSR_PWRRSTF_Pos) /*!< 0x08000000 */
|
|
|
+#define RCC_CSR_PWRRSTF RCC_CSR_PWRRSTF_Msk
|
|
|
+#define RCC_CSR_SFTRSTF_Pos (28U)
|
|
|
+#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
|
|
|
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
|
|
|
+#define RCC_CSR_IWDGRSTF_Pos (29U)
|
|
|
+#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
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|
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+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
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+#define RCC_CSR_WWDGRSTF_Pos (30U)
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+#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
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|
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+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
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|
|
+#define RCC_CSR_LPWRRSTF_Pos (31U)
|
|
|
+#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
|
|
|
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
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|
+
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|
|
+/******************************************************************************/
|
|
|
+/* */
|
|
|
+/* Real-Time Clock (RTC) */
|
|
|
+/* */
|
|
|
+/******************************************************************************/
|
|
|
+/*
|
|
|
+* @brief Specific device feature definitions
|
|
|
+*/
|
|
|
+#define RTC_WAKEUP_SUPPORT
|
|
|
+#define RTC_BACKUP_SUPPORT
|
|
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+
|
|
|
+/******************** Bits definition for RTC_TR register *******************/
|
|
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+#define RTC_TR_PM_Pos (22U)
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+#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
|
|
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+#define RTC_TR_PM RTC_TR_PM_Msk
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|
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+#define RTC_TR_HT_Pos (20U)
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+#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
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+#define RTC_TR_HT RTC_TR_HT_Msk
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+#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
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+#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
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|
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+#define RTC_TR_HU_Pos (16U)
|
|
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+#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
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+#define RTC_TR_HU RTC_TR_HU_Msk
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|
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+#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
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+#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
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+#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
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+#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
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|
|
+#define RTC_TR_MNT_Pos (12U)
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|
+#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
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|
|
+#define RTC_TR_MNT RTC_TR_MNT_Msk
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+#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
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+#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
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+#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
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|
+#define RTC_TR_MNU_Pos (8U)
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+#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
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|
|
+#define RTC_TR_MNU RTC_TR_MNU_Msk
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|
+#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
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|
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+#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
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+#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
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|
|
+#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
|
|
|
+#define RTC_TR_ST_Pos (4U)
|
|
|
+#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
|
|
|
+#define RTC_TR_ST RTC_TR_ST_Msk
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|
+#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
|
|
|
+#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
|
|
|
+#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
|
|
|
+#define RTC_TR_SU_Pos (0U)
|
|
|
+#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
|
|
|
+#define RTC_TR_SU RTC_TR_SU_Msk
|
|
|
+#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
|
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|
+#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
|
|
|
+#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
|
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|
+#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
|
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|
+
|
|
|
+/******************** Bits definition for RTC_DR register *******************/
|
|
|
+#define RTC_DR_YT_Pos (20U)
|
|
|
+#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
|
|
|
+#define RTC_DR_YT RTC_DR_YT_Msk
|
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|
+#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
|
|
|
+#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
|
|
|
+#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
|
|
|
+#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
|
|
|
+#define RTC_DR_YU_Pos (16U)
|
|
|
+#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
|
|
|
+#define RTC_DR_YU RTC_DR_YU_Msk
|
|
|
+#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
|
|
|
+#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
|
|
|
+#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
|
|
|
+#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
|
|
|
+#define RTC_DR_WDU_Pos (13U)
|
|
|
+#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
|
|
|
+#define RTC_DR_WDU RTC_DR_WDU_Msk
|
|
|
+#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
|
|
|
+#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
|
|
|
+#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
|
|
|
+#define RTC_DR_MT_Pos (12U)
|
|
|
+#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
|
|
|
+#define RTC_DR_MT RTC_DR_MT_Msk
|
|
|
+#define RTC_DR_MU_Pos (8U)
|
|
|
+#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
|
|
|
+#define RTC_DR_MU RTC_DR_MU_Msk
|
|
|
+#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
|
|
|
+#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
|
|
|
+#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
|
|
|
+#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
|
|
|
+#define RTC_DR_DT_Pos (4U)
|
|
|
+#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
|
|
|
+#define RTC_DR_DT RTC_DR_DT_Msk
|
|
|
+#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
|
|
|
+#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
|
|
|
+#define RTC_DR_DU_Pos (0U)
|
|
|
+#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
|
|
|
+#define RTC_DR_DU RTC_DR_DU_Msk
|
|
|
+#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
|
|
|
+#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
|
|
|
+#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
|
|
|
+#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
|
|
|
+
|
|
|
+/******************** Bits definition for RTC_SSR register ******************/
|
|
|
+#define RTC_SSR_SS_Pos (0U)
|
|
|
+#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
|
|
|
+#define RTC_SSR_SS RTC_SSR_SS_Msk
|
|
|
+
|
|
|
+/******************** Bits definition for RTC_ICSR register ******************/
|
|
|
+#define RTC_ICSR_RECALPF_Pos (16U)
|
|
|
+#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */
|
|
|
+#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk
|
|
|
+#define RTC_ICSR_INIT_Pos (7U)
|
|
|
+#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */
|
|
|
+#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk
|
|
|
+#define RTC_ICSR_INITF_Pos (6U)
|
|
|
+#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */
|
|
|
+#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk
|
|
|
+#define RTC_ICSR_RSF_Pos (5U)
|
|
|
+#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */
|
|
|
+#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk
|
|
|
+#define RTC_ICSR_INITS_Pos (4U)
|
|
|
+#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */
|
|
|
+#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk
|
|
|
+#define RTC_ICSR_SHPF_Pos (3U)
|
|
|
+#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */
|
|
|
+#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk
|
|
|
+#define RTC_ICSR_WUTWF_Pos (2U)
|
|
|
+#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */
|
|
|
+#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk /*!< Wakeup timer write flag > */
|
|
|
+#define RTC_ICSR_ALRBWF_Pos (1U)
|
|
|
+#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */
|
|
|
+#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk
|
|
|
+#define RTC_ICSR_ALRAWF_Pos (0U)
|
|
|
+#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */
|
|
|
+#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk
|
|
|
+
|
|
|
+/******************** Bits definition for RTC_PRER register *****************/
|
|
|
+#define RTC_PRER_PREDIV_A_Pos (16U)
|
|
|
+#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
|
|
|
+#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
|
|
|
+#define RTC_PRER_PREDIV_S_Pos (0U)
|
|
|
+#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
|
|
|
+#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
|
|
|
+
|
|
|
+/******************** Bits definition for RTC_WUTR register *****************/
|
|
|
+#define RTC_WUTR_WUT_Pos (0U)
|
|
|
+#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
|
|
|
+#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk /*!< Wakeup auto-reload value bits > */
|
|
|
+
|
|
|
+/******************** Bits definition for RTC_CR register *******************/
|
|
|
+#define RTC_CR_OUT2EN_Pos (31U)
|
|
|
+#define RTC_CR_OUT2EN_Msk (0x1UL << RTC_CR_OUT2EN_Pos) /*!< 0x80000000 */
|
|
|
+#define RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk /*!< RTC_OUT2 output enable */
|
|
|
+#define RTC_CR_TAMPALRM_TYPE_Pos (30U)
|
|
|
+#define RTC_CR_TAMPALRM_TYPE_Msk (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos) /*!< 0x40000000 */
|
|
|
+#define RTC_CR_TAMPALRM_TYPE RTC_CR_TAMPALRM_TYPE_Msk /*!< TAMPALARM output type */
|
|
|
+#define RTC_CR_TAMPALRM_PU_Pos (29U)
|
|
|
+#define RTC_CR_TAMPALRM_PU_Msk (0x1UL << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */
|
|
|
+#define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk /*!< TAMPALARM output pull-up config */
|
|
|
+#define RTC_CR_TAMPOE_Pos (26U)
|
|
|
+#define RTC_CR_TAMPOE_Msk (0x1UL << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */
|
|
|
+#define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk /*!< Tamper detection output enable on TAMPALARM */
|
|
|
+#define RTC_CR_TAMPTS_Pos (25U)
|
|
|
+#define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */
|
|
|
+#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*!< Activate timestamp on tamper detection event */
|
|
|
+#define RTC_CR_ITSE_Pos (24U)
|
|
|
+#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */
|
|
|
+#define RTC_CR_ITSE RTC_CR_ITSE_Msk /*!< Timestamp on internal event enable */
|
|
|
+#define RTC_CR_COE_Pos (23U)
|
|
|
+#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
|
|
|
+#define RTC_CR_COE RTC_CR_COE_Msk
|
|
|
+#define RTC_CR_OSEL_Pos (21U)
|
|
|
+#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
|
|
|
+#define RTC_CR_OSEL RTC_CR_OSEL_Msk
|
|
|
+#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
|
|
|
+#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
|
|
|
+#define RTC_CR_POL_Pos (20U)
|
|
|
+#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
|
|
|
+#define RTC_CR_POL RTC_CR_POL_Msk
|
|
|
+#define RTC_CR_COSEL_Pos (19U)
|
|
|
+#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
|
|
|
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk
|
|
|
+#define RTC_CR_BKP_Pos (18U)
|
|
|
+#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
|
|
|
+#define RTC_CR_BKP RTC_CR_BKP_Msk
|
|
|
+#define RTC_CR_SUB1H_Pos (17U)
|
|
|
+#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
|
|
|
+#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
|
|
|
+#define RTC_CR_ADD1H_Pos (16U)
|
|
|
+#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
|
|
|
+#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
|
|
|
+#define RTC_CR_TSIE_Pos (15U)
|
|
|
+#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
|
|
|
+#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< Timestamp interrupt enable > */
|
|
|
+#define RTC_CR_WUTIE_Pos (14U)
|
|
|
+#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
|
|
|
+#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< Wakeup timer interrupt enable > */
|
|
|
+#define RTC_CR_ALRBIE_Pos (13U)
|
|
|
+#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
|
|
|
+#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
|
|
|
+#define RTC_CR_ALRAIE_Pos (12U)
|
|
|
+#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
|
|
|
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
|
|
|
+#define RTC_CR_TSE_Pos (11U)
|
|
|
+#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
|
|
|
+#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< timestamp enable > */
|
|
|
+#define RTC_CR_WUTE_Pos (10U)
|
|
|
+#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
|
|
|
+#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< Wakeup timer enable > */
|
|
|
+#define RTC_CR_ALRBE_Pos (9U)
|
|
|
+#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
|
|
|
+#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
|
|
|
+#define RTC_CR_ALRAE_Pos (8U)
|
|
|
+#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
|
|
|
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
|
|
|
+#define RTC_CR_FMT_Pos (6U)
|
|
|
+#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
|
|
|
+#define RTC_CR_FMT RTC_CR_FMT_Msk
|
|
|
+#define RTC_CR_BYPSHAD_Pos (5U)
|
|
|
+#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
|
|
|
+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
|
|
|
+#define RTC_CR_REFCKON_Pos (4U)
|
|
|
+#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
|
|
|
+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
|
|
|
+#define RTC_CR_TSEDGE_Pos (3U)
|
|
|
+#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
|
|
|
+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< Timestamp event active edge > */
|
|
|
+#define RTC_CR_WUCKSEL_Pos (0U)
|
|
|
+#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
|
|
|
+#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< Wakeup clock selection > */
|
|
|
+#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
|
|
|
+#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
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+#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
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+
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+/******************** Bits definition for RTC_WPR register ******************/
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+#define RTC_WPR_KEY_Pos (0U)
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+#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
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+#define RTC_WPR_KEY RTC_WPR_KEY_Msk
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+
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+/******************** Bits definition for RTC_CALR register *****************/
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+#define RTC_CALR_CALP_Pos (15U)
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+#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
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+#define RTC_CALR_CALP RTC_CALR_CALP_Msk
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+#define RTC_CALR_CALW8_Pos (14U)
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+#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
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+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
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+#define RTC_CALR_CALW16_Pos (13U)
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+#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
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+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
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+#define RTC_CALR_CALM_Pos (0U)
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+#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
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+#define RTC_CALR_CALM RTC_CALR_CALM_Msk
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+#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
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+#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
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+#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
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+#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
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+#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
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+#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
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+#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
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+#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
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+#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
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+
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+/******************** Bits definition for RTC_SHIFTR register ***************/
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+#define RTC_SHIFTR_SUBFS_Pos (0U)
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+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
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+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
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+#define RTC_SHIFTR_ADD1S_Pos (31U)
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+#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
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+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
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+
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+/******************** Bits definition for RTC_TSTR register *****************/
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+#define RTC_TSTR_PM_Pos (22U)
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+#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
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+#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< AM-PM notation > */
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+#define RTC_TSTR_HT_Pos (20U)
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+#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
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+#define RTC_TSTR_HT RTC_TSTR_HT_Msk
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+#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
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+#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
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+#define RTC_TSTR_HU_Pos (16U)
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+#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
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+#define RTC_TSTR_HU RTC_TSTR_HU_Msk
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+#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
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+#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
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+#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
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+#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
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+#define RTC_TSTR_MNT_Pos (12U)
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+#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
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+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
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+#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
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+#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
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+#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
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+#define RTC_TSTR_MNU_Pos (8U)
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+#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
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+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
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+#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
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+#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
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+#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
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+#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
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+#define RTC_TSTR_ST_Pos (4U)
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+#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
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+#define RTC_TSTR_ST RTC_TSTR_ST_Msk
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+#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
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+#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
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+#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
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+#define RTC_TSTR_SU_Pos (0U)
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+#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
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+#define RTC_TSTR_SU RTC_TSTR_SU_Msk
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+#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
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+#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
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+#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
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+#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
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+
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+/******************** Bits definition for RTC_TSDR register *****************/
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+#define RTC_TSDR_WDU_Pos (13U)
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+#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
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+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< Week day units > */
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+#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
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+#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
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+#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
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+#define RTC_TSDR_MT_Pos (12U)
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+#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
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+#define RTC_TSDR_MT RTC_TSDR_MT_Msk
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+#define RTC_TSDR_MU_Pos (8U)
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+#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
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+#define RTC_TSDR_MU RTC_TSDR_MU_Msk
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+#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
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+#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
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+#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
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+#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
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+#define RTC_TSDR_DT_Pos (4U)
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+#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
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+#define RTC_TSDR_DT RTC_TSDR_DT_Msk
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+#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
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+#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
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+#define RTC_TSDR_DU_Pos (0U)
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+#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
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+#define RTC_TSDR_DU RTC_TSDR_DU_Msk
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+#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
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+#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
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+#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
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+#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
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+
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+/******************** Bits definition for RTC_TSSSR register ****************/
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+#define RTC_TSSSR_SS_Pos (0U)
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+#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
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+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk /*!< Sub second value > */
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+
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+/******************** Bits definition for RTC_ALRMAR register ***************/
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+#define RTC_ALRMAR_MSK4_Pos (31U)
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+#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
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+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
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+#define RTC_ALRMAR_WDSEL_Pos (30U)
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+#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
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+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
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+#define RTC_ALRMAR_DT_Pos (28U)
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+#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
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+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
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+#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
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+#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
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+#define RTC_ALRMAR_DU_Pos (24U)
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+#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
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+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
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+#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
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+#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
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+#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
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+#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
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+#define RTC_ALRMAR_MSK3_Pos (23U)
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+#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
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+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
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+#define RTC_ALRMAR_PM_Pos (22U)
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+#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
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|
|
+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
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+#define RTC_ALRMAR_HT_Pos (20U)
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+#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
|
|
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+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
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+#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
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+#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
|
|
|
+#define RTC_ALRMAR_HU_Pos (16U)
|
|
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+#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
|
|
|
+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
|
|
|
+#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
|
|
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+#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
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+#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
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+#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
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+#define RTC_ALRMAR_MSK2_Pos (15U)
|
|
|
+#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
|
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|
+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
|
|
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+#define RTC_ALRMAR_MNT_Pos (12U)
|
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+#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
|
|
|
+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
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+#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
|
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+#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
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+#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
|
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|
+#define RTC_ALRMAR_MNU_Pos (8U)
|
|
|
+#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
|
|
|
+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
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+#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
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+#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
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|
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+#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
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+#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
|
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+#define RTC_ALRMAR_MSK1_Pos (7U)
|
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|
+#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
|
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|
+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
|
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+#define RTC_ALRMAR_ST_Pos (4U)
|
|
|
+#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
|
|
|
+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
|
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+#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
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+#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
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+#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
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+#define RTC_ALRMAR_SU_Pos (0U)
|
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|
+#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
|
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|
+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
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+#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
|
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|
+#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
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+#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
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+#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
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+
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|
|
+/******************** Bits definition for RTC_ALRMASSR register *************/
|
|
|
+#define RTC_ALRMASSR_MASKSS_Pos (24U)
|
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|
+#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
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|
|
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
|
|
|
+#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
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|
+#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
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+#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
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|
+#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
|
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+#define RTC_ALRMASSR_SS_Pos (0U)
|
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|
+#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
|
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|
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
|
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+
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|
+/******************** Bits definition for RTC_ALRMBR register ***************/
|
|
|
+#define RTC_ALRMBR_MSK4_Pos (31U)
|
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|
+#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
|
|
|
+#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
|
|
|
+#define RTC_ALRMBR_WDSEL_Pos (30U)
|
|
|
+#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
|
|
|
+#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
|
|
|
+#define RTC_ALRMBR_DT_Pos (28U)
|
|
|
+#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
|
|
|
+#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
|
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|
+#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
|
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|
+#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
|
|
|
+#define RTC_ALRMBR_DU_Pos (24U)
|
|
|
+#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
|
|
|
+#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
|
|
|
+#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
|
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|
+#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
|
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|
+#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
|
|
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+#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
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+#define RTC_ALRMBR_MSK3_Pos (23U)
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+#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
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+#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
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+#define RTC_ALRMBR_PM_Pos (22U)
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+#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
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+#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
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+#define RTC_ALRMBR_HT_Pos (20U)
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+#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
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+#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
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+#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
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+#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
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+#define RTC_ALRMBR_HU_Pos (16U)
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+#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
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+#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
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+#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
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+#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
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+#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
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+#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
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+#define RTC_ALRMBR_MSK2_Pos (15U)
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+#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
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+#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
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+#define RTC_ALRMBR_MNT_Pos (12U)
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+#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
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+#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
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+#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
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+#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
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+#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
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+#define RTC_ALRMBR_MNU_Pos (8U)
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+#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
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+#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
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+#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
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+#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
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+#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
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+#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
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+#define RTC_ALRMBR_MSK1_Pos (7U)
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+#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
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+#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
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+#define RTC_ALRMBR_ST_Pos (4U)
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+#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
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+#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
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+#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
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+#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
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+#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
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+#define RTC_ALRMBR_SU_Pos (0U)
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+#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
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+#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
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+#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
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+#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
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+#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
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+#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
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+
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+/******************** Bits definition for RTC_ALRMASSR register *************/
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+#define RTC_ALRMBSSR_MASKSS_Pos (24U)
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+#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
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+#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
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+#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
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+#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
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+#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
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+#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
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+#define RTC_ALRMBSSR_SS_Pos (0U)
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+#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
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+#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
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+
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+/******************** Bits definition for RTC_SR register *******************/
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+#define RTC_SR_ITSF_Pos (5U)
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+#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */
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+#define RTC_SR_ITSF RTC_SR_ITSF_Msk
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+#define RTC_SR_TSOVF_Pos (4U)
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+#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */
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+#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk /*!< Timestamp overflow flag > */
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+#define RTC_SR_TSF_Pos (3U)
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+#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */
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+#define RTC_SR_TSF RTC_SR_TSF_Msk /*!< Timestamp flag > */
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+#define RTC_SR_WUTF_Pos (2U)
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+#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */
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+#define RTC_SR_WUTF RTC_SR_WUTF_Msk /*!< Wakeup timer flag > */
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+#define RTC_SR_ALRBF_Pos (1U)
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|
+#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */
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+#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk
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|
+#define RTC_SR_ALRAF_Pos (0U)
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+#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */
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+#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk
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+
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+/******************** Bits definition for RTC_MISR register *****************/
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+#define RTC_MISR_ITSMF_Pos (5U)
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+#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */
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+#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk
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+#define RTC_MISR_TSOVMF_Pos (4U)
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+#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */
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+#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk /*!< Timestamp overflow masked flag > */
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+#define RTC_MISR_TSMF_Pos (3U)
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+#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */
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+#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk /*!< Timestamp masked flag > */
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+#define RTC_MISR_WUTMF_Pos (2U)
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+#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */
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+#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk /*!< Wakeup timer masked flag > */
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+#define RTC_MISR_ALRBMF_Pos (1U)
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+#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */
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+#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk
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+#define RTC_MISR_ALRAMF_Pos (0U)
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+#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */
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+#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk
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+
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+/******************** Bits definition for RTC_SCR register ******************/
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+#define RTC_SCR_CITSF_Pos (5U)
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+#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */
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+#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk
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+#define RTC_SCR_CTSOVF_Pos (4U)
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+#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */
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+#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk /*!< Clear timestamp overflow flag > */
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+#define RTC_SCR_CTSF_Pos (3U)
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+#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */
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+#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk /*!< Clear timestamp flag > */
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+#define RTC_SCR_CWUTF_Pos (2U)
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+#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */
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+#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk /*!< Clear wakeup timer flag > */
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+#define RTC_SCR_CALRBF_Pos (1U)
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+#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */
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+#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk
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+#define RTC_SCR_CALRAF_Pos (0U)
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+#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */
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+#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk
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+
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+/******************************************************************************/
|
|
|
+/* */
|
|
|
+/* Tamper and backup register (TAMP) */
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+/* */
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+/******************************************************************************/
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|
|
+/******************** Bits definition for TAMP_CR1 register *****************/
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+#define TAMP_CR1_TAMP1E_Pos (0U)
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+#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */
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|
|
+#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk
|
|
|
+#define TAMP_CR1_TAMP2E_Pos (1U)
|
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|
+#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */
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|
|
+#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk
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|
|
+#define TAMP_CR1_ITAMP3E_Pos (18U)
|
|
|
+#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */
|
|
|
+#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk
|
|
|
+#define TAMP_CR1_ITAMP4E_Pos (19U)
|
|
|
+#define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */
|
|
|
+#define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk
|
|
|
+#define TAMP_CR1_ITAMP5E_Pos (20U)
|
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|
+#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */
|
|
|
+#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk
|
|
|
+#define TAMP_CR1_ITAMP6E_Pos (21U)
|
|
|
+#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */
|
|
|
+#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk
|
|
|
+
|
|
|
+/******************** Bits definition for TAMP_CR2 register *****************/
|
|
|
+#define TAMP_CR2_TAMP1NOERASE_Pos (0U)
|
|
|
+#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */
|
|
|
+#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk
|
|
|
+#define TAMP_CR2_TAMP2NOERASE_Pos (1U)
|
|
|
+#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */
|
|
|
+#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk
|
|
|
+#define TAMP_CR2_TAMP1MSK_Pos (16U)
|
|
|
+#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */
|
|
|
+#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk
|
|
|
+#define TAMP_CR2_TAMP2MSK_Pos (17U)
|
|
|
+#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */
|
|
|
+#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk
|
|
|
+#define TAMP_CR2_TAMP1TRG_Pos (24U)
|
|
|
+#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */
|
|
|
+#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk
|
|
|
+#define TAMP_CR2_TAMP2TRG_Pos (25U)
|
|
|
+#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */
|
|
|
+#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk
|
|
|
+
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|
|
+/******************** Bits definition for TAMP_FLTCR register ***************/
|
|
|
+#define TAMP_FLTCR_TAMPFREQ_0 0x00000001U
|
|
|
+#define TAMP_FLTCR_TAMPFREQ_1 0x00000002U
|
|
|
+#define TAMP_FLTCR_TAMPFREQ_2 0x00000004U
|
|
|
+#define TAMP_FLTCR_TAMPFREQ_Pos (0U)
|
|
|
+#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */
|
|
|
+#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk
|
|
|
+#define TAMP_FLTCR_TAMPFLT_0 0x00000008U
|
|
|
+#define TAMP_FLTCR_TAMPFLT_1 0x00000010U
|
|
|
+#define TAMP_FLTCR_TAMPFLT_Pos (3U)
|
|
|
+#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */
|
|
|
+#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk
|
|
|
+#define TAMP_FLTCR_TAMPPRCH_0 0x00000020U
|
|
|
+#define TAMP_FLTCR_TAMPPRCH_1 0x00000040U
|
|
|
+#define TAMP_FLTCR_TAMPPRCH_Pos (5U)
|
|
|
+#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */
|
|
|
+#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk
|
|
|
+#define TAMP_FLTCR_TAMPPUDIS_Pos (7U)
|
|
|
+#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */
|
|
|
+#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk
|
|
|
+
|
|
|
+/******************** Bits definition for TAMP_IER register *****************/
|
|
|
+#define TAMP_IER_TAMP1IE_Pos (0U)
|
|
|
+#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */
|
|
|
+#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk
|
|
|
+#define TAMP_IER_TAMP2IE_Pos (1U)
|
|
|
+#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */
|
|
|
+#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk
|
|
|
+#define TAMP_IER_ITAMP3IE_Pos (18U)
|
|
|
+#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */
|
|
|
+#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk
|
|
|
+#define TAMP_IER_ITAMP4IE_Pos (19U)
|
|
|
+#define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */
|
|
|
+#define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk
|
|
|
+#define TAMP_IER_ITAMP5IE_Pos (20U)
|
|
|
+#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */
|
|
|
+#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk
|
|
|
+#define TAMP_IER_ITAMP6IE_Pos (21U)
|
|
|
+#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */
|
|
|
+#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk
|
|
|
+
|
|
|
+/******************** Bits definition for TAMP_SR register ******************/
|
|
|
+#define TAMP_SR_TAMP1F_Pos (0U)
|
|
|
+#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */
|
|
|
+#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk
|
|
|
+#define TAMP_SR_TAMP2F_Pos (1U)
|
|
|
+#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */
|
|
|
+#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk
|
|
|
+#define TAMP_SR_ITAMP3F_Pos (18U)
|
|
|
+#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */
|
|
|
+#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk
|
|
|
+#define TAMP_SR_ITAMP4F_Pos (19U)
|
|
|
+#define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */
|
|
|
+#define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk
|
|
|
+#define TAMP_SR_ITAMP5F_Pos (20U)
|
|
|
+#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */
|
|
|
+#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk
|
|
|
+#define TAMP_SR_ITAMP6F_Pos (21U)
|
|
|
+#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */
|
|
|
+#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk
|
|
|
+
|
|
|
+/******************** Bits definition for TAMP_MISR register ****************/
|
|
|
+#define TAMP_MISR_TAMP1MF_Pos (0U)
|
|
|
+#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */
|
|
|
+#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk
|
|
|
+#define TAMP_MISR_TAMP2MF_Pos (1U)
|
|
|
+#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */
|
|
|
+#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk
|
|
|
+#define TAMP_MISR_ITAMP3MF_Pos (18U)
|
|
|
+#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */
|
|
|
+#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk
|
|
|
+#define TAMP_MISR_ITAMP4MF_Pos (19U)
|
|
|
+#define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */
|
|
|
+#define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk
|
|
|
+#define TAMP_MISR_ITAMP5MF_Pos (20U)
|
|
|
+#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */
|
|
|
+#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk
|
|
|
+#define TAMP_MISR_ITAMP6MF_Pos (21U)
|
|
|
+#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */
|
|
|
+#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk
|
|
|
+
|
|
|
+/******************** Bits definition for TAMP_SCR register *****************/
|
|
|
+#define TAMP_SCR_CTAMP1F_Pos (0U)
|
|
|
+#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */
|
|
|
+#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk
|
|
|
+#define TAMP_SCR_CTAMP2F_Pos (1U)
|
|
|
+#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */
|
|
|
+#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk
|
|
|
+#define TAMP_SCR_CITAMP3F_Pos (18U)
|
|
|
+#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */
|
|
|
+#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk
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|
|
+#define TAMP_SCR_CITAMP4F_Pos (19U)
|
|
|
+#define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */
|
|
|
+#define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk
|
|
|
+#define TAMP_SCR_CITAMP5F_Pos (20U)
|
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+#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */
|
|
|
+#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk
|
|
|
+#define TAMP_SCR_CITAMP6F_Pos (21U)
|
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|
+#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */
|
|
|
+#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk
|
|
|
+
|
|
|
+/******************** Bits definition for TAMP_BKP0R register ***************/
|
|
|
+#define TAMP_BKP0R_Pos (0U)
|
|
|
+#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define TAMP_BKP0R TAMP_BKP0R_Msk
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|
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+
|
|
|
+/******************** Bits definition for TAMP_BKP1R register ***************/
|
|
|
+#define TAMP_BKP1R_Pos (0U)
|
|
|
+#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define TAMP_BKP1R TAMP_BKP1R_Msk
|
|
|
+
|
|
|
+/******************** Bits definition for TAMP_BKP2R register ***************/
|
|
|
+#define TAMP_BKP2R_Pos (0U)
|
|
|
+#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define TAMP_BKP2R TAMP_BKP2R_Msk
|
|
|
+
|
|
|
+/******************** Bits definition for TAMP_BKP3R register ***************/
|
|
|
+#define TAMP_BKP3R_Pos (0U)
|
|
|
+#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define TAMP_BKP3R TAMP_BKP3R_Msk
|
|
|
+
|
|
|
+/******************** Bits definition for TAMP_BKP4R register ***************/
|
|
|
+#define TAMP_BKP4R_Pos (0U)
|
|
|
+#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */
|
|
|
+#define TAMP_BKP4R TAMP_BKP4R_Msk
|
|
|
+
|
|
|
+/******************************************************************************/
|
|
|
+/* */
|
|
|
+/* Serial Peripheral Interface (SPI) */
|
|
|
+/* */
|
|
|
+/******************************************************************************/
|
|
|
+/*
|
|
|
+ * @brief Specific device feature definitions (not present on all devices in the STM32G0 series)
|
|
|
+ */
|
|
|
+#define SPI_I2S_SUPPORT /*!< I2S support */
|
|
|
+
|
|
|
+/******************* Bit definition for SPI_CR1 register ********************/
|
|
|
+#define SPI_CR1_CPHA_Pos (0U)
|
|
|
+#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
|
|
|
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
|
|
|
+#define SPI_CR1_CPOL_Pos (1U)
|
|
|
+#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
|
|
|
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
|
|
|
+#define SPI_CR1_MSTR_Pos (2U)
|
|
|
+#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
|
|
|
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
|
|
|
+
|
|
|
+#define SPI_CR1_BR_Pos (3U)
|
|
|
+#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
|
|
|
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
|
|
|
+#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
|
|
|
+#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
|
|
|
+#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
|
|
|
+
|
|
|
+#define SPI_CR1_SPE_Pos (6U)
|
|
|
+#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
|
|
|
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
|
|
|
+#define SPI_CR1_LSBFIRST_Pos (7U)
|
|
|
+#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
|
|
|
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
|
|
|
+#define SPI_CR1_SSI_Pos (8U)
|
|
|
+#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
|
|
|
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
|
|
|
+#define SPI_CR1_SSM_Pos (9U)
|
|
|
+#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
|
|
|
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
|
|
|
+#define SPI_CR1_RXONLY_Pos (10U)
|
|
|
+#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
|
|
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+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
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|
|
+#define SPI_CR1_CRCL_Pos (11U)
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|
|
+#define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */
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|
|
+#define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
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|
|
+#define SPI_CR1_CRCNEXT_Pos (12U)
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|
+#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
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|
|
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
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|
+#define SPI_CR1_CRCEN_Pos (13U)
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|
+#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
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|
|
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
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+#define SPI_CR1_BIDIOE_Pos (14U)
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|
+#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
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|
|
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
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|
|
+#define SPI_CR1_BIDIMODE_Pos (15U)
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|
+#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
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|
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
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|
|
+
|
|
|
+/******************* Bit definition for SPI_CR2 register ********************/
|
|
|
+#define SPI_CR2_RXDMAEN_Pos (0U)
|
|
|
+#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
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|
|
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
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+#define SPI_CR2_TXDMAEN_Pos (1U)
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|
|
+#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
|
|
|
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
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|
|
+#define SPI_CR2_SSOE_Pos (2U)
|
|
|
+#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
|
|
|
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
|
|
|
+#define SPI_CR2_NSSP_Pos (3U)
|
|
|
+#define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */
|
|
|
+#define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */
|
|
|
+#define SPI_CR2_FRF_Pos (4U)
|
|
|
+#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
|
|
|
+#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
|
|
|
+#define SPI_CR2_ERRIE_Pos (5U)
|
|
|
+#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
|
|
|
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
|
|
|
+#define SPI_CR2_RXNEIE_Pos (6U)
|
|
|
+#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
|
|
|
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
|
|
|
+#define SPI_CR2_TXEIE_Pos (7U)
|
|
|
+#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
|
|
|
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
|
|
|
+#define SPI_CR2_DS_Pos (8U)
|
|
|
+#define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
|
|
|
+#define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
|
|
|
+#define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos) /*!< 0x00000100 */
|
|
|
+#define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos) /*!< 0x00000200 */
|
|
|
+#define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos) /*!< 0x00000400 */
|
|
|
+#define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos) /*!< 0x00000800 */
|
|
|
+#define SPI_CR2_FRXTH_Pos (12U)
|
|
|
+#define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
|
|
|
+#define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
|
|
|
+#define SPI_CR2_LDMARX_Pos (13U)
|
|
|
+#define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */
|
|
|
+#define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */
|
|
|
+#define SPI_CR2_LDMATX_Pos (14U)
|
|
|
+#define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */
|
|
|
+#define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */
|
|
|
+
|
|
|
+/******************** Bit definition for SPI_SR register ********************/
|
|
|
+#define SPI_SR_RXNE_Pos (0U)
|
|
|
+#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
|
|
|
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
|
|
|
+#define SPI_SR_TXE_Pos (1U)
|
|
|
+#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */
|
|
|
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
|
|
|
+#define SPI_SR_CHSIDE_Pos (2U)
|
|
|
+#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
|
|
|
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
|
|
|
+#define SPI_SR_UDR_Pos (3U)
|
|
|
+#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */
|
|
|
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
|
|
|
+#define SPI_SR_CRCERR_Pos (4U)
|
|
|
+#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
|
|
|
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
|
|
|
+#define SPI_SR_MODF_Pos (5U)
|
|
|
+#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */
|
|
|
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
|
|
|
+#define SPI_SR_OVR_Pos (6U)
|
|
|
+#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
|
|
|
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
|
|
|
+#define SPI_SR_BSY_Pos (7U)
|
|
|
+#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */
|
|
|
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
|
|
|
+#define SPI_SR_FRE_Pos (8U)
|
|
|
+#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */
|
|
|
+#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
|
|
|
+#define SPI_SR_FRLVL_Pos (9U)
|
|
|
+#define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
|
|
|
+#define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
|
|
|
+#define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
|
|
|
+#define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
|
|
|
+#define SPI_SR_FTLVL_Pos (11U)
|
|
|
+#define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
|
|
|
+#define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
|
|
|
+#define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
|
|
|
+#define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
|
|
|
+
|
|
|
+/******************** Bit definition for SPI_DR register ********************/
|
|
|
+#define SPI_DR_DR_Pos (0U)
|
|
|
+#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
|
|
|
+#define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
|
|
|
+
|
|
|
+/******************* Bit definition for SPI_CRCPR register ******************/
|
|
|
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
|
|
|
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
|
|
|
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
|
|
|
+
|
|
|
+/****************** Bit definition for SPI_RXCRCR register ******************/
|
|
|
+#define SPI_RXCRCR_RXCRC_Pos (0U)
|
|
|
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
|
|
|
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
|
|
|
+
|
|
|
+/****************** Bit definition for SPI_TXCRCR register ******************/
|
|
|
+#define SPI_TXCRCR_TXCRC_Pos (0U)
|
|
|
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
|
|
|
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
|
|
|
+
|
|
|
+/****************** Bit definition for SPI_I2SCFGR register *****************/
|
|
|
+#define SPI_I2SCFGR_CHLEN_Pos (0U)
|
|
|
+#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
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+#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
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+#define SPI_I2SCFGR_DATLEN_Pos (1U)
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+#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
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+#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
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+#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
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+#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
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+#define SPI_I2SCFGR_CKPOL_Pos (3U)
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+#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
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+#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
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+#define SPI_I2SCFGR_I2SSTD_Pos (4U)
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+#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
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+#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
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+#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
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+#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
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+#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
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+#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
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+#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
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+#define SPI_I2SCFGR_I2SCFG_Pos (8U)
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+#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
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+#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
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+#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
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+#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
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+#define SPI_I2SCFGR_I2SE_Pos (10U)
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+#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
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+#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
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+#define SPI_I2SCFGR_I2SMOD_Pos (11U)
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+#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
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+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
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+#define SPI_I2SCFGR_ASTRTEN_Pos (12U)
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+#define SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */
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+#define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */
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+
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+/****************** Bit definition for SPI_I2SPR register *******************/
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+#define SPI_I2SPR_I2SDIV_Pos (0U)
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+#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
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+#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
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+#define SPI_I2SPR_ODD_Pos (8U)
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+#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
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+#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
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+#define SPI_I2SPR_MCKOE_Pos (9U)
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+#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
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+#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
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+
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+/******************************************************************************/
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+/* */
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+/* SYSCFG */
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+/* */
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+/******************************************************************************/
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+#define SYSCFG_CDEN_SUPPORT
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+/***************** Bit definition for SYSCFG_CFGR1 register ****************/
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+#define SYSCFG_CFGR1_MEM_MODE_Pos (0U)
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+#define SYSCFG_CFGR1_MEM_MODE_Msk (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
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+#define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
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+#define SYSCFG_CFGR1_MEM_MODE_0 (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
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+#define SYSCFG_CFGR1_MEM_MODE_1 (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
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+#define SYSCFG_CFGR1_PA11_RMP_Pos (3U)
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+#define SYSCFG_CFGR1_PA11_RMP_Msk (0x1UL << SYSCFG_CFGR1_PA11_RMP_Pos) /*!< 0x00000008 */
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+#define SYSCFG_CFGR1_PA11_RMP SYSCFG_CFGR1_PA11_RMP_Msk /*!< PA11 Remap */
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+#define SYSCFG_CFGR1_PA12_RMP_Pos (4U)
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+#define SYSCFG_CFGR1_PA12_RMP_Msk (0x1UL << SYSCFG_CFGR1_PA12_RMP_Pos) /*!< 0x00000010 */
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+#define SYSCFG_CFGR1_PA12_RMP SYSCFG_CFGR1_PA12_RMP_Msk /*!< PA12 Remap */
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+#define SYSCFG_CFGR1_IR_POL_Pos (5U)
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+#define SYSCFG_CFGR1_IR_POL_Msk (0x1UL << SYSCFG_CFGR1_IR_POL_Pos) /*!< 0x00000020 */
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+#define SYSCFG_CFGR1_IR_POL SYSCFG_CFGR1_IR_POL_Msk /*!< IROut Polarity Selection */
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+#define SYSCFG_CFGR1_IR_MOD_Pos (6U)
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+#define SYSCFG_CFGR1_IR_MOD_Msk (0x3UL << SYSCFG_CFGR1_IR_MOD_Pos) /*!< 0x000000C0 */
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+#define SYSCFG_CFGR1_IR_MOD SYSCFG_CFGR1_IR_MOD_Msk /*!< IRDA Modulation Envelope signal source selection */
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+#define SYSCFG_CFGR1_IR_MOD_0 (0x1UL << SYSCFG_CFGR1_IR_MOD_Pos) /*!< 0x00000040 */
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+#define SYSCFG_CFGR1_IR_MOD_1 (0x2UL << SYSCFG_CFGR1_IR_MOD_Pos) /*!< 0x00000080 */
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+#define SYSCFG_CFGR1_BOOSTEN_Pos (8U)
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+#define SYSCFG_CFGR1_BOOSTEN_Msk (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos) /*!< 0x00000100 */
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+#define SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk /*!< I/O analog switch voltage booster enable */
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+#define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)
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+#define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */
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+#define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
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+#define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)
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+#define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */
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+#define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
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+#define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U)
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+#define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos) /*!< 0x00040000 */
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+#define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
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+#define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U)
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+#define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos) /*!< 0x00080000 */
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+#define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
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+#define SYSCFG_CFGR1_I2C1_FMP_Pos (20U)
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+#define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */
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+#define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 */
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+#define SYSCFG_CFGR1_I2C2_FMP_Pos (21U)
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+#define SYSCFG_CFGR1_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos) /*!< 0x00200000 */
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+#define SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk /*!< Enable I2C2 Fast mode plus */
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+#define SYSCFG_CFGR1_I2C_PA9_FMP_Pos (22U)
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+#define SYSCFG_CFGR1_I2C_PA9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PA9_FMP_Pos) /*!< 0x00400000 */
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+#define SYSCFG_CFGR1_I2C_PA9_FMP SYSCFG_CFGR1_I2C_PA9_FMP_Msk /*!< Enable Fast Mode Plus on PA9 */
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+#define SYSCFG_CFGR1_I2C_PA10_FMP_Pos (23U)
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+#define SYSCFG_CFGR1_I2C_PA10_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PA10_FMP_Pos) /*!< 0x00800000 */
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+#define SYSCFG_CFGR1_I2C_PA10_FMP SYSCFG_CFGR1_I2C_PA10_FMP_Msk /*!< Enable Fast Mode Plus on PA10 */
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+
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+/****************** Bit definition for SYSCFG_CFGR2 register ****************/
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+#define SYSCFG_CFGR2_CLL_Pos (0U)
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+#define SYSCFG_CFGR2_CLL_Msk (0x1UL << SYSCFG_CFGR2_CLL_Pos) /*!< 0x00000001 */
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+#define SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
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+#define SYSCFG_CFGR2_SPL_Pos (1U)
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+#define SYSCFG_CFGR2_SPL_Msk (0x1UL << SYSCFG_CFGR2_SPL_Pos) /*!< 0x00000002 */
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+#define SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
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+#define SYSCFG_CFGR2_ECCL_Pos (3U)
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+#define SYSCFG_CFGR2_ECCL_Msk (0x1UL << SYSCFG_CFGR2_ECCL_Pos) /*!< 0x00000008 */
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+#define SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk /*!< ECCL */
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+#define SYSCFG_CFGR2_SPF_Pos (8U)
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+#define SYSCFG_CFGR2_SPF_Msk (0x1UL << SYSCFG_CFGR2_SPF_Pos) /*!< 0x00000100 */
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+#define SYSCFG_CFGR2_SPF SYSCFG_CFGR2_SPF_Msk /*!< SRAM Parity error flag */
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+#define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SPF /*!< SRAM Parity error flag (define maintained for legacy purpose) */
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+
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+#define SYSCFG_CFGR2_PA1_CDEN_Pos (16U)
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+#define SYSCFG_CFGR2_PA1_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PA1_CDEN_Pos) /* 0x00010000 */
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+#define SYSCFG_CFGR2_PA1_CDEN SYSCFG_CFGR2_PA1_CDEN_Msk /*!< PA[1] Clamping Diode Enable */
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+#define SYSCFG_CFGR2_PA3_CDEN_Pos (17U)
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+#define SYSCFG_CFGR2_PA3_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PA3_CDEN_Pos) /* 0x00020000 */
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+#define SYSCFG_CFGR2_PA3_CDEN SYSCFG_CFGR2_PA3_CDEN_Msk /*!< PA[3] Clamping Diode Enable */
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+#define SYSCFG_CFGR2_PA5_CDEN_Pos (18U)
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+#define SYSCFG_CFGR2_PA5_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PA5_CDEN_Pos) /* 0x00040000 */
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+#define SYSCFG_CFGR2_PA5_CDEN SYSCFG_CFGR2_PA5_CDEN_Msk /*!< PA[5] Clamping Diode Enable */
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+#define SYSCFG_CFGR2_PA6_CDEN_Pos (19U)
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+#define SYSCFG_CFGR2_PA6_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PA6_CDEN_Pos) /* 0x00080000 */
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+#define SYSCFG_CFGR2_PA6_CDEN SYSCFG_CFGR2_PA6_CDEN_Msk /*!< PA[6] Clamping Diode Enable */
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+#define SYSCFG_CFGR2_PA13_CDEN_Pos (20U)
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+#define SYSCFG_CFGR2_PA13_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PA13_CDEN_Pos) /* 0x00100000 */
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+#define SYSCFG_CFGR2_PA13_CDEN SYSCFG_CFGR2_PA13_CDEN_Msk /*!< PA[13] Clamping Diode Enable */
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+#define SYSCFG_CFGR2_PB0_CDEN_Pos (21U)
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+#define SYSCFG_CFGR2_PB0_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PB0_CDEN_Pos) /* 0x00200000 */
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+#define SYSCFG_CFGR2_PB0_CDEN SYSCFG_CFGR2_PB0_CDEN_Msk /*!< PB[0] Clamping Diode Enable */
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+#define SYSCFG_CFGR2_PB1_CDEN_Pos (22U)
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+#define SYSCFG_CFGR2_PB1_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PB1_CDEN_Pos) /* 0x00400000 */
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+#define SYSCFG_CFGR2_PB1_CDEN SYSCFG_CFGR2_PB1_CDEN_Msk /*!< PB[1] Clamping Diode Enable */
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+#define SYSCFG_CFGR2_PB2_CDEN_Pos (23U)
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+#define SYSCFG_CFGR2_PB2_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PB2_CDEN_Pos) /* 0x00800000 */
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+#define SYSCFG_CFGR2_PB2_CDEN SYSCFG_CFGR2_PB2_CDEN_Msk /*!< PB[2] Clamping Diode Enable */
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+/***************** Bit definition for SYSCFG_ITLINEx ISR Wrapper register ****************/
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+#define SYSCFG_ITLINE0_SR_EWDG_Pos (0U)
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+#define SYSCFG_ITLINE0_SR_EWDG_Msk (0x1UL << SYSCFG_ITLINE0_SR_EWDG_Pos) /*!< 0x00000001 */
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+#define SYSCFG_ITLINE0_SR_EWDG SYSCFG_ITLINE0_SR_EWDG_Msk /*!< EWDG interrupt */
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+#define SYSCFG_ITLINE2_SR_TAMPER_Pos (0U)
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+#define SYSCFG_ITLINE2_SR_TAMPER_Msk (0x1UL << SYSCFG_ITLINE2_SR_TAMPER_Pos) /*!< 0x00000001 */
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+#define SYSCFG_ITLINE2_SR_TAMPER SYSCFG_ITLINE2_SR_TAMPER_Msk /*!< TAMPER -> exti[21] interrupt */
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+#define SYSCFG_ITLINE2_SR_RTC_Pos (1U)
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+#define SYSCFG_ITLINE2_SR_RTC_Msk (0x1UL << SYSCFG_ITLINE2_SR_RTC_Pos) /*!< 0x00000002 */
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+#define SYSCFG_ITLINE2_SR_RTC SYSCFG_ITLINE2_SR_RTC_Msk /*!< RTC -> exti[19] interrupt .... */
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+#define SYSCFG_ITLINE3_SR_FLASH_ECC_Pos (0U)
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+#define SYSCFG_ITLINE3_SR_FLASH_ECC_Msk (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ECC_Pos) /*!< 0x00000001 */
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+#define SYSCFG_ITLINE3_SR_FLASH_ECC SYSCFG_ITLINE3_SR_FLASH_ECC_Msk /*!< Flash ITF ECC interrupt */
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+#define SYSCFG_ITLINE3_SR_FLASH_ITF_Pos (1U)
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+#define SYSCFG_ITLINE3_SR_FLASH_ITF_Msk (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ITF_Pos) /*!< 0x00000002 */
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+#define SYSCFG_ITLINE3_SR_FLASH_ITF SYSCFG_ITLINE3_SR_FLASH_ITF_Msk /*!< FLASH ITF interrupt */
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+#define SYSCFG_ITLINE4_SR_CLK_CTRL_Pos (0U)
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+#define SYSCFG_ITLINE4_SR_CLK_CTRL_Msk (0x1UL << SYSCFG_ITLINE4_SR_CLK_CTRL_Pos) /*!< 0x00000001 */
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+#define SYSCFG_ITLINE4_SR_CLK_CTRL SYSCFG_ITLINE4_SR_CLK_CTRL_Msk /*!< RCC interrupt */
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+#define SYSCFG_ITLINE5_SR_EXTI0_Pos (0U)
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+#define SYSCFG_ITLINE5_SR_EXTI0_Msk (0x1UL << SYSCFG_ITLINE5_SR_EXTI0_Pos) /*!< 0x00000001 */
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+#define SYSCFG_ITLINE5_SR_EXTI0 SYSCFG_ITLINE5_SR_EXTI0_Msk /*!< External Interrupt 0 */
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+#define SYSCFG_ITLINE5_SR_EXTI1_Pos (1U)
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+#define SYSCFG_ITLINE5_SR_EXTI1_Msk (0x1UL << SYSCFG_ITLINE5_SR_EXTI1_Pos) /*!< 0x00000002 */
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+#define SYSCFG_ITLINE5_SR_EXTI1 SYSCFG_ITLINE5_SR_EXTI1_Msk /*!< External Interrupt 1 */
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+#define SYSCFG_ITLINE6_SR_EXTI2_Pos (0U)
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+#define SYSCFG_ITLINE6_SR_EXTI2_Msk (0x1UL << SYSCFG_ITLINE6_SR_EXTI2_Pos) /*!< 0x00000001 */
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+#define SYSCFG_ITLINE6_SR_EXTI2 SYSCFG_ITLINE6_SR_EXTI2_Msk /*!< External Interrupt 2 */
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+#define SYSCFG_ITLINE6_SR_EXTI3_Pos (1U)
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+#define SYSCFG_ITLINE6_SR_EXTI3_Msk (0x1UL << SYSCFG_ITLINE6_SR_EXTI3_Pos) /*!< 0x00000002 */
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+#define SYSCFG_ITLINE6_SR_EXTI3 SYSCFG_ITLINE6_SR_EXTI3_Msk /*!< External Interrupt 3 */
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+#define SYSCFG_ITLINE7_SR_EXTI4_Pos (0U)
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+#define SYSCFG_ITLINE7_SR_EXTI4_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI4_Pos) /*!< 0x00000001 */
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+#define SYSCFG_ITLINE7_SR_EXTI4 SYSCFG_ITLINE7_SR_EXTI4_Msk /*!< External Interrupt 4 */
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+#define SYSCFG_ITLINE7_SR_EXTI5_Pos (1U)
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+#define SYSCFG_ITLINE7_SR_EXTI5_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI5_Pos) /*!< 0x00000002 */
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+#define SYSCFG_ITLINE7_SR_EXTI5 SYSCFG_ITLINE7_SR_EXTI5_Msk /*!< External Interrupt 5 */
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+#define SYSCFG_ITLINE7_SR_EXTI6_Pos (2U)
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+#define SYSCFG_ITLINE7_SR_EXTI6_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI6_Pos) /*!< 0x00000004 */
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+#define SYSCFG_ITLINE7_SR_EXTI6 SYSCFG_ITLINE7_SR_EXTI6_Msk /*!< External Interrupt 6 */
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+#define SYSCFG_ITLINE7_SR_EXTI7_Pos (3U)
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+#define SYSCFG_ITLINE7_SR_EXTI7_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI7_Pos) /*!< 0x00000008 */
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+#define SYSCFG_ITLINE7_SR_EXTI7 SYSCFG_ITLINE7_SR_EXTI7_Msk /*!< External Interrupt 7 */
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+#define SYSCFG_ITLINE7_SR_EXTI8_Pos (4U)
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+#define SYSCFG_ITLINE7_SR_EXTI8_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI8_Pos) /*!< 0x00000010 */
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+#define SYSCFG_ITLINE7_SR_EXTI8 SYSCFG_ITLINE7_SR_EXTI8_Msk /*!< External Interrupt 8 */
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+#define SYSCFG_ITLINE7_SR_EXTI9_Pos (5U)
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+#define SYSCFG_ITLINE7_SR_EXTI9_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI9_Pos) /*!< 0x00000020 */
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+#define SYSCFG_ITLINE7_SR_EXTI9 SYSCFG_ITLINE7_SR_EXTI9_Msk /*!< External Interrupt 9 */
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+#define SYSCFG_ITLINE7_SR_EXTI10_Pos (6U)
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+#define SYSCFG_ITLINE7_SR_EXTI10_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI10_Pos) /*!< 0x00000040 */
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+#define SYSCFG_ITLINE7_SR_EXTI10 SYSCFG_ITLINE7_SR_EXTI10_Msk /*!< External Interrupt 10 */
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+#define SYSCFG_ITLINE7_SR_EXTI11_Pos (7U)
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+#define SYSCFG_ITLINE7_SR_EXTI11_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI11_Pos) /*!< 0x00000080 */
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+#define SYSCFG_ITLINE7_SR_EXTI11 SYSCFG_ITLINE7_SR_EXTI11_Msk /*!< External Interrupt 11 */
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+#define SYSCFG_ITLINE7_SR_EXTI12_Pos (8U)
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+#define SYSCFG_ITLINE7_SR_EXTI12_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI12_Pos) /*!< 0x00000100 */
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+#define SYSCFG_ITLINE7_SR_EXTI12 SYSCFG_ITLINE7_SR_EXTI12_Msk /*!< External Interrupt 12 */
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+#define SYSCFG_ITLINE7_SR_EXTI13_Pos (9U)
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+#define SYSCFG_ITLINE7_SR_EXTI13_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI13_Pos) /*!< 0x00000200 */
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+#define SYSCFG_ITLINE7_SR_EXTI13 SYSCFG_ITLINE7_SR_EXTI13_Msk /*!< External Interrupt 13 */
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+#define SYSCFG_ITLINE7_SR_EXTI14_Pos (10U)
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+#define SYSCFG_ITLINE7_SR_EXTI14_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI14_Pos) /*!< 0x00000400 */
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+#define SYSCFG_ITLINE7_SR_EXTI14 SYSCFG_ITLINE7_SR_EXTI14_Msk /*!< External Interrupt 14 */
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+#define SYSCFG_ITLINE7_SR_EXTI15_Pos (11U)
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+#define SYSCFG_ITLINE7_SR_EXTI15_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI15_Pos) /*!< 0x00000800 */
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+#define SYSCFG_ITLINE7_SR_EXTI15 SYSCFG_ITLINE7_SR_EXTI15_Msk /*!< External Interrupt 15 */
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+#define SYSCFG_ITLINE9_SR_DMA1_CH1_Pos (0U)
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+#define SYSCFG_ITLINE9_SR_DMA1_CH1_Msk (0x1UL << SYSCFG_ITLINE9_SR_DMA1_CH1_Pos) /*!< 0x00000001 */
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+#define SYSCFG_ITLINE9_SR_DMA1_CH1 SYSCFG_ITLINE9_SR_DMA1_CH1_Msk /*!< DMA1 Channel 1 Interrupt */
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+#define SYSCFG_ITLINE10_SR_DMA1_CH2_Pos (0U)
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+#define SYSCFG_ITLINE10_SR_DMA1_CH2_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH2_Pos) /*!< 0x00000001 */
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+#define SYSCFG_ITLINE10_SR_DMA1_CH2 SYSCFG_ITLINE10_SR_DMA1_CH2_Msk /*!< DMA1 Channel 2 Interrupt */
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+#define SYSCFG_ITLINE10_SR_DMA1_CH3_Pos (1U)
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+#define SYSCFG_ITLINE10_SR_DMA1_CH3_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH3_Pos) /*!< 0x00000002 */
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+#define SYSCFG_ITLINE10_SR_DMA1_CH3 SYSCFG_ITLINE10_SR_DMA1_CH3_Msk /*!< DMA2 Channel 3 Interrupt */
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+#define SYSCFG_ITLINE11_SR_DMAMUX1_Pos (0U)
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+#define SYSCFG_ITLINE11_SR_DMAMUX1_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMAMUX1_Pos) /*!< 0x00000001 */
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+#define SYSCFG_ITLINE11_SR_DMAMUX1 SYSCFG_ITLINE11_SR_DMAMUX1_Msk /*!< DMAMUX Interrupt */
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+#define SYSCFG_ITLINE11_SR_DMA1_CH4_Pos (1U)
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+#define SYSCFG_ITLINE11_SR_DMA1_CH4_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH4_Pos) /*!< 0x00000002 */
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+#define SYSCFG_ITLINE11_SR_DMA1_CH4 SYSCFG_ITLINE11_SR_DMA1_CH4_Msk /*!< DMA1 Channel 4 Interrupt */
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+#define SYSCFG_ITLINE11_SR_DMA1_CH5_Pos (2U)
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+#define SYSCFG_ITLINE11_SR_DMA1_CH5_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH5_Pos) /*!< 0x00000004 */
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+#define SYSCFG_ITLINE11_SR_DMA1_CH5 SYSCFG_ITLINE11_SR_DMA1_CH5_Msk /*!< DMA1 Channel 5 Interrupt */
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+#define SYSCFG_ITLINE12_SR_ADC_Pos (0U)
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+#define SYSCFG_ITLINE12_SR_ADC_Msk (0x1UL << SYSCFG_ITLINE12_SR_ADC_Pos) /*!< 0x00000001 */
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+#define SYSCFG_ITLINE12_SR_ADC SYSCFG_ITLINE12_SR_ADC_Msk /*!< ADC Interrupt */
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+#define SYSCFG_ITLINE13_SR_TIM1_CCU_Pos (0U)
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+#define SYSCFG_ITLINE13_SR_TIM1_CCU_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_CCU_Pos) /*!< 0x00000001 */
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+#define SYSCFG_ITLINE13_SR_TIM1_CCU SYSCFG_ITLINE13_SR_TIM1_CCU_Msk /*!< TIM1 CCU Interrupt */
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+#define SYSCFG_ITLINE13_SR_TIM1_TRG_Pos (1U)
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+#define SYSCFG_ITLINE13_SR_TIM1_TRG_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_TRG_Pos) /*!< 0x00000002 */
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+#define SYSCFG_ITLINE13_SR_TIM1_TRG SYSCFG_ITLINE13_SR_TIM1_TRG_Msk /*!< TIM1 TRG Interrupt */
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+#define SYSCFG_ITLINE13_SR_TIM1_UPD_Pos (2U)
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+#define SYSCFG_ITLINE13_SR_TIM1_UPD_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_UPD_Pos) /*!< 0x00000004 */
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+#define SYSCFG_ITLINE13_SR_TIM1_UPD SYSCFG_ITLINE13_SR_TIM1_UPD_Msk /*!< TIM1 UPD Interrupt */
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+#define SYSCFG_ITLINE13_SR_TIM1_BRK_Pos (3U)
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+#define SYSCFG_ITLINE13_SR_TIM1_BRK_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_BRK_Pos) /*!< 0x00000008 */
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+#define SYSCFG_ITLINE13_SR_TIM1_BRK SYSCFG_ITLINE13_SR_TIM1_BRK_Msk /*!< TIM1 BRK Interrupt */
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+#define SYSCFG_ITLINE14_SR_TIM1_CC_Pos (0U)
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+#define SYSCFG_ITLINE14_SR_TIM1_CC_Msk (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC_Pos) /*!< 0x00000001 */
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+#define SYSCFG_ITLINE14_SR_TIM1_CC SYSCFG_ITLINE14_SR_TIM1_CC_Msk /*!< TIM1 CC Interrupt */
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+#define SYSCFG_ITLINE16_SR_TIM3_GLB_Pos (0U)
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+#define SYSCFG_ITLINE16_SR_TIM3_GLB_Msk (0x1UL << SYSCFG_ITLINE16_SR_TIM3_GLB_Pos) /*!< 0x00000001 */
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+#define SYSCFG_ITLINE16_SR_TIM3_GLB SYSCFG_ITLINE16_SR_TIM3_GLB_Msk /*!< TIM3 GLB Interrupt */
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+#define SYSCFG_ITLINE19_SR_TIM14_GLB_Pos (0U)
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+#define SYSCFG_ITLINE19_SR_TIM14_GLB_Msk (0x1UL << SYSCFG_ITLINE19_SR_TIM14_GLB_Pos) /*!< 0x00000001 */
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+#define SYSCFG_ITLINE19_SR_TIM14_GLB SYSCFG_ITLINE19_SR_TIM14_GLB_Msk /*!< TIM14 GLB Interrupt */
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+#define SYSCFG_ITLINE21_SR_TIM16_GLB_Pos (0U)
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+#define SYSCFG_ITLINE21_SR_TIM16_GLB_Msk (0x1UL << SYSCFG_ITLINE21_SR_TIM16_GLB_Pos) /*!< 0x00000001 */
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+#define SYSCFG_ITLINE21_SR_TIM16_GLB SYSCFG_ITLINE21_SR_TIM16_GLB_Msk /*!< TIM16 GLB Interrupt */
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+#define SYSCFG_ITLINE22_SR_TIM17_GLB_Pos (0U)
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+#define SYSCFG_ITLINE22_SR_TIM17_GLB_Msk (0x1UL << SYSCFG_ITLINE22_SR_TIM17_GLB_Pos) /*!< 0x00000001 */
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+#define SYSCFG_ITLINE22_SR_TIM17_GLB SYSCFG_ITLINE22_SR_TIM17_GLB_Msk /*!< TIM17 GLB Interrupt */
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+#define SYSCFG_ITLINE23_SR_I2C1_GLB_Pos (0U)
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+#define SYSCFG_ITLINE23_SR_I2C1_GLB_Msk (0x1UL << SYSCFG_ITLINE23_SR_I2C1_GLB_Pos) /*!< 0x00000001 */
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+#define SYSCFG_ITLINE23_SR_I2C1_GLB SYSCFG_ITLINE23_SR_I2C1_GLB_Msk /*!< I2C1 GLB Interrupt -> exti[23] */
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+#define SYSCFG_ITLINE24_SR_I2C2_GLB_Pos (0U)
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+#define SYSCFG_ITLINE24_SR_I2C2_GLB_Msk (0x1UL << SYSCFG_ITLINE24_SR_I2C2_GLB_Pos) /*!< 0x00000001 */
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+#define SYSCFG_ITLINE24_SR_I2C2_GLB SYSCFG_ITLINE24_SR_I2C2_GLB_Msk /*!< I2C2 GLB Interrupt -> exti[22]*/
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+#define SYSCFG_ITLINE25_SR_SPI1_Pos (0U)
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+#define SYSCFG_ITLINE25_SR_SPI1_Msk (0x1UL << SYSCFG_ITLINE25_SR_SPI1_Pos) /*!< 0x00000001 */
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+#define SYSCFG_ITLINE25_SR_SPI1 SYSCFG_ITLINE25_SR_SPI1_Msk /*!< SPI1 Interrupt */
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+#define SYSCFG_ITLINE26_SR_SPI2_Pos (0U)
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+#define SYSCFG_ITLINE26_SR_SPI2_Msk (0x1UL << SYSCFG_ITLINE26_SR_SPI2_Pos) /*!< 0x00000001 */
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+#define SYSCFG_ITLINE26_SR_SPI2 SYSCFG_ITLINE26_SR_SPI2_Msk /*!< SPI2 Interrupt */
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+#define SYSCFG_ITLINE27_SR_USART1_GLB_Pos (0U)
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+#define SYSCFG_ITLINE27_SR_USART1_GLB_Msk (0x1UL << SYSCFG_ITLINE27_SR_USART1_GLB_Pos) /*!< 0x00000001 */
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+#define SYSCFG_ITLINE27_SR_USART1_GLB SYSCFG_ITLINE27_SR_USART1_GLB_Msk /*!< USART1 GLB Interrupt -> exti[25] */
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+#define SYSCFG_ITLINE28_SR_USART2_GLB_Pos (0U)
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+#define SYSCFG_ITLINE28_SR_USART2_GLB_Msk (0x1UL << SYSCFG_ITLINE28_SR_USART2_GLB_Pos) /*!< 0x00000001 */
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+#define SYSCFG_ITLINE28_SR_USART2_GLB SYSCFG_ITLINE28_SR_USART2_GLB_Msk /*!< USART2 GLB Interrupt -> exti[26] */
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+
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+/******************************************************************************/
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+/* */
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+/* TIM */
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+/* */
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+/******************************************************************************/
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+/******************* Bit definition for TIM_CR1 register ********************/
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+#define TIM_CR1_CEN_Pos (0U)
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+#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
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+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
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+#define TIM_CR1_UDIS_Pos (1U)
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+#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
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+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
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+#define TIM_CR1_URS_Pos (2U)
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+#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
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+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
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+#define TIM_CR1_OPM_Pos (3U)
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+#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
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+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
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+#define TIM_CR1_DIR_Pos (4U)
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+#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
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+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
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+
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+#define TIM_CR1_CMS_Pos (5U)
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+#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
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+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
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+#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
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+#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
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+
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+#define TIM_CR1_ARPE_Pos (7U)
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+#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
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+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
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+
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+#define TIM_CR1_CKD_Pos (8U)
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+#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
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+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
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+#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
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+#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
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+
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+#define TIM_CR1_UIFREMAP_Pos (11U)
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+#define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
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+#define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */
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+
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+/******************* Bit definition for TIM_CR2 register ********************/
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+#define TIM_CR2_CCPC_Pos (0U)
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+#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
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+#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
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+#define TIM_CR2_CCUS_Pos (2U)
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+#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
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+#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
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+#define TIM_CR2_CCDS_Pos (3U)
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+#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
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+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
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+
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+#define TIM_CR2_MMS_Pos (4U)
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+#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
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+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
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+#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
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+#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
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+#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
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+
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+#define TIM_CR2_TI1S_Pos (7U)
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+#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
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+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
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+#define TIM_CR2_OIS1_Pos (8U)
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+#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
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+#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
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+#define TIM_CR2_OIS1N_Pos (9U)
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+#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
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+#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
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+#define TIM_CR2_OIS2_Pos (10U)
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+#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
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+#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
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+#define TIM_CR2_OIS2N_Pos (11U)
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+#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
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+#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
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+#define TIM_CR2_OIS3_Pos (12U)
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+#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
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+#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
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+#define TIM_CR2_OIS3N_Pos (13U)
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+#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
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+#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
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+#define TIM_CR2_OIS4_Pos (14U)
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+#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
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+#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
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+#define TIM_CR2_OIS5_Pos (16U)
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+#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
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+#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 5 (OC5 output) */
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+#define TIM_CR2_OIS6_Pos (18U)
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+#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
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+#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 6 (OC6 output) */
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+
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+#define TIM_CR2_MMS2_Pos (20U)
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+#define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
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+#define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
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+#define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
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+#define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
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+#define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
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+#define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
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+
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+/******************* Bit definition for TIM_SMCR register *******************/
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+#define TIM_SMCR_SMS_Pos (0U)
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+#define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
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+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
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+#define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
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+#define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
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+#define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
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+#define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */
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+
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+#define TIM_SMCR_OCCS_Pos (3U)
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+#define TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
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+#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
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+
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+#define TIM_SMCR_TS_Pos (4U)
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+#define TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos) /*!< 0x00300070 */
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+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
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+#define TIM_SMCR_TS_0 (0x00001UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
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+#define TIM_SMCR_TS_1 (0x00002UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
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+#define TIM_SMCR_TS_2 (0x00004UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
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+#define TIM_SMCR_TS_3 (0x10000UL << TIM_SMCR_TS_Pos) /*!< 0x00100000 */
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+#define TIM_SMCR_TS_4 (0x20000UL << TIM_SMCR_TS_Pos) /*!< 0x00200000 */
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+
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+#define TIM_SMCR_MSM_Pos (7U)
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+#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
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+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
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+
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+#define TIM_SMCR_ETF_Pos (8U)
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+#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
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+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
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+#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
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+#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
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+#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
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+#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
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+
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+#define TIM_SMCR_ETPS_Pos (12U)
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+#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
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+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
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+#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
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+#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
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+
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+#define TIM_SMCR_ECE_Pos (14U)
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+#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
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+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
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+#define TIM_SMCR_ETP_Pos (15U)
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+#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
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+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
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+
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+/******************* Bit definition for TIM_DIER register *******************/
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+#define TIM_DIER_UIE_Pos (0U)
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+#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
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+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
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+#define TIM_DIER_CC1IE_Pos (1U)
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+#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
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+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
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+#define TIM_DIER_CC2IE_Pos (2U)
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+#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
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+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
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+#define TIM_DIER_CC3IE_Pos (3U)
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+#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
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+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
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+#define TIM_DIER_CC4IE_Pos (4U)
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+#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
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+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
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+#define TIM_DIER_COMIE_Pos (5U)
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+#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
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+#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
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+#define TIM_DIER_TIE_Pos (6U)
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+#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
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+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
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+#define TIM_DIER_BIE_Pos (7U)
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+#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
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+#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
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+#define TIM_DIER_UDE_Pos (8U)
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+#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
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+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
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+#define TIM_DIER_CC1DE_Pos (9U)
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+#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
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+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
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+#define TIM_DIER_CC2DE_Pos (10U)
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+#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
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+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
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+#define TIM_DIER_CC3DE_Pos (11U)
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+#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
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+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
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+#define TIM_DIER_CC4DE_Pos (12U)
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+#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
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+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
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+#define TIM_DIER_COMDE_Pos (13U)
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+#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
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+#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
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+#define TIM_DIER_TDE_Pos (14U)
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+#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
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+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
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+
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|
+/******************** Bit definition for TIM_SR register ********************/
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+#define TIM_SR_UIF_Pos (0U)
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+#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
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+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
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+#define TIM_SR_CC1IF_Pos (1U)
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+#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
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+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
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+#define TIM_SR_CC2IF_Pos (2U)
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+#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
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+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
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+#define TIM_SR_CC3IF_Pos (3U)
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+#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
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+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
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+#define TIM_SR_CC4IF_Pos (4U)
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+#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
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+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
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+#define TIM_SR_COMIF_Pos (5U)
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+#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
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+#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
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+#define TIM_SR_TIF_Pos (6U)
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+#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
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+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
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+#define TIM_SR_BIF_Pos (7U)
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+#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */
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+#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
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+#define TIM_SR_B2IF_Pos (8U)
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+#define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
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+#define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break 2 interrupt Flag */
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+#define TIM_SR_CC1OF_Pos (9U)
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+#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
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+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
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+#define TIM_SR_CC2OF_Pos (10U)
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+#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
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+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
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+#define TIM_SR_CC3OF_Pos (11U)
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+#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
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+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
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+#define TIM_SR_CC4OF_Pos (12U)
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+#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
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+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
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+#define TIM_SR_SBIF_Pos (13U)
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+#define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos) /*!< 0x00002000 */
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+#define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!<System Break interrupt Flag */
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+#define TIM_SR_CC5IF_Pos (16U)
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+#define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
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+#define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
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+#define TIM_SR_CC6IF_Pos (17U)
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+#define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
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+#define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
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+
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+
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|
+/******************* Bit definition for TIM_EGR register ********************/
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+#define TIM_EGR_UG_Pos (0U)
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+#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
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+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
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+#define TIM_EGR_CC1G_Pos (1U)
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+#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
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+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
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+#define TIM_EGR_CC2G_Pos (2U)
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+#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
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+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
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+#define TIM_EGR_CC3G_Pos (3U)
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+#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
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+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
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+#define TIM_EGR_CC4G_Pos (4U)
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+#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
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+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
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+#define TIM_EGR_COMG_Pos (5U)
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+#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
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+#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
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+#define TIM_EGR_TG_Pos (6U)
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+#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
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+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
|
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+#define TIM_EGR_BG_Pos (7U)
|
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+#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */
|
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+#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
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+#define TIM_EGR_B2G_Pos (8U)
|
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+#define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos) /*!< 0x00000100 */
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|
+#define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break 2 Generation */
|
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|
+
|
|
|
+
|
|
|
+/****************** Bit definition for TIM_CCMR1 register *******************/
|
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|
+#define TIM_CCMR1_CC1S_Pos (0U)
|
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|
+#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
|
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+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
|
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|
+#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
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+#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
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|
+
|
|
|
+#define TIM_CCMR1_OC1FE_Pos (2U)
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+#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
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|
|
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
|
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|
+#define TIM_CCMR1_OC1PE_Pos (3U)
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|
+#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
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|
|
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
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+
|
|
|
+#define TIM_CCMR1_OC1M_Pos (4U)
|
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|
+#define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
|
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|
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
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|
+#define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
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|
+#define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
|
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|
+#define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
|
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|
+#define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */
|
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|
+
|
|
|
+#define TIM_CCMR1_OC1CE_Pos (7U)
|
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|
+#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
|
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|
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1 Clear Enable */
|
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|
+
|
|
|
+#define TIM_CCMR1_CC2S_Pos (8U)
|
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|
+#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
|
|
|
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
|
|
|
+#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
|
|
|
+#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
|
|
|
+
|
|
|
+#define TIM_CCMR1_OC2FE_Pos (10U)
|
|
|
+#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
|
|
|
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
|
|
|
+#define TIM_CCMR1_OC2PE_Pos (11U)
|
|
|
+#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
|
|
|
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
|
|
|
+
|
|
|
+#define TIM_CCMR1_OC2M_Pos (12U)
|
|
|
+#define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
|
|
|
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
|
|
|
+#define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
|
|
|
+#define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
|
|
|
+#define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
|
|
|
+#define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */
|
|
|
+
|
|
|
+#define TIM_CCMR1_OC2CE_Pos (15U)
|
|
|
+#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
|
|
|
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
|
|
|
+
|
|
|
+/*----------------------------------------------------------------------------*/
|
|
|
+#define TIM_CCMR1_IC1PSC_Pos (2U)
|
|
|
+#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
|
|
|
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
|
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+#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
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+#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
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+
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+#define TIM_CCMR1_IC1F_Pos (4U)
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+#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
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+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
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+#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
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+#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
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+#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
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+#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
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+
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+#define TIM_CCMR1_IC2PSC_Pos (10U)
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+#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
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+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
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+#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
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+#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
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+
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+#define TIM_CCMR1_IC2F_Pos (12U)
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+#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
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+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
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+#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
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+#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
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+#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
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+#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
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+
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+/****************** Bit definition for TIM_CCMR2 register *******************/
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+#define TIM_CCMR2_CC3S_Pos (0U)
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+#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
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+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
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+#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
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+#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
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+
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+#define TIM_CCMR2_OC3FE_Pos (2U)
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+#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
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+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
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+#define TIM_CCMR2_OC3PE_Pos (3U)
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+#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
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+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
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+
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+#define TIM_CCMR2_OC3M_Pos (4U)
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+#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
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+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
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+#define TIM_CCMR2_OC3M_0 (0x0001UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
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+#define TIM_CCMR2_OC3M_1 (0x0002UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
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+#define TIM_CCMR2_OC3M_2 (0x0004UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
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+#define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */
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+
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+#define TIM_CCMR2_OC3CE_Pos (7U)
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+#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
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+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
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+
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+#define TIM_CCMR2_CC4S_Pos (8U)
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+#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
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+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
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+#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
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+#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
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+
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+#define TIM_CCMR2_OC4FE_Pos (10U)
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+#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
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+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
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+#define TIM_CCMR2_OC4PE_Pos (11U)
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+#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
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+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
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+
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+#define TIM_CCMR2_OC4M_Pos (12U)
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+#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
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+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
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+#define TIM_CCMR2_OC4M_0 (0x0001UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
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+#define TIM_CCMR2_OC4M_1 (0x0002UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
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+#define TIM_CCMR2_OC4M_2 (0x0004UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
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+#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
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+
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+#define TIM_CCMR2_OC4CE_Pos (15U)
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+#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
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+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
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+
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+/*----------------------------------------------------------------------------*/
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+#define TIM_CCMR2_IC3PSC_Pos (2U)
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+#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
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+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
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+#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
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+#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
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+
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+#define TIM_CCMR2_IC3F_Pos (4U)
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+#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
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+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
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+#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
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+#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
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+#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
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+#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
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+
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+#define TIM_CCMR2_IC4PSC_Pos (10U)
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+#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
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+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
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+#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
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+#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
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+
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+#define TIM_CCMR2_IC4F_Pos (12U)
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+#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
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+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
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+#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
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+#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
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+#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
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+#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
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+
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+/****************** Bit definition for TIM_CCMR3 register *******************/
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+#define TIM_CCMR3_OC5FE_Pos (2U)
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+#define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
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+#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
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+#define TIM_CCMR3_OC5PE_Pos (3U)
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+#define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
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+#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
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+
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+#define TIM_CCMR3_OC5M_Pos (4U)
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+#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
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+#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
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+#define TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
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+#define TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
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+#define TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
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+#define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
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+
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+#define TIM_CCMR3_OC5CE_Pos (7U)
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+#define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
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+#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
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+
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+#define TIM_CCMR3_OC6FE_Pos (10U)
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+#define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
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+#define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */
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+#define TIM_CCMR3_OC6PE_Pos (11U)
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+#define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
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+#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 6 Preload enable */
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+
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+#define TIM_CCMR3_OC6M_Pos (12U)
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+#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
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+#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
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+#define TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
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+#define TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
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+#define TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
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+#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
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+
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+#define TIM_CCMR3_OC6CE_Pos (15U)
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+#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
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+#define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 6 Clear Enable */
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+
|
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+/******************* Bit definition for TIM_CCER register *******************/
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+#define TIM_CCER_CC1E_Pos (0U)
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+#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
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+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
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+#define TIM_CCER_CC1P_Pos (1U)
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+#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
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+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
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+#define TIM_CCER_CC1NE_Pos (2U)
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+#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
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+#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
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+#define TIM_CCER_CC1NP_Pos (3U)
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+#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
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+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
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+#define TIM_CCER_CC2E_Pos (4U)
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+#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
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+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
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+#define TIM_CCER_CC2P_Pos (5U)
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+#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
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+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
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+#define TIM_CCER_CC2NE_Pos (6U)
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+#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
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+#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
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+#define TIM_CCER_CC2NP_Pos (7U)
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+#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
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+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
|
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+#define TIM_CCER_CC3E_Pos (8U)
|
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+#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
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+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
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+#define TIM_CCER_CC3P_Pos (9U)
|
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+#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
|
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+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
|
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+#define TIM_CCER_CC3NE_Pos (10U)
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+#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
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+#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
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+#define TIM_CCER_CC3NP_Pos (11U)
|
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|
+#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
|
|
|
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
|
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|
+#define TIM_CCER_CC4E_Pos (12U)
|
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|
+#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
|
|
|
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
|
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|
+#define TIM_CCER_CC4P_Pos (13U)
|
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|
+#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
|
|
|
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
|
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|
+#define TIM_CCER_CC4NP_Pos (15U)
|
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|
+#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
|
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|
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
|
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|
+#define TIM_CCER_CC5E_Pos (16U)
|
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|
+#define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
|
|
|
+#define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
|
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|
+#define TIM_CCER_CC5P_Pos (17U)
|
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|
+#define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
|
|
|
+#define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
|
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|
+#define TIM_CCER_CC6E_Pos (20U)
|
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|
+#define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
|
|
|
+#define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
|
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|
+#define TIM_CCER_CC6P_Pos (21U)
|
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|
+#define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
|
|
|
+#define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
|
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|
+
|
|
|
+/******************* Bit definition for TIM_CNT register ********************/
|
|
|
+#define TIM_CNT_CNT_Pos (0U)
|
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|
+#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
|
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|
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
|
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|
+#define TIM_CNT_UIFCPY_Pos (31U)
|
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|
+#define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
|
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+#define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy (if UIFREMAP=1) */
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+
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+/******************* Bit definition for TIM_PSC register ********************/
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+#define TIM_PSC_PSC_Pos (0U)
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+#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
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+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
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+
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+/******************* Bit definition for TIM_ARR register ********************/
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+#define TIM_ARR_ARR_Pos (0U)
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+#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
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+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<Actual auto-reload Value */
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+
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+/******************* Bit definition for TIM_RCR register ********************/
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+#define TIM_RCR_REP_Pos (0U)
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+#define TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */
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+#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
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+
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+/******************* Bit definition for TIM_CCR1 register *******************/
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+#define TIM_CCR1_CCR1_Pos (0U)
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+#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
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+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
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+
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+/******************* Bit definition for TIM_CCR2 register *******************/
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+#define TIM_CCR2_CCR2_Pos (0U)
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+#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
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+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
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+
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+/******************* Bit definition for TIM_CCR3 register *******************/
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+#define TIM_CCR3_CCR3_Pos (0U)
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+#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
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+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
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+
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+/******************* Bit definition for TIM_CCR4 register *******************/
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+#define TIM_CCR4_CCR4_Pos (0U)
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+#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
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+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
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+
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+/******************* Bit definition for TIM_CCR5 register *******************/
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+#define TIM_CCR5_CCR5_Pos (0U)
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+#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
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+#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
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+#define TIM_CCR5_GC5C1_Pos (29U)
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+#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
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+#define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
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+#define TIM_CCR5_GC5C2_Pos (30U)
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+#define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
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+#define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
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+#define TIM_CCR5_GC5C3_Pos (31U)
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+#define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
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+#define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
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+
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+/******************* Bit definition for TIM_CCR6 register *******************/
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+#define TIM_CCR6_CCR6_Pos (0U)
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+#define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
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+#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
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+
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+/******************* Bit definition for TIM_BDTR register *******************/
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+#define TIM_BDTR_DTG_Pos (0U)
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+#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
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+#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
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+#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
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+#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
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+#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
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+#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
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+#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
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+#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
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+#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
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+#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
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+
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+#define TIM_BDTR_LOCK_Pos (8U)
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+#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
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+#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
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+#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
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+#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
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+
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+#define TIM_BDTR_OSSI_Pos (10U)
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+#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
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+#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
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+#define TIM_BDTR_OSSR_Pos (11U)
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+#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
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+#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
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+#define TIM_BDTR_BKE_Pos (12U)
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+#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
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+#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break 1 */
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+#define TIM_BDTR_BKP_Pos (13U)
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+#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
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+#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break 1 */
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+#define TIM_BDTR_AOE_Pos (14U)
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+#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
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+#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
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+#define TIM_BDTR_MOE_Pos (15U)
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+#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
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+#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
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+
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|
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+#define TIM_BDTR_BKF_Pos (16U)
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+#define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
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+#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break 1 */
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+#define TIM_BDTR_BK2F_Pos (20U)
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+#define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
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+#define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break 2 */
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+
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+#define TIM_BDTR_BK2E_Pos (24U)
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+#define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
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+#define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break 2 */
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+#define TIM_BDTR_BK2P_Pos (25U)
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+#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
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+#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break 2 */
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+
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+#define TIM_BDTR_BKDSRM_Pos (26U)
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+#define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos) /*!< 0x04000000 */
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+#define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break disarming/re-arming */
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+#define TIM_BDTR_BK2DSRM_Pos (27U)
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+#define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos) /*!< 0x08000000 */
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+#define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 disarming/re-arming */
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+
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+#define TIM_BDTR_BKBID_Pos (28U)
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+#define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos) /*!< 0x10000000 */
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+#define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk /*!<Break BIDirectional */
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+#define TIM_BDTR_BK2BID_Pos (29U)
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+#define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos) /*!< 0x20000000 */
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+#define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk /*!<Break2 BIDirectional */
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+
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+/******************* Bit definition for TIM_DCR register ********************/
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+#define TIM_DCR_DBA_Pos (0U)
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+#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
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+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
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+#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
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+#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
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+#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
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+#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
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+#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
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+
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+#define TIM_DCR_DBL_Pos (8U)
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+#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
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+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
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+#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
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+#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
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+#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
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+#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
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+#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
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+
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+/******************* Bit definition for TIM_DMAR register *******************/
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+#define TIM_DMAR_DMAB_Pos (0U)
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+#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
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+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
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+
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+/******************* Bit definition for TIM1_OR1 register *******************/
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+#define TIM1_OR1_OCREF_CLR_Pos (0U)
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+#define TIM1_OR1_OCREF_CLR_Msk (0x1UL << TIM1_OR1_OCREF_CLR_Pos) /*!< 0x00000001 */
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+#define TIM1_OR1_OCREF_CLR TIM1_OR1_OCREF_CLR_Msk /*!<OCREF clear input selection */
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+
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|
|
+/******************* Bit definition for TIM1_AF1 register *******************/
|
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+#define TIM1_AF1_BKINE_Pos (0U)
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+#define TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos) /*!< 0x00000001 */
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+#define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk /*!<BRK BKIN input enable */
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+#define TIM1_AF1_BKCMP1E_Pos (1U)
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+#define TIM1_AF1_BKCMP1E_Msk (0x1UL << TIM1_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
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+#define TIM1_AF1_BKCMP1E TIM1_AF1_BKCMP1E_Msk /*!<BRK COMP1 enable */
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+#define TIM1_AF1_BKCMP2E_Pos (2U)
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+#define TIM1_AF1_BKCMP2E_Msk (0x1UL << TIM1_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
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+#define TIM1_AF1_BKCMP2E TIM1_AF1_BKCMP2E_Msk /*!<BRK COMP2 enable */
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+#define TIM1_AF1_BKINP_Pos (9U)
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+#define TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos) /*!< 0x00000200 */
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+#define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk /*!<BRK BKIN input polarity */
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+#define TIM1_AF1_BKCMP1P_Pos (10U)
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+#define TIM1_AF1_BKCMP1P_Msk (0x1UL << TIM1_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
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+#define TIM1_AF1_BKCMP1P TIM1_AF1_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
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+#define TIM1_AF1_BKCMP2P_Pos (11U)
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+#define TIM1_AF1_BKCMP2P_Msk (0x1UL << TIM1_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
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+#define TIM1_AF1_BKCMP2P TIM1_AF1_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
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+
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+#define TIM1_AF1_ETRSEL_Pos (14U)
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+#define TIM1_AF1_ETRSEL_Msk (0xFUL << TIM1_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
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+#define TIM1_AF1_ETRSEL TIM1_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */
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+#define TIM1_AF1_ETRSEL_0 (0x1UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00004000 */
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+#define TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00008000 */
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+#define TIM1_AF1_ETRSEL_2 (0x4UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00010000 */
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+#define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00020000 */
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+
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|
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+/******************* Bit definition for TIM1_AF2 register *******************/
|
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+#define TIM1_AF2_BK2INE_Pos (0U)
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+#define TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos) /*!< 0x00000001 */
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+#define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk /*!<BRK2 BKIN2 input enable */
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+#define TIM1_AF2_BK2CMP1E_Pos (1U)
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+#define TIM1_AF2_BK2CMP1E_Msk (0x1UL << TIM1_AF2_BK2CMP1E_Pos) /*!< 0x00000002 */
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+#define TIM1_AF2_BK2CMP1E TIM1_AF2_BK2CMP1E_Msk /*!<BRK2 COMP1 enable */
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+#define TIM1_AF2_BK2CMP2E_Pos (2U)
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+#define TIM1_AF2_BK2CMP2E_Msk (0x1UL << TIM1_AF2_BK2CMP2E_Pos) /*!< 0x00000004 */
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+#define TIM1_AF2_BK2CMP2E TIM1_AF2_BK2CMP2E_Msk /*!<BRK2 COMP2 enable */
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|
+#define TIM1_AF2_BK2INP_Pos (9U)
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+#define TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos) /*!< 0x00000200 */
|
|
|
+#define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk /*!<BRK2 BKIN2 input polarity */
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+#define TIM1_AF2_BK2CMP1P_Pos (10U)
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+#define TIM1_AF2_BK2CMP1P_Msk (0x1UL << TIM1_AF2_BK2CMP1P_Pos) /*!< 0x00000400 */
|
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+#define TIM1_AF2_BK2CMP1P TIM1_AF2_BK2CMP1P_Msk /*!<BRK2 COMP1 input polarity */
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|
|
+#define TIM1_AF2_BK2CMP2P_Pos (11U)
|
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|
+#define TIM1_AF2_BK2CMP2P_Msk (0x1UL << TIM1_AF2_BK2CMP2P_Pos) /*!< 0x00000800 */
|
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|
+#define TIM1_AF2_BK2CMP2P TIM1_AF2_BK2CMP2P_Msk /*!<BRK2 COMP2 input polarity */
|
|
|
+
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|
|
+
|
|
|
+/******************* Bit definition for TIM3_OR1 register *******************/
|
|
|
+#define TIM3_OR1_OCREF_CLR_Pos (0U)
|
|
|
+#define TIM3_OR1_OCREF_CLR_Msk (0x1UL << TIM3_OR1_OCREF_CLR_Pos) /*!< 0x00000001 */
|
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|
+#define TIM3_OR1_OCREF_CLR TIM3_OR1_OCREF_CLR_Msk /*!<OCREF clear input selection */
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+
|
|
|
+/******************* Bit definition for TIM3_AF1 register *******************/
|
|
|
+#define TIM3_AF1_ETRSEL_Pos (14U)
|
|
|
+#define TIM3_AF1_ETRSEL_Msk (0xFUL << TIM3_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
|
|
|
+#define TIM3_AF1_ETRSEL TIM3_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM3 ETR source selection) */
|
|
|
+#define TIM3_AF1_ETRSEL_0 (0x1UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00004000 */
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|
+#define TIM3_AF1_ETRSEL_1 (0x2UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00008000 */
|
|
|
+#define TIM3_AF1_ETRSEL_2 (0x4UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00010000 */
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|
+#define TIM3_AF1_ETRSEL_3 (0x8UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00020000 */
|
|
|
+
|
|
|
+/******************* Bit definition for TIM14_AF1 register *******************/
|
|
|
+#define TIM14_AF1_ETRSEL_Pos (14U)
|
|
|
+#define TIM14_AF1_ETRSEL_Msk (0xFUL << TIM14_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
|
|
|
+#define TIM14_AF1_ETRSEL TIM14_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM14 ETR source selection) */
|
|
|
+#define TIM14_AF1_ETRSEL_0 (0x1UL << TIM14_AF1_ETRSEL_Pos) /*!< 0x00004000 */
|
|
|
+#define TIM14_AF1_ETRSEL_1 (0x2UL << TIM14_AF1_ETRSEL_Pos) /*!< 0x00008000 */
|
|
|
+#define TIM14_AF1_ETRSEL_2 (0x4UL << TIM14_AF1_ETRSEL_Pos) /*!< 0x00010000 */
|
|
|
+#define TIM14_AF1_ETRSEL_3 (0x8UL << TIM14_AF1_ETRSEL_Pos) /*!< 0x00020000 */
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+
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+
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+/******************* Bit definition for TIM16_AF1 register ******************/
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+#define TIM16_AF1_BKINE_Pos (0U)
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+#define TIM16_AF1_BKINE_Msk (0x1UL << TIM16_AF1_BKINE_Pos) /*!< 0x00000001 */
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+#define TIM16_AF1_BKINE TIM16_AF1_BKINE_Msk /*!<BRK BKIN input enable */
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+#define TIM16_AF1_BKCMP1E_Pos (1U)
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+#define TIM16_AF1_BKCMP1E_Msk (0x1UL << TIM16_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
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+#define TIM16_AF1_BKCMP1E TIM16_AF1_BKCMP1E_Msk /*!<BRK COMP1 enable */
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+#define TIM16_AF1_BKCMP2E_Pos (2U)
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+#define TIM16_AF1_BKCMP2E_Msk (0x1UL << TIM16_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
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+#define TIM16_AF1_BKCMP2E TIM16_AF1_BKCMP2E_Msk /*!<BRK COMP2 enable */
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+#define TIM16_AF1_BKINP_Pos (9U)
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+#define TIM16_AF1_BKINP_Msk (0x1UL << TIM16_AF1_BKINP_Pos) /*!< 0x00000200 */
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+#define TIM16_AF1_BKINP TIM16_AF1_BKINP_Msk /*!<BRK BKIN input polarity */
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+#define TIM16_AF1_BKCMP1P_Pos (10U)
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+#define TIM16_AF1_BKCMP1P_Msk (0x1UL << TIM16_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
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+#define TIM16_AF1_BKCMP1P TIM16_AF1_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
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+#define TIM16_AF1_BKCMP2P_Pos (11U)
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+#define TIM16_AF1_BKCMP2P_Msk (0x1UL << TIM16_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
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+#define TIM16_AF1_BKCMP2P TIM16_AF1_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
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+
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+/******************* Bit definition for TIM17_AF1 register ******************/
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+#define TIM17_AF1_BKINE_Pos (0U)
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+#define TIM17_AF1_BKINE_Msk (0x1UL << TIM17_AF1_BKINE_Pos) /*!< 0x00000001 */
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+#define TIM17_AF1_BKINE TIM17_AF1_BKINE_Msk /*!<BRK BKIN input enable */
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+#define TIM17_AF1_BKCMP1E_Pos (1U)
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+#define TIM17_AF1_BKCMP1E_Msk (0x1UL << TIM17_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
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+#define TIM17_AF1_BKCMP1E TIM17_AF1_BKCMP1E_Msk /*!<BRK COMP1 enable */
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+#define TIM17_AF1_BKCMP2E_Pos (2U)
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+#define TIM17_AF1_BKCMP2E_Msk (0x1UL << TIM17_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
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+#define TIM17_AF1_BKCMP2E TIM17_AF1_BKCMP2E_Msk /*!<BRK COMP2 enable */
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+#define TIM17_AF1_BKINP_Pos (9U)
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+#define TIM17_AF1_BKINP_Msk (0x1UL << TIM17_AF1_BKINP_Pos) /*!< 0x00000200 */
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+#define TIM17_AF1_BKINP TIM17_AF1_BKINP_Msk /*!<BRK BKIN input polarity */
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+#define TIM17_AF1_BKCMP1P_Pos (10U)
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+#define TIM17_AF1_BKCMP1P_Msk (0x1UL << TIM17_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
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+#define TIM17_AF1_BKCMP1P TIM17_AF1_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
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+#define TIM17_AF1_BKCMP2P_Pos (11U)
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+#define TIM17_AF1_BKCMP2P_Msk (0x1UL << TIM17_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
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+#define TIM17_AF1_BKCMP2P TIM17_AF1_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
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+
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+/******************* Bit definition for TIM_TISEL register *********************/
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+#define TIM_TISEL_TI1SEL_Pos (0U)
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+#define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
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+#define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM TI1 SEL)*/
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+#define TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
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+#define TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
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+#define TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
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+#define TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
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+
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+#define TIM_TISEL_TI2SEL_Pos (8U)
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+#define TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
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+#define TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM TI2 SEL)*/
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+#define TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
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+#define TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
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+#define TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
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+#define TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
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+
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+#define TIM_TISEL_TI3SEL_Pos (16U)
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+#define TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */
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+#define TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM TI3 SEL)*/
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+#define TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00010000 */
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+#define TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00020000 */
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+#define TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00040000 */
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+#define TIM_TISEL_TI3SEL_3 (0x8UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00080000 */
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+
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+#define TIM_TISEL_TI4SEL_Pos (24U)
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+#define TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */
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+#define TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM TI4 SEL)*/
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+#define TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x01000000 */
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+#define TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x02000000 */
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+#define TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x04000000 */
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+#define TIM_TISEL_TI4SEL_3 (0x8UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x08000000 */
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+
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+
|
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+
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+/******************************************************************************/
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|
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+/* */
|
|
|
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
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+/* */
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+/******************************************************************************/
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+/****************** Bit definition for USART_CR1 register *******************/
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+#define USART_CR1_UE_Pos (0U)
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+#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
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+#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
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+#define USART_CR1_UESM_Pos (1U)
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+#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */
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+#define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
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+#define USART_CR1_RE_Pos (2U)
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+#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
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+#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
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+#define USART_CR1_TE_Pos (3U)
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+#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
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+#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
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+#define USART_CR1_IDLEIE_Pos (4U)
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+#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
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+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
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+#define USART_CR1_RXNEIE_RXFNEIE_Pos (5U)
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+#define USART_CR1_RXNEIE_RXFNEIE_Msk (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */
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+#define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE_Msk /*!< RXNE/RXFIFO not empty Interrupt Enable */
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+#define USART_CR1_TCIE_Pos (6U)
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+#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
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+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
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+#define USART_CR1_TXEIE_TXFNFIE_Pos (7U)
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+#define USART_CR1_TXEIE_TXFNFIE_Msk (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */
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+#define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE_Msk /*!< TXE/TXFIFO not full Interrupt Enable */
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+#define USART_CR1_PEIE_Pos (8U)
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+#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
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+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
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+#define USART_CR1_PS_Pos (9U)
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+#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
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+#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
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+#define USART_CR1_PCE_Pos (10U)
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+#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
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+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
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+#define USART_CR1_WAKE_Pos (11U)
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+#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
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+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
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+#define USART_CR1_M_Pos (12U)
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+#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */
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+#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
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+#define USART_CR1_M0_Pos (12U)
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+#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */
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+#define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
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+#define USART_CR1_MME_Pos (13U)
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+#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */
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+#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
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+#define USART_CR1_CMIE_Pos (14U)
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+#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
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+#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
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+#define USART_CR1_OVER8_Pos (15U)
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+#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
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+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
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+#define USART_CR1_DEDT_Pos (16U)
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+#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
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+#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
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+#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
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+#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
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+#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
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+#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
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+#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
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+#define USART_CR1_DEAT_Pos (21U)
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+#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
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+#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
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+#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
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+#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
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+#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
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+#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
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+#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
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+#define USART_CR1_RTOIE_Pos (26U)
|
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|
+#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
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|
+#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
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+#define USART_CR1_EOBIE_Pos (27U)
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|
+#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
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|
+#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
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+#define USART_CR1_M1_Pos (28U)
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+#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */
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+#define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
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+#define USART_CR1_FIFOEN_Pos (29U)
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+#define USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos) /*!< 0x20000000 */
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+#define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk /*!< FIFO mode enable */
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+#define USART_CR1_TXFEIE_Pos (30U)
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+#define USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos) /*!< 0x40000000 */
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+#define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk /*!< TXFIFO empty interrupt enable */
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+#define USART_CR1_RXFFIE_Pos (31U)
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+#define USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos) /*!< 0x80000000 */
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+#define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk /*!< RXFIFO Full interrupt enable */
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+
|
|
|
+/****************** Bit definition for USART_CR2 register *******************/
|
|
|
+#define USART_CR2_SLVEN_Pos (0U)
|
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|
+#define USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos) /*!< 0x00000001 */
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+#define USART_CR2_SLVEN USART_CR2_SLVEN_Msk /*!< Synchronous Slave mode enable */
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+#define USART_CR2_DIS_NSS_Pos (3U)
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|
+#define USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos) /*!< 0x00000008 */
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+#define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk /*!< NSS input pin disable for SPI slave selection */
|
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|
+#define USART_CR2_ADDM7_Pos (4U)
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|
+#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
|
|
|
+#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
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|
|
+#define USART_CR2_LBDL_Pos (5U)
|
|
|
+#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
|
|
|
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
|
|
|
+#define USART_CR2_LBDIE_Pos (6U)
|
|
|
+#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
|
|
|
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
|
|
|
+#define USART_CR2_LBCL_Pos (8U)
|
|
|
+#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
|
|
|
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
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|
|
+#define USART_CR2_CPHA_Pos (9U)
|
|
|
+#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
|
|
|
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
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|
|
+#define USART_CR2_CPOL_Pos (10U)
|
|
|
+#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
|
|
|
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
|
|
|
+#define USART_CR2_CLKEN_Pos (11U)
|
|
|
+#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
|
|
|
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
|
|
|
+#define USART_CR2_STOP_Pos (12U)
|
|
|
+#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
|
|
|
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
|
|
|
+#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */
|
|
|
+#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */
|
|
|
+#define USART_CR2_LINEN_Pos (14U)
|
|
|
+#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
|
|
|
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
|
|
|
+#define USART_CR2_SWAP_Pos (15U)
|
|
|
+#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
|
|
|
+#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
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+#define USART_CR2_RXINV_Pos (16U)
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+#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
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+#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
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+#define USART_CR2_TXINV_Pos (17U)
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+#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
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+#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
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+#define USART_CR2_DATAINV_Pos (18U)
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+#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
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+#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
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+#define USART_CR2_MSBFIRST_Pos (19U)
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+#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
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+#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
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+#define USART_CR2_ABREN_Pos (20U)
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+#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
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+#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
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+#define USART_CR2_ABRMODE_Pos (21U)
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+#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
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+#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
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+#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
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+#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
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+#define USART_CR2_RTOEN_Pos (23U)
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+#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
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+#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
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+#define USART_CR2_ADD_Pos (24U)
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+#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
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+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
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+
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+/****************** Bit definition for USART_CR3 register *******************/
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+#define USART_CR3_EIE_Pos (0U)
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+#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
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+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
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+#define USART_CR3_IREN_Pos (1U)
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+#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
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+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
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+#define USART_CR3_IRLP_Pos (2U)
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+#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
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+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
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+#define USART_CR3_HDSEL_Pos (3U)
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+#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
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+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
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+#define USART_CR3_NACK_Pos (4U)
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+#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
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+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
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+#define USART_CR3_SCEN_Pos (5U)
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+#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
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+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
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+#define USART_CR3_DMAR_Pos (6U)
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+#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
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+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
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+#define USART_CR3_DMAT_Pos (7U)
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+#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
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+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
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+#define USART_CR3_RTSE_Pos (8U)
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+#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
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+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
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+#define USART_CR3_CTSE_Pos (9U)
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+#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
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+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
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+#define USART_CR3_CTSIE_Pos (10U)
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+#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
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+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
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+#define USART_CR3_ONEBIT_Pos (11U)
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+#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
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+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
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+#define USART_CR3_OVRDIS_Pos (12U)
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+#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
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+#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
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+#define USART_CR3_DDRE_Pos (13U)
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+#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
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+#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
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+#define USART_CR3_DEM_Pos (14U)
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+#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */
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+#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
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+#define USART_CR3_DEP_Pos (15U)
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+#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */
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+#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
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+#define USART_CR3_SCARCNT_Pos (17U)
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+#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
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+#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
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+#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
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+#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
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+#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
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+#define USART_CR3_WUS_Pos (20U)
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+#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */
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+#define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
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+#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */
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+#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */
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+#define USART_CR3_WUFIE_Pos (22U)
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+#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
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+#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
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+#define USART_CR3_TXFTIE_Pos (23U)
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+#define USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos) /*!< 0x00800000 */
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+#define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk /*!< TXFIFO threshold interrupt enable */
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+#define USART_CR3_TCBGTIE_Pos (24U)
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+#define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */
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+#define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete Before Guard Time Interrupt Enable */
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+#define USART_CR3_RXFTCFG_Pos (25U)
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+#define USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos) /*!< 0x0E000000 */
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+#define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk /*!< RXFIFO FIFO threshold configuration */
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+#define USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos) /*!< 0x02000000 */
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+#define USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos) /*!< 0x04000000 */
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+#define USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos) /*!< 0x08000000 */
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+#define USART_CR3_RXFTIE_Pos (28U)
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+#define USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos) /*!< 0x10000000 */
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+#define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk /*!< RXFIFO threshold interrupt enable */
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+#define USART_CR3_TXFTCFG_Pos (29U)
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+#define USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos) /*!< 0xE0000000 */
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+#define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk /*!< TXFIFO threshold configuration */
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+#define USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos) /*!< 0x20000000 */
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+#define USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos) /*!< 0x40000000 */
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+#define USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos) /*!< 0x80000000 */
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+
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+/****************** Bit definition for USART_BRR register *******************/
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+#define USART_BRR_BRR ((uint16_t)0xFFFF) /*!< USART Baud rate register [15:0] */
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+
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+/****************** Bit definition for USART_GTPR register ******************/
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+#define USART_GTPR_PSC_Pos (0U)
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+#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
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+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
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+#define USART_GTPR_GT_Pos (8U)
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+#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
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+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
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+
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+/******************* Bit definition for USART_RTOR register *****************/
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+#define USART_RTOR_RTO_Pos (0U)
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+#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
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+#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
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+#define USART_RTOR_BLEN_Pos (24U)
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+#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
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+#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
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+
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+/******************* Bit definition for USART_RQR register ******************/
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+#define USART_RQR_ABRRQ ((uint16_t)0x0001) /*!< Auto-Baud Rate Request */
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+#define USART_RQR_SBKRQ ((uint16_t)0x0002) /*!< Send Break Request */
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+#define USART_RQR_MMRQ ((uint16_t)0x0004) /*!< Mute Mode Request */
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+#define USART_RQR_RXFRQ ((uint16_t)0x0008) /*!< Receive Data flush Request */
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+#define USART_RQR_TXFRQ ((uint16_t)0x0010) /*!< Transmit data flush Request */
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+
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+/******************* Bit definition for USART_ISR register ******************/
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+#define USART_ISR_PE_Pos (0U)
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+#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */
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+#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
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+#define USART_ISR_FE_Pos (1U)
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+#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */
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+#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
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+#define USART_ISR_NE_Pos (2U)
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+#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */
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+#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
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+#define USART_ISR_ORE_Pos (3U)
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+#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */
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+#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
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+#define USART_ISR_IDLE_Pos (4U)
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+#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
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+#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
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+#define USART_ISR_RXNE_RXFNE_Pos (5U)
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+#define USART_ISR_RXNE_RXFNE_Msk (0x1UL << USART_ISR_RXNE_RXFNE_Pos) /*!< 0x00000020 */
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+#define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE_Msk /*!< Read Data Register Not Empty/RXFIFO Not Empty */
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+#define USART_ISR_TC_Pos (6U)
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+#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */
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+#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
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+#define USART_ISR_TXE_TXFNF_Pos (7U)
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+#define USART_ISR_TXE_TXFNF_Msk (0x1UL << USART_ISR_TXE_TXFNF_Pos) /*!< 0x00000080 */
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+#define USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF_Msk /*!< Transmit Data Register Empty/TXFIFO Not Full */
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+#define USART_ISR_LBDF_Pos (8U)
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+#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
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+#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
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+#define USART_ISR_CTSIF_Pos (9U)
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+#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
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+#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
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+#define USART_ISR_CTS_Pos (10U)
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+#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */
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+#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
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+#define USART_ISR_RTOF_Pos (11U)
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+#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
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+#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
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+#define USART_ISR_EOBF_Pos (12U)
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+#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
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+#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
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+#define USART_ISR_UDR_Pos (13U)
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+#define USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos) /*!< 0x00002000 */
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+#define USART_ISR_UDR USART_ISR_UDR_Msk /*!< SPI Slave Underrun Error Flag */
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+#define USART_ISR_ABRE_Pos (14U)
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+#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
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+#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
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+#define USART_ISR_ABRF_Pos (15U)
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+#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
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+#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
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+#define USART_ISR_BUSY_Pos (16U)
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+#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
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+#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
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+#define USART_ISR_CMF_Pos (17U)
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+#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */
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+#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
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+#define USART_ISR_SBKF_Pos (18U)
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+#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
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+#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
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+#define USART_ISR_RWU_Pos (19U)
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+#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */
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+#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
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+#define USART_ISR_WUF_Pos (20U)
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+#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */
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+#define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
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+#define USART_ISR_TEACK_Pos (21U)
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+#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
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+#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
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+#define USART_ISR_REACK_Pos (22U)
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+#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */
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+#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
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+#define USART_ISR_TXFE_Pos (23U)
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+#define USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos) /*!< 0x00800000 */
|
|
|
+#define USART_ISR_TXFE USART_ISR_TXFE_Msk /*!< TXFIFO Empty Flag */
|
|
|
+#define USART_ISR_RXFF_Pos (24U)
|
|
|
+#define USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos) /*!< 0x01000000 */
|
|
|
+#define USART_ISR_RXFF USART_ISR_RXFF_Msk /*!< RXFIFO Full Flag */
|
|
|
+#define USART_ISR_TCBGT_Pos (25U)
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|
|
+#define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */
|
|
|
+#define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission Complete Before Guard Time Completion Flag */
|
|
|
+#define USART_ISR_RXFT_Pos (26U)
|
|
|
+#define USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos) /*!< 0x04000000 */
|
|
|
+#define USART_ISR_RXFT USART_ISR_RXFT_Msk /*!< RXFIFO Threshold Flag */
|
|
|
+#define USART_ISR_TXFT_Pos (27U)
|
|
|
+#define USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos) /*!< 0x08000000 */
|
|
|
+#define USART_ISR_TXFT USART_ISR_TXFT_Msk /*!< TXFIFO Threshold Flag */
|
|
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+
|
|
|
+/******************* Bit definition for USART_ICR register ******************/
|
|
|
+#define USART_ICR_PECF_Pos (0U)
|
|
|
+#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */
|
|
|
+#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
|
|
|
+#define USART_ICR_FECF_Pos (1U)
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|
+#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */
|
|
|
+#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
|
|
|
+#define USART_ICR_NECF_Pos (2U)
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|
+#define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos) /*!< 0x00000004 */
|
|
|
+#define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise Error detected Clear Flag */
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|
|
+#define USART_ICR_ORECF_Pos (3U)
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|
+#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
|
|
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+#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
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|
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+#define USART_ICR_IDLECF_Pos (4U)
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+#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
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+#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
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+#define USART_ICR_TXFECF_Pos (5U)
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+#define USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos) /*!< 0x00000020 */
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|
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+#define USART_ICR_TXFECF USART_ICR_TXFECF_Msk /*!< TXFIFO Empty Clear Flag */
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+#define USART_ICR_TCCF_Pos (6U)
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+#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
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+#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
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+#define USART_ICR_TCBGTCF_Pos (7U)
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+#define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */
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+#define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission Complete Before Guard Time Clear Flag */
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+#define USART_ICR_LBDCF_Pos (8U)
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+#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
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+#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
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+#define USART_ICR_CTSCF_Pos (9U)
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+#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
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+#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
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+#define USART_ICR_RTOCF_Pos (11U)
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+#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
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+#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
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+#define USART_ICR_EOBCF_Pos (12U)
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+#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
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+#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
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+#define USART_ICR_UDRCF_Pos (13U)
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+#define USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos) /*!< 0x00002000 */
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+#define USART_ICR_UDRCF USART_ICR_UDRCF_Msk /*!< SPI Slave Underrun Clear Flag */
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+#define USART_ICR_CMCF_Pos (17U)
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+#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
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+#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
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+#define USART_ICR_WUCF_Pos (20U)
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+#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
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|
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+#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
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+
|
|
|
+/******************* Bit definition for USART_RDR register ******************/
|
|
|
+#define USART_RDR_RDR_Pos (0U)
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|
+#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */
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|
|
+#define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
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+
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|
|
+/******************* Bit definition for USART_TDR register ******************/
|
|
|
+#define USART_TDR_TDR_Pos (0U)
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|
+#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */
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|
|
+#define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
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+
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|
|
+/******************* Bit definition for USART_PRESC register ****************/
|
|
|
+#define USART_PRESC_PRESCALER_Pos (0U)
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|
+#define USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos) /*!< 0x0000000F */
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|
|
+#define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk /*!< PRESCALER[3:0] bits (Clock prescaler) */
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|
|
+#define USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000001 */
|
|
|
+#define USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000002 */
|
|
|
+#define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */
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|
|
+#define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
|
|
|
+
|
|
|
+
|
|
|
+/******************************************************************************/
|
|
|
+/* */
|
|
|
+/* Window WATCHDOG */
|
|
|
+/* */
|
|
|
+/******************************************************************************/
|
|
|
+/******************* Bit definition for WWDG_CR register ********************/
|
|
|
+#define WWDG_CR_T_Pos (0U)
|
|
|
+#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
|
|
|
+#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
|
|
|
+#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */
|
|
|
+#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */
|
|
|
+#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */
|
|
|
+#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */
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|
|
+#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */
|
|
|
+#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */
|
|
|
+#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */
|
|
|
+
|
|
|
+#define WWDG_CR_WDGA_Pos (7U)
|
|
|
+#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
|
|
|
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
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|
|
+
|
|
|
+/******************* Bit definition for WWDG_CFR register *******************/
|
|
|
+#define WWDG_CFR_W_Pos (0U)
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|
|
+#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
|
|
|
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
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|
|
+#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */
|
|
|
+#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */
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|
|
+#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */
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|
|
+#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */
|
|
|
+#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */
|
|
|
+#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */
|
|
|
+#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */
|
|
|
+
|
|
|
+#define WWDG_CFR_WDGTB_Pos (11U)
|
|
|
+#define WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00003800 */
|
|
|
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[2:0] bits (Timer Base) */
|
|
|
+#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000800 */
|
|
|
+#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00001000 */
|
|
|
+#define WWDG_CFR_WDGTB_2 (0x4UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00002000 */
|
|
|
+
|
|
|
+#define WWDG_CFR_EWI_Pos (9U)
|
|
|
+#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
|
|
|
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
|
|
|
+
|
|
|
+/******************* Bit definition for WWDG_SR register ********************/
|
|
|
+#define WWDG_SR_EWIF_Pos (0U)
|
|
|
+#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
|
|
|
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
|
|
|
+
|
|
|
+/******************************************************************************/
|
|
|
+/* */
|
|
|
+/* Debug MCU */
|
|
|
+/* */
|
|
|
+/******************************************************************************/
|
|
|
+/******************** Bit definition for DBG_IDCODE register *************/
|
|
|
+#define DBG_IDCODE_DEV_ID_Pos (0U)
|
|
|
+#define DBG_IDCODE_DEV_ID_Msk (0xFFFUL << DBG_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
|
|
|
+#define DBG_IDCODE_DEV_ID DBG_IDCODE_DEV_ID_Msk
|
|
|
+#define DBG_IDCODE_REV_ID_Pos (16U)
|
|
|
+#define DBG_IDCODE_REV_ID_Msk (0xFFFFUL << DBG_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
|
|
|
+#define DBG_IDCODE_REV_ID DBG_IDCODE_REV_ID_Msk
|
|
|
+
|
|
|
+/******************** Bit definition for DBG_CR register *****************/
|
|
|
+#define DBG_CR_DBG_STOP_Pos (1U)
|
|
|
+#define DBG_CR_DBG_STOP_Msk (0x1UL << DBG_CR_DBG_STOP_Pos) /*!< 0x00000002 */
|
|
|
+#define DBG_CR_DBG_STOP DBG_CR_DBG_STOP_Msk
|
|
|
+#define DBG_CR_DBG_STANDBY_Pos (2U)
|
|
|
+#define DBG_CR_DBG_STANDBY_Msk (0x1UL << DBG_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
|
|
|
+#define DBG_CR_DBG_STANDBY DBG_CR_DBG_STANDBY_Msk
|
|
|
+
|
|
|
+
|
|
|
+/******************** Bit definition for DBG_APB_FZ1 register ***********/
|
|
|
+#define DBG_APB_FZ1_DBG_TIM3_STOP_Pos (1U)
|
|
|
+#define DBG_APB_FZ1_DBG_TIM3_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
|
|
|
+#define DBG_APB_FZ1_DBG_TIM3_STOP DBG_APB_FZ1_DBG_TIM3_STOP_Msk
|
|
|
+#define DBG_APB_FZ1_DBG_RTC_STOP_Pos (10U)
|
|
|
+#define DBG_APB_FZ1_DBG_RTC_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
|
|
|
+#define DBG_APB_FZ1_DBG_RTC_STOP DBG_APB_FZ1_DBG_RTC_STOP_Msk
|
|
|
+#define DBG_APB_FZ1_DBG_WWDG_STOP_Pos (11U)
|
|
|
+#define DBG_APB_FZ1_DBG_WWDG_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
|
|
|
+#define DBG_APB_FZ1_DBG_WWDG_STOP DBG_APB_FZ1_DBG_WWDG_STOP_Msk
|
|
|
+#define DBG_APB_FZ1_DBG_IWDG_STOP_Pos (12U)
|
|
|
+#define DBG_APB_FZ1_DBG_IWDG_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
|
|
|
+#define DBG_APB_FZ1_DBG_IWDG_STOP DBG_APB_FZ1_DBG_IWDG_STOP_Msk
|
|
|
+#define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Pos (21U)
|
|
|
+#define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Pos) /*!< 0x00200000 */
|
|
|
+#define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Msk
|
|
|
+
|
|
|
+/******************** Bit definition for DBG_APB_FZ2 register ************/
|
|
|
+#define DBG_APB_FZ2_DBG_TIM1_STOP_Pos (11U)
|
|
|
+#define DBG_APB_FZ2_DBG_TIM1_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */
|
|
|
+#define DBG_APB_FZ2_DBG_TIM1_STOP DBG_APB_FZ2_DBG_TIM1_STOP_Msk
|
|
|
+#define DBG_APB_FZ2_DBG_TIM14_STOP_Pos (15U)
|
|
|
+#define DBG_APB_FZ2_DBG_TIM14_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM14_STOP_Pos) /*!< 0x00008000 */
|
|
|
+#define DBG_APB_FZ2_DBG_TIM14_STOP DBG_APB_FZ2_DBG_TIM14_STOP_Msk
|
|
|
+#define DBG_APB_FZ2_DBG_TIM16_STOP_Pos (17U)
|
|
|
+#define DBG_APB_FZ2_DBG_TIM16_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */
|
|
|
+#define DBG_APB_FZ2_DBG_TIM16_STOP DBG_APB_FZ2_DBG_TIM16_STOP_Msk
|
|
|
+#define DBG_APB_FZ2_DBG_TIM17_STOP_Pos (18U)
|
|
|
+#define DBG_APB_FZ2_DBG_TIM17_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */
|
|
|
+#define DBG_APB_FZ2_DBG_TIM17_STOP DBG_APB_FZ2_DBG_TIM17_STOP_Msk
|
|
|
+
|
|
|
+
|
|
|
+/** @addtogroup Exported_macros
|
|
|
+ * @{
|
|
|
+ */
|
|
|
+
|
|
|
+/******************************* ADC Instances ********************************/
|
|
|
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
|
|
|
+
|
|
|
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+/******************************* CRC Instances ********************************/
|
|
|
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
|
|
|
+
|
|
|
+
|
|
|
+/******************************** DMA Instances *******************************/
|
|
|
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
|
|
|
+ ((INSTANCE) == DMA1_Channel2) || \
|
|
|
+ ((INSTANCE) == DMA1_Channel3) || \
|
|
|
+ ((INSTANCE) == DMA1_Channel4) || \
|
|
|
+ ((INSTANCE) == DMA1_Channel5))
|
|
|
+/******************************** DMAMUX Instances ****************************/
|
|
|
+#define IS_DMAMUX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMAMUX1)
|
|
|
+
|
|
|
+#define IS_DMAMUX_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
|
|
|
+ ((INSTANCE) == DMAMUX1_RequestGenerator1) || \
|
|
|
+ ((INSTANCE) == DMAMUX1_RequestGenerator2) || \
|
|
|
+ ((INSTANCE) == DMAMUX1_RequestGenerator3))
|
|
|
+
|
|
|
+/******************************* GPIO Instances *******************************/
|
|
|
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
|
|
+ ((INSTANCE) == GPIOB) || \
|
|
|
+ ((INSTANCE) == GPIOC) || \
|
|
|
+ ((INSTANCE) == GPIOD) || \
|
|
|
+ ((INSTANCE) == GPIOF))
|
|
|
+/******************************* GPIO AF Instances ****************************/
|
|
|
+#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
|
|
|
+
|
|
|
+/**************************** GPIO Lock Instances *****************************/
|
|
|
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
|
|
+ ((INSTANCE) == GPIOB) || \
|
|
|
+ ((INSTANCE) == GPIOC))
|
|
|
+
|
|
|
+/******************************** I2C Instances *******************************/
|
|
|
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
|
|
|
+ ((INSTANCE) == I2C2))
|
|
|
+
|
|
|
+
|
|
|
+/****************************** RTC Instances *********************************/
|
|
|
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
|
|
|
+
|
|
|
+/****************************** SMBUS Instances *******************************/
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+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
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+
|
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+/****************************** WAKEUP_FROMSTOP Instances *******************************/
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+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
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+
|
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+/******************************** SPI Instances *******************************/
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+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
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+ ((INSTANCE) == SPI2))
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+
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+/******************************** SPI Instances *******************************/
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+#define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
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+
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+
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+/****************** TIM Instances : All supported instances *******************/
|
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+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
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+ ((INSTANCE) == TIM3) || \
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+ ((INSTANCE) == TIM14) || \
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+ ((INSTANCE) == TIM16) || \
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+ ((INSTANCE) == TIM17))
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+
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+/****************** TIM Instances : supporting 32 bits counter ****************/
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+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (0)
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+
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+/****************** TIM Instances : supporting the break function *************/
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+#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
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+ ((INSTANCE) == TIM16) || \
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+ ((INSTANCE) == TIM17))
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+
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+/************** TIM Instances : supporting Break source selection *************/
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+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
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+ ((INSTANCE) == TIM16) || \
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+ ((INSTANCE) == TIM17))
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+
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+/****************** TIM Instances : supporting 2 break inputs *****************/
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+#define IS_TIM_BKIN2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
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+
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+/************* TIM Instances : at least 1 capture/compare channel *************/
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+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
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+ ((INSTANCE) == TIM3) || \
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+ ((INSTANCE) == TIM14) || \
|
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+ ((INSTANCE) == TIM16) || \
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+ ((INSTANCE) == TIM17))
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+
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+/************ TIM Instances : at least 2 capture/compare channels *************/
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+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
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+ ((INSTANCE) == TIM3))
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+
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+/************ TIM Instances : at least 3 capture/compare channels *************/
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+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
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+ ((INSTANCE) == TIM3))
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+
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+/************ TIM Instances : at least 4 capture/compare channels *************/
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+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
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+ ((INSTANCE) == TIM3))
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+
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+/****************** TIM Instances : at least 5 capture/compare channels *******/
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|
+#define IS_TIM_CC5_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
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+
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+/****************** TIM Instances : at least 6 capture/compare channels *******/
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+#define IS_TIM_CC6_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
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+
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+/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
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|
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
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+ ((INSTANCE) == TIM16) || \
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+ ((INSTANCE) == TIM17))
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+
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|
+/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
|
|
|
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
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|
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+ ((INSTANCE) == TIM3) || \
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|
+ ((INSTANCE) == TIM16) || \
|
|
|
+ ((INSTANCE) == TIM17))
|
|
|
+
|
|
|
+/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
|
|
|
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
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|
|
+ ((INSTANCE) == TIM3) || \
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|
+ ((INSTANCE) == TIM14) || \
|
|
|
+ ((INSTANCE) == TIM16) || \
|
|
|
+ ((INSTANCE) == TIM17))
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+
|
|
|
+/******************** TIM Instances : DMA burst feature ***********************/
|
|
|
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
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|
|
+ ((INSTANCE) == TIM3) || \
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|
|
+ ((INSTANCE) == TIM16) || \
|
|
|
+ ((INSTANCE) == TIM17))
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|
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+
|
|
|
+/******************* TIM Instances : output(s) available **********************/
|
|
|
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
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|
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+ ((((INSTANCE) == TIM1) && \
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+ (((CHANNEL) == TIM_CHANNEL_1) || \
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+ ((CHANNEL) == TIM_CHANNEL_2) || \
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+ ((CHANNEL) == TIM_CHANNEL_3) || \
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|
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+ ((CHANNEL) == TIM_CHANNEL_4) || \
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|
|
+ ((CHANNEL) == TIM_CHANNEL_5) || \
|
|
|
+ ((CHANNEL) == TIM_CHANNEL_6))) \
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|
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+ || \
|
|
|
+ (((INSTANCE) == TIM3) && \
|
|
|
+ (((CHANNEL) == TIM_CHANNEL_1) || \
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|
|
+ ((CHANNEL) == TIM_CHANNEL_2) || \
|
|
|
+ ((CHANNEL) == TIM_CHANNEL_3) || \
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|
|
+ ((CHANNEL) == TIM_CHANNEL_4))) \
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|
|
+ || \
|
|
|
+ (((INSTANCE) == TIM14) && \
|
|
|
+ (((CHANNEL) == TIM_CHANNEL_1))) \
|
|
|
+ || \
|
|
|
+ (((INSTANCE) == TIM16) && \
|
|
|
+ (((CHANNEL) == TIM_CHANNEL_1))) \
|
|
|
+ || \
|
|
|
+ (((INSTANCE) == TIM17) && \
|
|
|
+ (((CHANNEL) == TIM_CHANNEL_1))))
|
|
|
+/****************** TIM Instances : supporting complementary output(s) ********/
|
|
|
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
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|
|
+ ((((INSTANCE) == TIM1) && \
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|
|
+ (((CHANNEL) == TIM_CHANNEL_1) || \
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|
|
+ ((CHANNEL) == TIM_CHANNEL_2) || \
|
|
|
+ ((CHANNEL) == TIM_CHANNEL_3))) \
|
|
|
+ || \
|
|
|
+ (((INSTANCE) == TIM16) && \
|
|
|
+ ((CHANNEL) == TIM_CHANNEL_1)) \
|
|
|
+ || \
|
|
|
+ (((INSTANCE) == TIM17) && \
|
|
|
+ ((CHANNEL) == TIM_CHANNEL_1)))
|
|
|
+
|
|
|
+/****************** TIM Instances : supporting clock division *****************/
|
|
|
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
+ ((INSTANCE) == TIM3) || \
|
|
|
+ ((INSTANCE) == TIM14) || \
|
|
|
+ ((INSTANCE) == TIM16) || \
|
|
|
+ ((INSTANCE) == TIM17))
|
|
|
+
|
|
|
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
|
|
|
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
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|
|
+ ((INSTANCE) == TIM3))
|
|
|
+
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|
|
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
|
|
|
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
+ ((INSTANCE) == TIM3))
|
|
|
+
|
|
|
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
|
|
|
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
+ ((INSTANCE) == TIM3))
|
|
|
+
|
|
|
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
|
|
|
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
+ ((INSTANCE) == TIM3))
|
|
|
+
|
|
|
+/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
|
|
|
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
|
|
|
+
|
|
|
+/****************** TIM Instances : supporting commutation event generation ***/
|
|
|
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
+ ((INSTANCE) == TIM16) || \
|
|
|
+ ((INSTANCE) == TIM17))
|
|
|
+
|
|
|
+/****************** TIM Instances : supporting counting mode selection ********/
|
|
|
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
+ ((INSTANCE) == TIM3))
|
|
|
+
|
|
|
+/****************** TIM Instances : supporting encoder interface **************/
|
|
|
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
+ ((INSTANCE) == TIM3))
|
|
|
+
|
|
|
+/****************** TIM Instances : supporting Hall sensor interface **********/
|
|
|
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
+ ((INSTANCE) == TIM3))
|
|
|
+
|
|
|
+/**************** TIM Instances : external trigger input available ************/
|
|
|
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
+ ((INSTANCE) == TIM3))
|
|
|
+
|
|
|
+/************* TIM Instances : supporting ETR source selection ***************/
|
|
|
+#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
+ ((INSTANCE) == TIM3))
|
|
|
+
|
|
|
+/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
|
|
|
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
+ ((INSTANCE) == TIM3))
|
|
|
+
|
|
|
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
|
|
|
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
+ ((INSTANCE) == TIM3))
|
|
|
+
|
|
|
+/****************** TIM Instances : supporting OCxREF clear *******************/
|
|
|
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
+ ((INSTANCE) == TIM3))
|
|
|
+
|
|
|
+/****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/
|
|
|
+#define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
+ ((INSTANCE) == TIM3))
|
|
|
+
|
|
|
+/****************** TIM Instances : remapping capability **********************/
|
|
|
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
|
|
|
+
|
|
|
+/****************** TIM Instances : supporting repetition counter *************/
|
|
|
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
+ ((INSTANCE) == TIM16) || \
|
|
|
+ ((INSTANCE) == TIM17))
|
|
|
+
|
|
|
+/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
|
|
|
+#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
|
|
|
+
|
|
|
+/******************* TIM Instances : Timer input XOR function *****************/
|
|
|
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
+ ((INSTANCE) == TIM3))
|
|
|
+
|
|
|
+/******************* TIM Instances : Timer input selection ********************/
|
|
|
+#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
+ ((INSTANCE) == TIM3) || \
|
|
|
+ ((INSTANCE) == TIM14) || \
|
|
|
+ ((INSTANCE) == TIM16) || \
|
|
|
+ ((INSTANCE) == TIM17))
|
|
|
+
|
|
|
+/************ TIM Instances : Advanced timers ********************************/
|
|
|
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
|
|
|
+
|
|
|
+/******************** UART Instances : Asynchronous mode **********************/
|
|
|
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
|
|
+ ((INSTANCE) == USART2))
|
|
|
+
|
|
|
+/******************** USART Instances : Synchronous mode **********************/
|
|
|
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
|
|
+ ((INSTANCE) == USART2))
|
|
|
+/****************** UART Instances : Hardware Flow control ********************/
|
|
|
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
|
|
+ ((INSTANCE) == USART2))
|
|
|
+
|
|
|
+/********************* USART Instances : Smard card mode ***********************/
|
|
|
+#define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
|
|
|
+/****************** UART Instances : Auto Baud Rate detection ****************/
|
|
|
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
|
|
|
+/******************** UART Instances : Half-Duplex mode **********************/
|
|
|
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
|
|
+ ((INSTANCE) == USART2))
|
|
|
+
|
|
|
+/******************** UART Instances : LIN mode **********************/
|
|
|
+#define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
|
|
|
+/******************** UART Instances : Wake-up from Stop mode **********************/
|
|
|
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
|
|
|
+
|
|
|
+/****************** UART Instances : Driver Enable *****************/
|
|
|
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
|
|
+ ((INSTANCE) == USART2))
|
|
|
+
|
|
|
+/****************** UART Instances : SPI Slave selection mode ***************/
|
|
|
+#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
|
|
+ ((INSTANCE) == USART2))
|
|
|
+
|
|
|
+/****************** UART Instances : Driver Enable *****************/
|
|
|
+#define IS_UART_FIFO_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
|
|
|
+
|
|
|
+/*********************** UART Instances : IRDA mode ***************************/
|
|
|
+#define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
|
|
|
+
|
|
|
+#define IS_LPUART_INSTANCE(INSTANCE) (0U)
|
|
|
+
|
|
|
+/****************************** IWDG Instances ********************************/
|
|
|
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
|
|
|
+
|
|
|
+/****************************** WWDG Instances ********************************/
|
|
|
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
|
|
|
+
|
|
|
+
|
|
|
+/**
|
|
|
+ * @}
|
|
|
+ */
|
|
|
+
|
|
|
+ /**
|
|
|
+ * @}
|
|
|
+ */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @}
|
|
|
+ */
|
|
|
+
|
|
|
+#ifdef __cplusplus
|
|
|
+}
|
|
|
+#endif /* __cplusplus */
|
|
|
+
|
|
|
+#endif /* STM32G030xx_H */
|
|
|
+
|
|
|
+/**
|
|
|
+ * @}
|
|
|
+ */
|
|
|
+
|
|
|
+ /**
|
|
|
+ * @}
|
|
|
+ */
|
|
|
+
|
|
|
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
Vladimir N. Shilov
8 tháng trước cách đây