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@@ -44,10 +44,6 @@ void Board_Init(void)
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/* Initialize all configured peripherals */
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/* Initialize all configured peripherals */
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GPIO_Init();
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GPIO_Init();
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- //GPIO_SetPinMode(GPIOA, GPIO_PIN_8, GPIO_MODE_OUT);
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- //GPIO_SetPinOutputType(GPIOA, GPIO_PIN_8, GPIO_OTYPE_PP);
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- //GPIO_SetPinSpeed(GPIOA, GPIO_PIN_8, GPIO_OSPEED_VH);
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- //GPIO_SetPinPull(GPIOA, GPIO_PIN_8, GPIO_PUPDR_NO);
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ADC_Init();
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ADC_Init();
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@@ -97,6 +93,12 @@ static void GPIO_Init(void)
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GPIO_SetPinSpeed(Servo_1_Port, (Servo_1_Pin|Servo_2_Pin), GPIO_OSPEED_LW);
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GPIO_SetPinSpeed(Servo_1_Port, (Servo_1_Pin|Servo_2_Pin), GPIO_OSPEED_LW);
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GPIO_SetPinMode(Servo_1_Port, (Servo_1_Pin|Servo_2_Pin), GPIO_MODE_AFF);
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GPIO_SetPinMode(Servo_1_Port, (Servo_1_Pin|Servo_2_Pin), GPIO_MODE_AFF);
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+ GPIO_SetAFPin_0_7(GPIOB, GPIO_PIN_3, GPIO_AF_1);
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+ GPIO_SetPinOutputType(GPIOB, GPIO_PIN_3, GPIO_OTYPE_PP);
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+ GPIO_SetPinPull(GPIOB, GPIO_PIN_3, GPIO_PUPDR_NO);
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+ GPIO_SetPinSpeed(GPIOB, GPIO_PIN_3, GPIO_OSPEED_LW);
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+ GPIO_SetPinMode(GPIOB, GPIO_PIN_3, GPIO_MODE_AFF);
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+
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/* Photo_Pin: analog in, pull none */
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/* Photo_Pin: analog in, pull none */
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GPIO_SetPinPull(Photo_Port, Photo_Pin, GPIO_PUPDR_NO);
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GPIO_SetPinPull(Photo_Port, Photo_Pin, GPIO_PUPDR_NO);
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GPIO_SetPinMode(Photo_Port, Photo_Pin, GPIO_MODE_ANL);
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GPIO_SetPinMode(Photo_Port, Photo_Pin, GPIO_MODE_ANL);
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@@ -134,16 +136,16 @@ static void ADC_Init(void)
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ADC1->ISR |= ADC_ISR_CCRDY;
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ADC1->ISR |= ADC_ISR_CCRDY;
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/* External trigger - Tim3 */
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/* External trigger - Tim3 */
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- //ADC1->CFGR1 |= (ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_CFGR1_EXTEN_0 | ADC_CFGR1_OVRMOD);
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- ADC1->CFGR1 = ADC_CFGR1_OVRMOD;
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+ //ADC1->CFGR1 |= (ADC_CFGR1_EXTEN_0 | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_CFGR1_OVRMOD);
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+ ADC1->CFGR1 = (ADC_CFGR1_EXTEN_0 |ADC_CFGR1_OVRMOD);
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- /* Enable ADC internal voltage regulator */
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- ADC1->CR |= ADC_CR_ADVREGEN; // ???
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+ /* Enable ADC internal voltage regulator */
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+ ADC1->CR |= ADC_CR_ADVREGEN; // ???
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/** Configure Regular Channel */
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/** Configure Regular Channel */
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ADC1->CHSELR = ADC_CHSELR_CHSEL11;
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ADC1->CHSELR = ADC_CHSELR_CHSEL11;
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- /* Poll for ADC channel configuration ready */
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+ /* Poll for ADC channel configuration ready */
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while ((ADC1->ISR & ADC_ISR_CCRDY) == 0) {};
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while ((ADC1->ISR & ADC_ISR_CCRDY) == 0) {};
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/* Clear flag ADC channel configuration ready */
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/* Clear flag ADC channel configuration ready */
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ADC1->ISR |= ADC_ISR_CCRDY;
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ADC1->ISR |= ADC_ISR_CCRDY;
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@@ -171,25 +173,30 @@ static void ADC_Init(void)
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static void TIM1_Init(void)
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static void TIM1_Init(void)
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{
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{
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/* TIM1 interrupt Init */
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/* TIM1 interrupt Init */
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- NVIC_SetPriority(TIM1_BRK_UP_TRG_COM_IRQn, 0);
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- NVIC_EnableIRQ(TIM1_BRK_UP_TRG_COM_IRQn);
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+ //NVIC_SetPriority(TIM1_BRK_UP_TRG_COM_IRQn, 0);
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+ //NVIC_EnableIRQ(TIM1_BRK_UP_TRG_COM_IRQn);
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/* target clock */
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/* target clock */
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TIM1->PSC = TIM1_PSC; // prescaler
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TIM1->PSC = TIM1_PSC; // prescaler
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TIM1->ARR = TIM1_ARR; // auto reload value
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TIM1->ARR = TIM1_ARR; // auto reload value
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TIM1->CR1 = TIM_CR1_ARPE;
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TIM1->CR1 = TIM_CR1_ARPE;
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// initial pwm value
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// initial pwm value
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TIM1->CCR1 = SERVO_INIT_VAL;
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TIM1->CCR1 = SERVO_INIT_VAL;
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+ TIM1->CCR2 = SERVO_INIT_VAL;
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TIM1->CCR4 = SERVO_INIT_VAL;
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TIM1->CCR4 = SERVO_INIT_VAL;
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// pwm mode 1 for chanels
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// pwm mode 1 for chanels
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TIM1->CCMR1 = (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1PE);
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TIM1->CCMR1 = (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1PE);
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+ TIM1->CCMR1 |= (TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2 | TIM_CCMR1_OC2PE);
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TIM1->CCMR2 = (TIM_CCMR2_OC4M_1 | TIM_CCMR2_OC4M_2 | TIM_CCMR2_OC4PE);
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TIM1->CCMR2 = (TIM_CCMR2_OC4M_1 | TIM_CCMR2_OC4M_2 | TIM_CCMR2_OC4PE);
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//TIM1->SR |= TIM_SR_UIF;
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//TIM1->SR |= TIM_SR_UIF;
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TIM1->BDTR = TIM_BDTR_MOE; // enable main output
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TIM1->BDTR = TIM_BDTR_MOE; // enable main output
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TIM1->EGR = TIM_EGR_UG; // force timer update
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TIM1->EGR = TIM_EGR_UG; // force timer update
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/* TIM1 CC_EnableChannel */
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/* TIM1 CC_EnableChannel */
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TIM1->CCER = (TIM_CCER_CC1E | TIM_CCER_CC1P | TIM_CCER_CC4E | TIM_CCER_CC4P);
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TIM1->CCER = (TIM_CCER_CC1E | TIM_CCER_CC1P | TIM_CCER_CC4E | TIM_CCER_CC4P);
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+ TIM1->CCER |= (TIM_CCER_CC2E | TIM_CCER_CC2P);
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+ /* Set the trigger output 2 (TRGO2) used for ADC synchronization */
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+ TIM1->CR2 |= TIM_CR2_MMS2_1; // update event
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/* Enable interrupts */
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/* Enable interrupts */
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- TIM1->DIER = TIM_DIER_UIE;
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+ //TIM1->DIER = TIM_DIER_UIE;
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/* TIM_EnableCounter */
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/* TIM_EnableCounter */
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TIM1->CR1 |= TIM_CR1_CEN;
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TIM1->CR1 |= TIM_CR1_CEN;
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}
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}
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@@ -204,11 +211,11 @@ static void TIM3_Init(void)
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/* target clock */
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/* target clock */
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TIM3->PSC = TIM3_PSC; // prescaler
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TIM3->PSC = TIM3_PSC; // prescaler
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TIM3->ARR = TIM3_ARR; // auto reload value
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TIM3->ARR = TIM3_ARR; // auto reload value
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- TIM3->CR1 = TIM_CR1_ARPE | TIM_CR1_DIR;
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+ TIM3->CR1 = (TIM_CR1_ARPE | TIM_CR1_DIR);
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// launch timer
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// launch timer
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- TIM3->EGR = TIM_EGR_UG; // force timer update
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+ TIM3->EGR = TIM_EGR_TG | TIM_EGR_UG; // force timer update
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/* Set the trigger output 2 (TRGO2) used for ADC synchronization */
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/* Set the trigger output 2 (TRGO2) used for ADC synchronization */
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- TIM3->CR2 |= TIM_CR2_MMS2_2; // update event
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+ TIM3->CR2 |= TIM_CR2_MMS2_1; // update event
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/* TIM3 enable */
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/* TIM3 enable */
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TIM3->CR1 |= TIM_CR1_CEN;
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TIM3->CR1 |= TIM_CR1_CEN;
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}
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}
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