123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290 |
- #include "stm32g0xx.h"
- #if !defined (HSE_VALUE)
- #define HSE_VALUE (8000000UL)
- #endif
- #if !defined (HSI_VALUE)
- #define HSI_VALUE (16000000UL)
- #endif
- #if !defined (LSI_VALUE)
- #define LSI_VALUE (32000UL)
- #endif
- #if !defined (LSE_VALUE)
- #define LSE_VALUE (32768UL)
- #endif
- #define VECT_TAB_OFFSET 0x0U
-
- uint32_t SystemCoreClock = 16000000UL;
- const uint32_t AHBPrescTable[16UL] = {0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL, 6UL, 7UL, 8UL, 9UL};
- const uint32_t APBPrescTable[8UL] = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
- void SystemInit(void)
- {
-
- #ifdef VECT_TAB_SRAM
- SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET;
- #else
- SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET;
- #endif
- }
- void SystemCoreClockUpdate(void)
- {
- uint32_t tmp;
- uint32_t pllvco;
- uint32_t pllr;
- uint32_t pllsource;
- uint32_t pllm;
- uint32_t hsidiv;
-
- switch (RCC->CFGR & RCC_CFGR_SWS)
- {
- case RCC_CFGR_SWS_0:
- SystemCoreClock = HSE_VALUE;
- break;
- case (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0):
- SystemCoreClock = LSI_VALUE;
- break;
- case RCC_CFGR_SWS_2:
- SystemCoreClock = LSE_VALUE;
- break;
- case RCC_CFGR_SWS_1:
-
- pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
- pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL;
- if(pllsource == 0x03UL)
- {
- pllvco = (HSE_VALUE / pllm);
- }
- else
- {
- pllvco = (HSI_VALUE / pllm);
- }
- pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
- pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
- SystemCoreClock = pllvco/pllr;
- break;
-
- case 0x00000000U:
- default:
- hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV))>> RCC_CR_HSIDIV_Pos));
- SystemCoreClock = (HSI_VALUE/hsidiv);
- break;
- }
-
-
- tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
-
- SystemCoreClock >>= tmp;
- }
|