<?xml version="1.0" encoding="utf-8" standalone="no"?> <!-- Copyright (c) 2020 STMicroelectronics. SPDX-License-Identifier: Apache-2.0 Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. --> <device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> <name>STM32G030</name> <version>1.2</version> <description>STM32G030</description> <cpu> <name>CM0</name> <revision>r0p1</revision> <endian>little</endian> <mpuPresent>true</mpuPresent> <fpuPresent>false</fpuPresent> <nvicPrioBits>4</nvicPrioBits> <vendorSystickConfig>false</vendorSystickConfig> </cpu> <addressUnitBits>8</addressUnitBits> <width>32</width> <size>0x20</size> <resetValue>0x0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <peripherals> <peripheral> <name>IWDG</name> <description>Independent watchdog</description> <groupName>IWDG</groupName> <baseAddress>0x40003000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>KR</name> <displayName>KR</displayName> <description>Key register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>KEY</name> <description>Key value (write only, read 0x0000)</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>PR</name> <displayName>PR</displayName> <description>Prescaler register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PR</name> <description>Prescaler divider</description> <bitOffset>0</bitOffset> <bitWidth>3</bitWidth> </field> </fields> </register> <register> <name>RLR</name> <displayName>RLR</displayName> <description>Reload register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000FFF</resetValue> <fields> <field> <name>RL</name> <description>Watchdog counter reload value</description> <bitOffset>0</bitOffset> <bitWidth>12</bitWidth> </field> </fields> </register> <register> <name>SR</name> <displayName>SR</displayName> <description>Status register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>WVU</name> <description>Watchdog counter window value update</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RVU</name> <description>Watchdog counter reload value update</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PVU</name> <description>Watchdog prescaler value update</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>WINR</name> <displayName>WINR</displayName> <description>Window register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000FFF</resetValue> <fields> <field> <name>WIN</name> <description>Watchdog counter window value</description> <bitOffset>0</bitOffset> <bitWidth>12</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>WWDG</name> <description>System window watchdog</description> <groupName>WWDG</groupName> <baseAddress>0x40002C00</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>WWDG</name> <description>Window watchdog interrupt</description> <value>0</value> </interrupt> <registers> <register> <name>CR</name> <displayName>CR</displayName> <description>Control register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000007F</resetValue> <fields> <field> <name>WDGA</name> <description>Activation bit</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>T</name> <description>7-bit counter (MSB to LSB)</description> <bitOffset>0</bitOffset> <bitWidth>7</bitWidth> </field> </fields> </register> <register> <name>CFR</name> <displayName>CFR</displayName> <description>Configuration register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000007F</resetValue> <fields> <field> <name>WDGTB</name> <description>Timer base</description> <bitOffset>11</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>EWI</name> <description>Early wakeup interrupt</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>W</name> <description>7-bit window value</description> <bitOffset>0</bitOffset> <bitWidth>7</bitWidth> </field> </fields> </register> <register> <name>SR</name> <displayName>SR</displayName> <description>Status register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>EWIF</name> <description>Early wakeup interrupt flag</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>FLASH</name> <description>Flash</description> <groupName>Flash</groupName> <baseAddress>0x40022000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>FLASH</name> <description>Flash global interrupt</description> <value>3</value> </interrupt> <registers> <register> <name>ACR</name> <displayName>ACR</displayName> <description>Access control register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000600</resetValue> <fields> <field> <name>LATENCY</name> <description>Latency</description> <bitOffset>0</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>PRFTEN</name> <description>Prefetch enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ICEN</name> <description>Instruction cache enable</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ICRST</name> <description>Instruction cache reset</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EMPTY</name> <description>Flash User area empty</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_SWEN</name> <description>Debug access software enable</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>KEYR</name> <displayName>KEYR</displayName> <description>Flash key register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>KEYR</name> <description>KEYR</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>OPTKEYR</name> <displayName>OPTKEYR</displayName> <description>Option byte key register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OPTKEYR</name> <description>Option byte key</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>SR</name> <displayName>SR</displayName> <description>Status register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>EOP</name> <description>End of operation</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OPERR</name> <description>Operation error</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PROGERR</name> <description>Programming error</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WRPERR</name> <description>Write protected error</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PGAERR</name> <description>Programming alignment error</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SIZERR</name> <description>Size error</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PGSERR</name> <description>Programming sequence error</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MISERR</name> <description>Fast programming data miss error</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FASTERR</name> <description>Fast programming error</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RDERR</name> <description>PCROP read error</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OPTVERR</name> <description>Option and Engineering bits loading validity error</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BSY</name> <description>Busy</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CFGBSY</name> <description>Programming or erase configuration busy.</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CR</name> <displayName>CR</displayName> <description>Flash control register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0xC0000000</resetValue> <fields> <field> <name>PG</name> <description>Programming</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PER</name> <description>Page erase</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MER</name> <description>Mass erase</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PNB</name> <description>Page number</description> <bitOffset>3</bitOffset> <bitWidth>6</bitWidth> </field> <field> <name>STRT</name> <description>Start</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OPTSTRT</name> <description>Options modification start</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FSTPG</name> <description>Fast programming</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EOPIE</name> <description>End of operation interrupt enable</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ERRIE</name> <description>Error interrupt enable</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RDERRIE</name> <description>PCROP read error interrupt enable</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OBL_LAUNCH</name> <description>Force the option byte loading</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SEC_PROT</name> <description>Securable memory area protection enable</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OPTLOCK</name> <description>Options Lock</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LOCK</name> <description>FLASH_CR Lock</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ECCR</name> <displayName>ECCR</displayName> <description>Flash ECC register</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <resetValue>0x00000000</resetValue> <fields> <field> <name>ADDR_ECC</name> <description>ECC fail address</description> <bitOffset>0</bitOffset> <bitWidth>14</bitWidth> <access>read-only</access> </field> <field> <name>SYSF_ECC</name> <description>ECC fail for Corrected ECC Error or Double ECC Error in info block</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>ECCIE</name> <description>ECC correction interrupt enable</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ECCC</name> <description>ECC correction</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ECCD</name> <description>ECC detection</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>OPTR</name> <displayName>OPTR</displayName> <description>Flash option register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0xF0000000</resetValue> <fields> <field> <name>RDP</name> <description>Read protection level</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>BOREN</name> <description>BOR reset Level</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BORF_LEV</name> <description>These bits contain the VDD supply level threshold that activates the reset</description> <bitOffset>9</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>BORR_LEV</name> <description>These bits contain the VDD supply level threshold that releases the reset.</description> <bitOffset>11</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>nRST_STOP</name> <description>nRST_STOP</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>nRST_STDBY</name> <description>nRST_STDBY</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>nRSTS_HDW</name> <description>nRSTS_HDW</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDWG_SW</name> <description>Independent watchdog selection</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IWDG_STOP</name> <description>Independent watchdog counter freeze in Stop mode</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IWDG_STDBY</name> <description>Independent watchdog counter freeze in Standby mode</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WWDG_SW</name> <description>Window watchdog selection</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RAM_PARITY_CHECK</name> <description>SRAM parity check control</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>nBOOT_SEL</name> <description>nBOOT_SEL</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>nBOOT1</name> <description>Boot configuration</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>nBOOT0</name> <description>nBOOT0 option bit</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NRST_MODE</name> <description>NRST_MODE</description> <bitOffset>27</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>IRHEN</name> <description>Internal reset holder enable bit</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>PCROP1ASR</name> <displayName>PCROP1ASR</displayName> <description>Flash PCROP zone A Start address register</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0xF0000000</resetValue> <fields> <field> <name>PCROP1A_STRT</name> <description>PCROP1A area start offset</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>PCROP1AER</name> <displayName>PCROP1AER</displayName> <description>Flash PCROP zone A End address register</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0xF0000000</resetValue> <fields> <field> <name>PCROP1A_END</name> <description>PCROP1A area end offset</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>PCROP_RDP</name> <description>PCROP area preserved when RDP level decreased</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>WRP1AR</name> <displayName>WRP1AR</displayName> <description>Flash WRP area A address register</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0xF0000000</resetValue> <fields> <field> <name>WRP1A_STRT</name> <description>WRP area A start offset</description> <bitOffset>0</bitOffset> <bitWidth>6</bitWidth> </field> <field> <name>WRP1A_END</name> <description>WRP area A end offset</description> <bitOffset>16</bitOffset> <bitWidth>6</bitWidth> </field> </fields> </register> <register> <name>WRP1BR</name> <displayName>WRP1BR</displayName> <description>Flash WRP area B address register</description> <addressOffset>0x30</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0xF0000000</resetValue> <fields> <field> <name>WRP1B_STRT</name> <description>WRP area B start offset</description> <bitOffset>0</bitOffset> <bitWidth>6</bitWidth> </field> <field> <name>WRP1B_END</name> <description>WRP area B end offset</description> <bitOffset>16</bitOffset> <bitWidth>6</bitWidth> </field> </fields> </register> <register> <name>PCROP1BSR</name> <displayName>PCROP1BSR</displayName> <description>Flash PCROP zone B Start address register</description> <addressOffset>0x34</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0xF0000000</resetValue> <fields> <field> <name>PCROP1B_STRT</name> <description>PCROP1B area start offset</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>PCROP1BER</name> <displayName>PCROP1BER</displayName> <description>Flash PCROP zone B End address register</description> <addressOffset>0x38</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0xF0000000</resetValue> <fields> <field> <name>PCROP1B_END</name> <description>PCROP1B area end offset</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>SECR</name> <displayName>SECR</displayName> <description>Flash Security register</description> <addressOffset>0x80</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0xF0000000</resetValue> <fields> <field> <name>SEC_SIZE</name> <description>Securable memory area size</description> <bitOffset>0</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>BOOT_LOCK</name> <description>used to force boot from user area</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>RCC</name> <description>Reset and clock control</description> <groupName>RCC</groupName> <baseAddress>0x40021000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>RCC</name> <description>RCC global interrupt</description> <value>4</value> </interrupt> <registers> <register> <name>CR</name> <displayName>CR</displayName> <description>Clock control register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000063</resetValue> <fields> <field> <name>HSION</name> <description>HSI16 clock enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HSIKERON</name> <description>HSI16 always enable for peripheral kernels</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HSIRDY</name> <description>HSI16 clock ready flag</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HSIDIV</name> <description>HSI16 clock division factor</description> <bitOffset>11</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>HSEON</name> <description>HSE clock enable</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HSERDY</name> <description>HSE clock ready flag</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HSEBYP</name> <description>HSE crystal oscillator bypass</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CSSON</name> <description>Clock security system enable</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLON</name> <description>PLL enable</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLRDY</name> <description>PLL clock ready flag</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ICSCR</name> <displayName>ICSCR</displayName> <description>Internal clock sources calibration register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <resetValue>0x10000000</resetValue> <fields> <field> <name>HSICAL</name> <description>HSI16 clock calibration</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> <access>read-only</access> </field> <field> <name>HSITRIM</name> <description>HSI16 clock trimming</description> <bitOffset>8</bitOffset> <bitWidth>7</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>CFGR</name> <displayName>CFGR</displayName> <description>Clock configuration register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <resetValue>0x00000000</resetValue> <fields> <field> <name>MCOPRE</name> <description>Microcontroller clock output prescaler</description> <bitOffset>28</bitOffset> <bitWidth>3</bitWidth> <access>read-only</access> </field> <field> <name>MCOSEL</name> <description>Microcontroller clock output</description> <bitOffset>24</bitOffset> <bitWidth>3</bitWidth> <access>read-write</access> </field> <field> <name>PPRE</name> <description>APB prescaler</description> <bitOffset>12</bitOffset> <bitWidth>3</bitWidth> <access>read-write</access> </field> <field> <name>HPRE</name> <description>AHB prescaler</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> <name>SWS</name> <description>System clock switch status</description> <bitOffset>3</bitOffset> <bitWidth>3</bitWidth> <access>read-only</access> </field> <field> <name>SW</name> <description>System clock switch</description> <bitOffset>0</bitOffset> <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>PLLSYSCFGR</name> <displayName>PLLSYSCFGR</displayName> <description>PLL configuration register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00001000</resetValue> <fields> <field> <name>PLLSRC</name> <description>PLL input clock source</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PLLM</name> <description>Division factor M of the PLL input clock divider</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>PLLN</name> <description>PLL frequency multiplication factor N</description> <bitOffset>8</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>PLLPEN</name> <description>PLLPCLK clock output enable</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLP</name> <description>PLL VCO division factor P for PLLPCLK clock output</description> <bitOffset>17</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>PLLQEN</name> <description>PLLQCLK clock output enable</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLQ</name> <description>PLL VCO division factor Q for PLLQCLK clock output</description> <bitOffset>25</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>PLLREN</name> <description>PLLRCLK clock output enable</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLR</name> <description>PLL VCO division factor R for PLLRCLK clock output</description> <bitOffset>29</bitOffset> <bitWidth>3</bitWidth> </field> </fields> </register> <register> <name>CIER</name> <displayName>CIER</displayName> <description>Clock interrupt enable register</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>LSIRDYIE</name> <description>LSI ready interrupt enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LSERDYIE</name> <description>LSE ready interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HSIRDYIE</name> <description>HSI ready interrupt enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HSERDYIE</name> <description>HSE ready interrupt enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLSYSRDYIE</name> <description>PLL ready interrupt enable</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CIFR</name> <displayName>CIFR</displayName> <description>Clock interrupt flag register</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>LSIRDYF</name> <description>LSI ready interrupt flag</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LSERDYF</name> <description>LSE ready interrupt flag</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HSIRDYF</name> <description>HSI ready interrupt flag</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HSERDYF</name> <description>HSE ready interrupt flag</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLSYSRDYF</name> <description>PLL ready interrupt flag</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CSSF</name> <description>Clock security system interrupt flag</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LSECSSF</name> <description>LSE Clock security system interrupt flag</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CICR</name> <displayName>CICR</displayName> <description>Clock interrupt clear register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>LSIRDYC</name> <description>LSI ready interrupt clear</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LSERDYC</name> <description>LSE ready interrupt clear</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HSIRDYC</name> <description>HSI ready interrupt clear</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HSERDYC</name> <description>HSE ready interrupt clear</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLSYSRDYC</name> <description>PLL ready interrupt clear</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CSSC</name> <description>Clock security system interrupt clear</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LSECSSC</name> <description>LSE Clock security system interrupt clear</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>AHBRSTR</name> <displayName>AHBRSTR</displayName> <description>AHB peripheral reset register</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DMARST</name> <description>DMA1 reset</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FLASHRST</name> <description>FLITF reset</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CRCRST</name> <description>CRC reset</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>IOPRSTR</name> <displayName>IOPRSTR</displayName> <description>GPIO reset register</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IOPARST</name> <description>I/O port A reset</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IOPBRST</name> <description>I/O port B reset</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IOPCRST</name> <description>I/O port C reset</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IOPDRST</name> <description>I/O port D reset</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IOPFRST</name> <description>I/O port F reset</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>APBRSTR1</name> <displayName>APBRSTR1</displayName> <description>APB peripheral reset register 1</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TIM2RST</name> <description>TIM2 timer reset</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM3RST</name> <description>TIM3 timer reset</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPI2RST</name> <description>SPI2 reset</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>USART2RST</name> <description>USART2 reset</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>I2C1RST</name> <description>I2C1 reset</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>I2C2RST</name> <description>I2C2 reset</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBGRST</name> <description>Debug support reset</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PWRRST</name> <description>Power interface reset</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>APBRSTR2</name> <displayName>APBRSTR2</displayName> <description>APB peripheral reset register 2</description> <addressOffset>0x30</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SYSCFGRST</name> <description>SYSCFG, COMP and VREFBUF reset</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM1RST</name> <description>TIM1 timer reset</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPI1RST</name> <description>SPI1 reset</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>USART1RST</name> <description>USART1 reset</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM14RST</name> <description>TIM14 timer reset</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM16RST</name> <description>TIM16 timer reset</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM17RST</name> <description>TIM17 timer reset</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADCRST</name> <description>ADC reset</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>IOPENR</name> <displayName>IOPENR</displayName> <description>GPIO clock enable register</description> <addressOffset>0x34</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IOPAEN</name> <description>I/O port A clock enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IOPBEN</name> <description>I/O port B clock enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IOPCEN</name> <description>I/O port C clock enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IOPDEN</name> <description>I/O port D clock enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IOPFEN</name> <description>I/O port F clock enable</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>AHBENR</name> <displayName>AHBENR</displayName> <description>AHB peripheral clock enable register</description> <addressOffset>0x38</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DMAEN</name> <description>DMA clock enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FLASHEN</name> <description>Flash memory interface clock enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CRCEN</name> <description>CRC clock enable</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>APBENR1</name> <displayName>APBENR1</displayName> <description>APB peripheral clock enable register 1</description> <addressOffset>0x3C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TIM2EN</name> <description>TIM2 timer clock enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM3EN</name> <description>TIM3 timer clock enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RTCAPBEN</name> <description>RTC APB clock enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WWDGEN</name> <description>WWDG clock enable</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPI2EN</name> <description>SPI2 clock enable</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>USART2EN</name> <description>USART2 clock enable</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>I2C1EN</name> <description>I2C1 clock enable</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>I2C2EN</name> <description>I2C2 clock enable</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBGEN</name> <description>Debug support clock enable</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PWREN</name> <description>Power interface clock enable</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>APBENR2</name> <displayName>APBENR2</displayName> <description>APB peripheral clock enable register 2</description> <addressOffset>0x40</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SYSCFGEN</name> <description>SYSCFG, COMP and VREFBUF clock enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM1EN</name> <description>TIM1 timer clock enable</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPI1EN</name> <description>SPI1 clock enable</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>USART1EN</name> <description>USART1 clock enable</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM14EN</name> <description>TIM14 timer clock enable</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM16EN</name> <description>TIM16 timer clock enable</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM17EN</name> <description>TIM16 timer clock enable</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADCEN</name> <description>ADC clock enable</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>IOPSMENR</name> <displayName>IOPSMENR</displayName> <description>GPIO in Sleep mode clock enable register</description> <addressOffset>0x44</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IOPASMEN</name> <description>I/O port A clock enable during Sleep mode</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IOPBSMEN</name> <description>I/O port B clock enable during Sleep mode</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IOPCSMEN</name> <description>I/O port C clock enable during Sleep mode</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IOPDSMEN</name> <description>I/O port D clock enable during Sleep mode</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IOPFSMEN</name> <description>I/O port F clock enable during Sleep mode</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>AHBSMENR</name> <displayName>AHBSMENR</displayName> <description>AHB peripheral clock enable in Sleep mode register</description> <addressOffset>0x48</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DMASMEN</name> <description>DMA clock enable during Sleep mode</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FLASHSMEN</name> <description>Flash memory interface clock enable during Sleep mode</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SRAMSMEN</name> <description>SRAM clock enable during Sleep mode</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CRCSMEN</name> <description>CRC clock enable during Sleep mode</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>APBSMENR1</name> <displayName>APBSMENR1</displayName> <description>APB peripheral clock enable in Sleep mode register 1</description> <addressOffset>0x4C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TIM2SMEN</name> <description>TIM2 timer clock enable during Sleep mode</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM3SMEN</name> <description>TIM3 timer clock enable during Sleep mode</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RTCAPBSMEN</name> <description>RTC APB clock enable during Sleep mode</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WWDGSMEN</name> <description>WWDG clock enable during Sleep mode</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPI2SMEN</name> <description>SPI2 clock enable during Sleep mode</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>USART2SMEN</name> <description>USART2 clock enable during Sleep mode</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>I2C1SMEN</name> <description>I2C1 clock enable during Sleep mode</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>I2C2SMEN</name> <description>I2C2 clock enable during Sleep mode</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBGSMEN</name> <description>Debug support clock enable during Sleep mode</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PWRSMEN</name> <description>Power interface clock enable during Sleep mode</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>APBSMENR2</name> <displayName>APBSMENR2</displayName> <description>APB peripheral clock enable in Sleep mode register 2</description> <addressOffset>0x50</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SYSCFGSMEN</name> <description>SYSCFG, COMP and VREFBUF clock enable during Sleep mode</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM1SMEN</name> <description>TIM1 timer clock enable during Sleep mode</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPI1SMEN</name> <description>SPI1 clock enable during Sleep mode</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>USART1SMEN</name> <description>USART1 clock enable during Sleep mode</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM14SMEN</name> <description>TIM14 timer clock enable during Sleep mode</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM16SMEN</name> <description>TIM16 timer clock enable during Sleep mode</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM17SMEN</name> <description>TIM16 timer clock enable during Sleep mode</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADCSMEN</name> <description>ADC clock enable during Sleep mode</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CCIPR</name> <displayName>CCIPR</displayName> <description>Peripherals independent clock configuration register</description> <addressOffset>0x54</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>USART1SEL</name> <description>USART1 clock source selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>I2C1SEL</name> <description>I2C1 clock source selection</description> <bitOffset>12</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>I2S2SEL</name> <description>I2S1 clock source selection</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>TIM1SEL</name> <description>TIM1 clock source selection</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RNGSEL</name> <description>RNG clock source selection</description> <bitOffset>26</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>RNGDIV</name> <description>Division factor of RNG clock divider</description> <bitOffset>28</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>ADCSEL</name> <description>ADCs clock source selection</description> <bitOffset>30</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>BDCR</name> <displayName>BDCR</displayName> <description>RTC domain control register</description> <addressOffset>0x5C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>LSEON</name> <description>LSE oscillator enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LSERDY</name> <description>LSE oscillator ready</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LSEBYP</name> <description>LSE oscillator bypass</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LSEDRV</name> <description>LSE oscillator drive capability</description> <bitOffset>3</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>LSECSSON</name> <description>CSS on LSE enable</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LSECSSD</name> <description>CSS on LSE failure Detection</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RTCSEL</name> <description>RTC clock source selection</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>RTCEN</name> <description>RTC clock enable</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BDRST</name> <description>RTC domain software reset</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LSCOEN</name> <description>Low-speed clock output (LSCO) enable</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LSCOSEL</name> <description>Low-speed clock output selection</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CSR</name> <displayName>CSR</displayName> <description>Control/status register</description> <addressOffset>0x60</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>LSION</name> <description>LSI oscillator enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LSIRDY</name> <description>LSI oscillator ready</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RMVF</name> <description>Remove reset flags</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OBLRSTF</name> <description>Option byte loader reset flag</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PINRSTF</name> <description>Pin reset flag</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PWRRSTF</name> <description>BOR or POR/PDR flag</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SFTRSTF</name> <description>Software reset flag</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IWDGRSTF</name> <description>Independent window watchdog reset flag</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WWDGRSTF</name> <description>Window watchdog reset flag</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LPWRRSTF</name> <description>Low-power reset flag</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>PWR</name> <description>Power control</description> <groupName>PWR</groupName> <baseAddress>0x40007000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>CR1</name> <displayName>CR1</displayName> <description>Power control register 1</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000200</resetValue> <fields> <field> <name>LPR</name> <description>Low-power run</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>VOS</name> <description>Voltage scaling range selection</description> <bitOffset>9</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DBP</name> <description>Disable backup domain write protection</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FPD_LPSLP</name> <description>Flash memory powered down during Low-power sleep mode</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FPD_LPRUN</name> <description>Flash memory powered down during Low-power run mode</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FPD_STOP</name> <description>Flash memory powered down during Stop mode</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LPMS</name> <description>Low-power mode selection</description> <bitOffset>0</bitOffset> <bitWidth>3</bitWidth> </field> </fields> </register> <register> <name>CR2</name> <displayName>CR2</displayName> <description>Power control register 2</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PVDE</name> <description>Power voltage detector enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PVDFT</name> <description>Power voltage detector falling threshold selection</description> <bitOffset>1</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>PVDRT</name> <description>Power voltage detector rising threshold selection</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> </fields> </register> <register> <name>CR3</name> <displayName>CR3</displayName> <description>Power control register 3</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0X00008000</resetValue> <fields> <field> <name>EWUP1</name> <description>Enable Wakeup pin WKUP1</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EWUP2</name> <description>Enable Wakeup pin WKUP2</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EWUP4</name> <description>Enable Wakeup pin WKUP4</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EWUP5</name> <description>Enable WKUP5 wakeup pin</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EWUP6</name> <description>Enable WKUP6 wakeup pin</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RRS</name> <description>SRAM retention in Standby mode</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ULPEN</name> <description>Enable the periodical sampling mode for PDR detection</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>APC</name> <description>Apply pull-up and pull-down configuration</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EIWUL</name> <description>Enable internal wakeup line</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CR4</name> <displayName>CR4</displayName> <description>Power control register 4</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>WP1</name> <description>Wakeup pin WKUP1 polarity</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WP2</name> <description>Wakeup pin WKUP2 polarity</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WP4</name> <description>Wakeup pin WKUP4 polarity</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WP5</name> <description>Wakeup pin WKUP5 polarity</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WP6</name> <description>WKUP6 wakeup pin polarity</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>VBE</name> <description>VBAT battery charging enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>VBRS</name> <description>VBAT battery charging resistor selection</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SR1</name> <displayName>SR1</displayName> <description>Power status register 1</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>WUF1</name> <description>Wakeup flag 1</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WUF2</name> <description>Wakeup flag 2</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WUF4</name> <description>Wakeup flag 4</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WUF5</name> <description>Wakeup flag 5</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WUF6</name> <description>Wakeup flag 6</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SBF</name> <description>Standby flag</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WUFI</name> <description>Wakeup flag internal</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SR2</name> <displayName>SR2</displayName> <description>Power status register 2</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PVDO</name> <description>Power voltage detector output</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>VOSF</name> <description>Voltage scaling flag</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>REGLPF</name> <description>Low-power regulator flag</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>REGLPS</name> <description>Low-power regulator started</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FLASH_RDY</name> <description>Flash ready flag</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SCR</name> <displayName>SCR</displayName> <description>Power status clear register</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSBF</name> <description>Clear standby flag</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CWUF6</name> <description>Clear wakeup flag 6</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CWUF5</name> <description>Clear wakeup flag 5</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CWUF4</name> <description>Clear wakeup flag 4</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CWUF2</name> <description>Clear wakeup flag 2</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CWUF1</name> <description>Clear wakeup flag 1</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>PUCRA</name> <displayName>PUCRA</displayName> <description>Power Port A pull-up control register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PU15</name> <description>Port A pull-up bit y (y=0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PU14</name> <description>Port A pull-up bit y (y=0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PU13</name> <description>Port A pull-up bit y (y=0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PU12</name> <description>Port A pull-up bit y (y=0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PU11</name> <description>Port A pull-up bit y (y=0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PU10</name> <description>Port A pull-up bit y (y=0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PU9</name> <description>Port A pull-up bit y (y=0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PU8</name> <description>Port A pull-up bit y (y=0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PU7</name> <description>Port A pull-up bit y (y=0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PU6</name> <description>Port A pull-up bit y (y=0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PU5</name> <description>Port A pull-up bit y (y=0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PU4</name> <description>Port A pull-up bit y (y=0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PU3</name> <description>Port A pull-up bit y (y=0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PU2</name> <description>Port A pull-up bit y (y=0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PU1</name> <description>Port A pull-up bit y (y=0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PU0</name> <description>Port A pull-up bit y (y=0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>PDCRA</name> <displayName>PDCRA</displayName> <description>Power Port A pull-down control register</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PD15</name> <description>Port A pull-down bit y (y=0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD14</name> <description>Port A pull-down bit y (y=0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD13</name> <description>Port A pull-down bit y (y=0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD12</name> <description>Port A pull-down bit y (y=0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD11</name> <description>Port A pull-down bit y (y=0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD10</name> <description>Port A pull-down bit y (y=0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD9</name> <description>Port A pull-down bit y (y=0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD8</name> <description>Port A pull-down bit y (y=0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD7</name> <description>Port A pull-down bit y (y=0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD6</name> <description>Port A pull-down bit y (y=0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD5</name> <description>Port A pull-down bit y (y=0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD4</name> <description>Port A pull-down bit y (y=0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD3</name> <description>Port A pull-down bit y (y=0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD2</name> <description>Port A pull-down bit y (y=0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD1</name> <description>Port A pull-down bit y (y=0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD0</name> <description>Port A pull-down bit y (y=0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>PUCRB</name> <displayName>PUCRB</displayName> <description>Power Port B pull-up control register</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PU15</name> <description>Port B pull-up bit y (y=0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PU14</name> <description>Port B pull-up bit y (y=0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PU13</name> <description>Port B pull-up bit y (y=0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PU12</name> <description>Port B pull-up bit y (y=0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PU11</name> <description>Port B pull-up bit y (y=0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PU10</name> <description>Port B pull-up bit y (y=0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PU9</name> <description>Port B pull-up bit y (y=0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PU8</name> <description>Port B pull-up bit y (y=0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PU7</name> <description>Port B pull-up bit y (y=0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PU6</name> <description>Port B pull-up bit y (y=0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PU5</name> <description>Port B pull-up bit y (y=0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PU4</name> <description>Port B pull-up bit y (y=0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PU3</name> <description>Port B pull-up bit y (y=0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PU2</name> <description>Port B pull-up bit y (y=0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PU1</name> <description>Port B pull-up bit y (y=0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PU0</name> <description>Port B pull-up bit y (y=0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>PDCRB</name> <displayName>PDCRB</displayName> <description>Power Port B pull-down control register</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PD15</name> <description>Port B pull-down bit y (y=0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD14</name> <description>Port B pull-down bit y (y=0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD13</name> <description>Port B pull-down bit y (y=0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD12</name> <description>Port B pull-down bit y (y=0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD11</name> <description>Port B pull-down bit y (y=0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD10</name> <description>Port B pull-down bit y (y=0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD9</name> <description>Port B pull-down bit y (y=0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD8</name> <description>Port B pull-down bit y (y=0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD7</name> <description>Port B pull-down bit y (y=0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD6</name> <description>Port B pull-down bit y (y=0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD5</name> <description>Port B pull-down bit y (y=0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD4</name> <description>Port B pull-down bit y (y=0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD3</name> <description>Port B pull-down bit y (y=0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD2</name> <description>Port B pull-down bit y (y=0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD1</name> <description>Port B pull-down bit y (y=0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD0</name> <description>Port B pull-down bit y (y=0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>PUCRC</name> <displayName>PUCRC</displayName> <description>Power Port C pull-up control register</description> <addressOffset>0x30</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PU15</name> <description>Port C pull-up bit y (y=0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PU14</name> <description>Port C pull-up bit y (y=0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PU13</name> <description>Port C pull-up bit y (y=0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PU7</name> <description>Port C pull-up bit y (y=0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PU6</name> <description>Port C pull-up bit y (y=0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>PDCRC</name> <displayName>PDCRC</displayName> <description>Power Port C pull-down control register</description> <addressOffset>0x34</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PD15</name> <description>Port C pull-down bit y (y=0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD14</name> <description>Port C pull-down bit y (y=0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD13</name> <description>Port C pull-down bit y (y=0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD12</name> <description>Port C pull-down bit y (y=0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD11</name> <description>Port C pull-down bit y (y=0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD10</name> <description>Port C pull-down bit y (y=0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD9</name> <description>Port C pull-down bit y (y=0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD8</name> <description>Port C pull-down bit y (y=0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD7</name> <description>Port C pull-down bit y (y=0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD6</name> <description>Port C pull-down bit y (y=0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD5</name> <description>Port C pull-down bit y (y=0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD4</name> <description>Port C pull-down bit y (y=0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD3</name> <description>Port C pull-down bit y (y=0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD2</name> <description>Port C pull-down bit y (y=0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD1</name> <description>Port C pull-down bit y (y=0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD0</name> <description>Port C pull-down bit y (y=0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>PUCRD</name> <displayName>PUCRD</displayName> <description>Power Port D pull-up control register</description> <addressOffset>0x38</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PU3</name> <description>Port D pull-up bit y (y=0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PU2</name> <description>Port D pull-up bit y (y=0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PU1</name> <description>Port D pull-up bit y (y=0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PU0</name> <description>Port D pull-up bit y (y=0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>PDCRD</name> <displayName>PDCRD</displayName> <description>Power Port D pull-down control register</description> <addressOffset>0x3C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PD9</name> <description>Port D pull-down bit y (y=0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD8</name> <description>Port D pull-down bit y (y=0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD6</name> <description>Port D pull-down bit y (y=0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD5</name> <description>Port D pull-down bit y (y=0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD4</name> <description>Port D pull-down bit y (y=0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD3</name> <description>Port D pull-down bit y (y=0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD2</name> <description>Port D pull-down bit y (y=0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD1</name> <description>Port D pull-down bit y (y=0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD0</name> <description>Port D pull-down bit y (y=0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>PUCRF</name> <displayName>PUCRF</displayName> <description>Power Port F pull-up control register</description> <addressOffset>0x48</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PU2</name> <description>Port F pull-up bit y (y=0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PU1</name> <description>Port F pull-up bit y (y=0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PU0</name> <description>Port F pull-up bit y (y=0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>PDCRF</name> <displayName>PDCRF</displayName> <description>Power Port F pull-down control register</description> <addressOffset>0x4C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PD2</name> <description>Port F pull-down bit y (y=0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD1</name> <description>Port F pull-down bit y (y=0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PD0</name> <description>Port F pull-down bit y (y=0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>DMA</name> <description>DMA controller</description> <groupName>DMA</groupName> <baseAddress>0x40020000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>DMA_Channel1</name> <description>DMA channel 1 interrupt</description> <value>9</value> </interrupt> <interrupt> <name>DMA_Channel2_3</name> <description>DMA channel 2 & 3 interrupts</description> <value>10</value> </interrupt> <registers> <register> <name>ISR</name> <displayName>ISR</displayName> <description>low interrupt status register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>GIF0</name> <description>Channel global interrupt flag</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIF1</name> <description>Channel transfer complete flag</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIF2</name> <description>Channel half transfer flag</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIF3</name> <description>Channel transfer error flag</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GIF4</name> <description>Channel global interrupt flag</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIF5</name> <description>Channel transfer complete flag</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIF6</name> <description>Channel half transfer flag</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIF7</name> <description>Channel transfer error flag</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GIF8</name> <description>Channel global interrupt flag</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIF9</name> <description>Channel transfer complete flag</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIF10</name> <description>Channel half transfer flag</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIF11</name> <description>Channel transfer error flag</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GIF12</name> <description>Channel global interrupt flag</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIF13</name> <description>Channel transfer complete flag</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIF14</name> <description>Channel half transfer flag</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIF15</name> <description>Channel transfer error flag</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GIF16</name> <description>Channel global interrupt flag</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIF17</name> <description>Channel transfer complete flag</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIF18</name> <description>Channel half transfer flag</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIF19</name> <description>Channel transfer error flag</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GIF20</name> <description>Channel global interrupt flag</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIF21</name> <description>Channel transfer complete flag</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIF22</name> <description>Channel half transfer flag</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIF23</name> <description>Channel transfer error flag</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GIF24</name> <description>Channel global interrupt flag</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIF25</name> <description>Channel transfer complete flag</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIF26</name> <description>Channel half transfer flag</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIF27</name> <description>Channel transfer error flag</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>IFCR</name> <displayName>IFCR</displayName> <description>high interrupt status register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CGIF0</name> <description>Channel global interrupt flag</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTCIF1</name> <description>Channel transfer complete flag</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHTIF2</name> <description>Channel half transfer flag</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTEIF3</name> <description>Channel transfer error flag</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CGIF4</name> <description>Channel global interrupt flag</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTCIF5</name> <description>Channel transfer complete flag</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHTIF6</name> <description>Channel half transfer flag</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTEIF7</name> <description>Channel transfer error flag</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CGIF8</name> <description>Channel global interrupt flag</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTCIF9</name> <description>Channel transfer complete flag</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHTIF10</name> <description>Channel half transfer flag</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTEIF11</name> <description>Channel transfer error flag</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CGIF12</name> <description>Channel global interrupt flag</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTCIF13</name> <description>Channel transfer complete flag</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHTIF14</name> <description>Channel half transfer flag</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTEIF15</name> <description>Channel transfer error flag</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CGIF16</name> <description>Channel global interrupt flag</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTCIF17</name> <description>Channel transfer complete flag</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHTIF18</name> <description>Channel half transfer flag</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTEIF19</name> <description>Channel transfer error flag</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CGIF20</name> <description>Channel global interrupt flag</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTCIF21</name> <description>Channel transfer complete flag</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHTIF22</name> <description>Channel half transfer flag</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTEIF23</name> <description>Channel transfer error flag</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CGIF24</name> <description>Channel global interrupt flag</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTCIF25</name> <description>Channel transfer complete flag</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHTIF26</name> <description>Channel half transfer flag</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTEIF27</name> <description>Channel transfer error flag</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CCR1</name> <displayName>CCR1</displayName> <description>DMA channel x configuration register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>EN</name> <description>Channel enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIE</name> <description>Transfer complete interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIE</name> <description>Half transfer interrupt enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIE</name> <description>Transfer error interrupt enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DIR</name> <description>Data transfer direction</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CIRC</name> <description>Circular mode</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PINC</name> <description>Peripheral increment mode</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MINC</name> <description>Memory increment mode</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PSIZE</name> <description>Peripheral size</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MSIZE</name> <description>Memory size</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PL</name> <description>Channel priority level</description> <bitOffset>12</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MEM2MEM</name> <description>Memory to memory mode</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CCR2</name> <displayName>CCR2</displayName> <description>DMA channel x configuration register</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>EN</name> <description>Channel enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIE</name> <description>Transfer complete interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIE</name> <description>Half transfer interrupt enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIE</name> <description>Transfer error interrupt enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DIR</name> <description>Data transfer direction</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CIRC</name> <description>Circular mode</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PINC</name> <description>Peripheral increment mode</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MINC</name> <description>Memory increment mode</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PSIZE</name> <description>Peripheral size</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MSIZE</name> <description>Memory size</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PL</name> <description>Channel priority level</description> <bitOffset>12</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MEM2MEM</name> <description>Memory to memory mode</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CCR3</name> <displayName>CCR3</displayName> <description>DMA channel x configuration register</description> <addressOffset>0x30</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>EN</name> <description>Channel enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIE</name> <description>Transfer complete interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIE</name> <description>Half transfer interrupt enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIE</name> <description>Transfer error interrupt enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DIR</name> <description>Data transfer direction</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CIRC</name> <description>Circular mode</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PINC</name> <description>Peripheral increment mode</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MINC</name> <description>Memory increment mode</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PSIZE</name> <description>Peripheral size</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MSIZE</name> <description>Memory size</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PL</name> <description>Channel priority level</description> <bitOffset>12</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MEM2MEM</name> <description>Memory to memory mode</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CCR4</name> <displayName>CCR4</displayName> <description>DMA channel x configuration register</description> <addressOffset>0x44</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>EN</name> <description>Channel enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIE</name> <description>Transfer complete interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIE</name> <description>Half transfer interrupt enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIE</name> <description>Transfer error interrupt enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DIR</name> <description>Data transfer direction</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CIRC</name> <description>Circular mode</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PINC</name> <description>Peripheral increment mode</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MINC</name> <description>Memory increment mode</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PSIZE</name> <description>Peripheral size</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MSIZE</name> <description>Memory size</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PL</name> <description>Channel priority level</description> <bitOffset>12</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MEM2MEM</name> <description>Memory to memory mode</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CCR5</name> <displayName>CCR5</displayName> <description>DMA channel x configuration register</description> <addressOffset>0x58</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>EN</name> <description>Channel enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIE</name> <description>Transfer complete interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIE</name> <description>Half transfer interrupt enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIE</name> <description>Transfer error interrupt enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DIR</name> <description>Data transfer direction</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CIRC</name> <description>Circular mode</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PINC</name> <description>Peripheral increment mode</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MINC</name> <description>Memory increment mode</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PSIZE</name> <description>Peripheral size</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MSIZE</name> <description>Memory size</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PL</name> <description>Channel priority level</description> <bitOffset>12</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MEM2MEM</name> <description>Memory to memory mode</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CNDTR1</name> <displayName>CNDTR1</displayName> <description>DMA channel x number of data register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>NDT</name> <description>Number of data to transfer</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CNDTR2</name> <displayName>CNDTR2</displayName> <description>DMA channel x number of data register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>NDT</name> <description>Number of data to transfer</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CNDTR3</name> <displayName>CNDTR3</displayName> <description>DMA channel x configuration register</description> <addressOffset>0x34</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>NDT</name> <description>Number of data to transfer</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CNDTR4</name> <displayName>CNDTR4</displayName> <description>DMA channel x configuration register</description> <addressOffset>0x48</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>NDT</name> <description>Number of data to transfer</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CNDTR5</name> <displayName>CNDTR5</displayName> <description>DMA channel x configuration register</description> <addressOffset>0x5C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>NDT</name> <description>Number of data to transfer</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CPAR1</name> <displayName>CPAR1</displayName> <description>DMA channel x peripheral address register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PA</name> <description>Peripheral address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CPAR2</name> <displayName>CPAR2</displayName> <description>DMA channel x peripheral address register</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PA</name> <description>Peripheral address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CPAR3</name> <displayName>CPAR3</displayName> <description>DMA channel x peripheral address register</description> <addressOffset>0x38</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PA</name> <description>Peripheral address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CPAR4</name> <displayName>CPAR4</displayName> <description>DMA channel x peripheral address register</description> <addressOffset>0x4C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PA</name> <description>Peripheral address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CPAR5</name> <displayName>CPAR5</displayName> <description>DMA channel x peripheral address register</description> <addressOffset>0x60</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PA</name> <description>Peripheral address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CMAR1</name> <displayName>CMAR1</displayName> <description>DMA channel x memory address register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MA</name> <description>Memory address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CMAR2</name> <displayName>CMAR2</displayName> <description>DMA channel x memory address register</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MA</name> <description>Memory address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CMAR3</name> <displayName>CMAR3</displayName> <description>DMA channel x memory address register</description> <addressOffset>0x3C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MA</name> <description>Memory address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CMAR4</name> <displayName>CMAR4</displayName> <description>DMA channel x memory address register</description> <addressOffset>0x50</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MA</name> <description>Memory address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CMAR5</name> <displayName>CMAR5</displayName> <description>DMA channel x memory address register</description> <addressOffset>0x64</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MA</name> <description>Memory address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>DMAMUX</name> <description>DMAMUX</description> <groupName>DMAMUX</groupName> <baseAddress>0x40020800</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>DMA_Channel4_5_6_7</name> <description>DMA channel 4, 5, 6 & 7 and DMAMUX</description> <value>11</value> </interrupt> <registers> <register> <name>C0CR</name> <displayName>C0CR</displayName> <description>DMAMux - DMA request line multiplexer channel x control register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DMAREQ_ID</name> <description>Input DMA request line selected</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>SOIE</name> <description>Interrupt enable at synchronization event overrun</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EGE</name> <description>Event generation enable/disable</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SE</name> <description>Synchronous operating mode enable/disable</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPOL</name> <description>Synchronization event type selector Defines the synchronization event on the selected synchronization input:</description> <bitOffset>17</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>NBREQ</name> <description>Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.</description> <bitOffset>19</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>SYNC_ID</name> <description>Synchronization input selected</description> <bitOffset>24</bitOffset> <bitWidth>5</bitWidth> </field> </fields> </register> <register> <name>C1CR</name> <displayName>C1CR</displayName> <description>DMAMux - DMA request line multiplexer channel x control register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DMAREQ_ID</name> <description>Input DMA request line selected</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>SOIE</name> <description>Interrupt enable at synchronization event overrun</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EGE</name> <description>Event generation enable/disable</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SE</name> <description>Synchronous operating mode enable/disable</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPOL</name> <description>Synchronization event type selector Defines the synchronization event on the selected synchronization input:</description> <bitOffset>17</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>NBREQ</name> <description>Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.</description> <bitOffset>19</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>SYNC_ID</name> <description>Synchronization input selected</description> <bitOffset>24</bitOffset> <bitWidth>5</bitWidth> </field> </fields> </register> <register> <name>C2CR</name> <displayName>C2CR</displayName> <description>DMAMux - DMA request line multiplexer channel x control register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DMAREQ_ID</name> <description>Input DMA request line selected</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>SOIE</name> <description>Interrupt enable at synchronization event overrun</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EGE</name> <description>Event generation enable/disable</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SE</name> <description>Synchronous operating mode enable/disable</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPOL</name> <description>Synchronization event type selector Defines the synchronization event on the selected synchronization input:</description> <bitOffset>17</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>NBREQ</name> <description>Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.</description> <bitOffset>19</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>SYNC_ID</name> <description>Synchronization input selected</description> <bitOffset>24</bitOffset> <bitWidth>5</bitWidth> </field> </fields> </register> <register> <name>C3CR</name> <displayName>C3CR</displayName> <description>DMAMux - DMA request line multiplexer channel x control register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DMAREQ_ID</name> <description>Input DMA request line selected</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>SOIE</name> <description>Interrupt enable at synchronization event overrun</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EGE</name> <description>Event generation enable/disable</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SE</name> <description>Synchronous operating mode enable/disable</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPOL</name> <description>Synchronization event type selector Defines the synchronization event on the selected synchronization input:</description> <bitOffset>17</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>NBREQ</name> <description>Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.</description> <bitOffset>19</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>SYNC_ID</name> <description>Synchronization input selected</description> <bitOffset>24</bitOffset> <bitWidth>5</bitWidth> </field> </fields> </register> <register> <name>C4CR</name> <displayName>C4CR</displayName> <description>DMAMux - DMA request line multiplexer channel x control register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DMAREQ_ID</name> <description>Input DMA request line selected</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>SOIE</name> <description>Interrupt enable at synchronization event overrun</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EGE</name> <description>Event generation enable/disable</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SE</name> <description>Synchronous operating mode enable/disable</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPOL</name> <description>Synchronization event type selector Defines the synchronization event on the selected synchronization input:</description> <bitOffset>17</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>NBREQ</name> <description>Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.</description> <bitOffset>19</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>SYNC_ID</name> <description>Synchronization input selected</description> <bitOffset>24</bitOffset> <bitWidth>5</bitWidth> </field> </fields> </register> <register> <name>C5CR</name> <displayName>C5CR</displayName> <description>DMAMux - DMA request line multiplexer channel x control register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DMAREQ_ID</name> <description>Input DMA request line selected</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>SOIE</name> <description>Interrupt enable at synchronization event overrun</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EGE</name> <description>Event generation enable/disable</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SE</name> <description>Synchronous operating mode enable/disable</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPOL</name> <description>Synchronization event type selector Defines the synchronization event on the selected synchronization input:</description> <bitOffset>17</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>NBREQ</name> <description>Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.</description> <bitOffset>19</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>SYNC_ID</name> <description>Synchronization input selected</description> <bitOffset>24</bitOffset> <bitWidth>5</bitWidth> </field> </fields> </register> <register> <name>C6CR</name> <displayName>C6CR</displayName> <description>DMAMux - DMA request line multiplexer channel x control register</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DMAREQ_ID</name> <description>Input DMA request line selected</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>SOIE</name> <description>Interrupt enable at synchronization event overrun</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EGE</name> <description>Event generation enable/disable</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SE</name> <description>Synchronous operating mode enable/disable</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPOL</name> <description>Synchronization event type selector Defines the synchronization event on the selected synchronization input:</description> <bitOffset>17</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>NBREQ</name> <description>Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.</description> <bitOffset>19</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>SYNC_ID</name> <description>Synchronization input selected</description> <bitOffset>24</bitOffset> <bitWidth>5</bitWidth> </field> </fields> </register> <register> <name>RG0CR</name> <displayName>RG0CR</displayName> <description>DMAMux - DMA request generator channel x control register</description> <addressOffset>0x100</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SIG_ID</name> <description>DMA request trigger input selected</description> <bitOffset>0</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>OIE</name> <description>Interrupt enable at trigger event overrun</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GE</name> <description>DMA request generator channel enable/disable</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GPOL</name> <description>DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input</description> <bitOffset>17</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>GNBREQ</name> <description>Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.</description> <bitOffset>19</bitOffset> <bitWidth>5</bitWidth> </field> </fields> </register> <register> <name>RG1CR</name> <displayName>RG1CR</displayName> <description>DMAMux - DMA request generator channel x control register</description> <addressOffset>0x104</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SIG_ID</name> <description>DMA request trigger input selected</description> <bitOffset>0</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>OIE</name> <description>Interrupt enable at trigger event overrun</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GE</name> <description>DMA request generator channel enable/disable</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GPOL</name> <description>DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input</description> <bitOffset>17</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>GNBREQ</name> <description>Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.</description> <bitOffset>19</bitOffset> <bitWidth>5</bitWidth> </field> </fields> </register> <register> <name>RG2CR</name> <displayName>RG2CR</displayName> <description>DMAMux - DMA request generator channel x control register</description> <addressOffset>0x108</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SIG_ID</name> <description>DMA request trigger input selected</description> <bitOffset>0</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>OIE</name> <description>Interrupt enable at trigger event overrun</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GE</name> <description>DMA request generator channel enable/disable</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GPOL</name> <description>DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input</description> <bitOffset>17</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>GNBREQ</name> <description>Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.</description> <bitOffset>19</bitOffset> <bitWidth>5</bitWidth> </field> </fields> </register> <register> <name>RG3CR</name> <displayName>RG3CR</displayName> <description>DMAMux - DMA request generator channel x control register</description> <addressOffset>0x10C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SIG_ID</name> <description>DMA request trigger input selected</description> <bitOffset>0</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>OIE</name> <description>Interrupt enable at trigger event overrun</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GE</name> <description>DMA request generator channel enable/disable</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GPOL</name> <description>DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input</description> <bitOffset>17</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>GNBREQ</name> <description>Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.</description> <bitOffset>19</bitOffset> <bitWidth>5</bitWidth> </field> </fields> </register> <register> <name>RGSR</name> <displayName>RGSR</displayName> <description>DMAMux - DMA request generator status register</description> <addressOffset>0x140</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OF</name> <description>Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register.</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>RGCFR</name> <displayName>RGCFR</displayName> <description>DMAMux - DMA request generator clear flag register</description> <addressOffset>0x144</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>COF</name> <description>Clear trigger event overrun flag Upon setting, this bit clears the corresponding overrun flag OFx in the DMAMUX_RGCSR register.</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>GPIOA</name> <description>General-purpose I/Os</description> <groupName>GPIO</groupName> <baseAddress>0x50000000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>MODER</name> <displayName>MODER</displayName> <description>GPIO port mode register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0xEBFFFFFF</resetValue> <fields> <field> <name>MODER15</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>30</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER14</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>28</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER13</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>26</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER12</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>24</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER11</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>22</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER10</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER9</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER8</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER7</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER6</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER5</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER4</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER3</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER2</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER1</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER0</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>OTYPER</name> <displayName>OTYPER</displayName> <description>GPIO port output type register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OT15</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT14</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT13</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT12</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT11</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT10</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT9</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT8</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT7</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT6</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT5</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT4</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT3</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT2</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT1</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT0</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OSPEEDR</name> <displayName>OSPEEDR</displayName> <description>GPIO port output speed register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0C000000</resetValue> <fields> <field> <name>OSPEEDR15</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>30</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR14</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>28</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR13</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>26</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR12</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>24</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR11</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>22</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR10</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR9</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR8</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR7</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR6</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR5</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR4</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR3</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR2</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR1</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR0</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>PUPDR</name> <displayName>PUPDR</displayName> <description>GPIO port pull-up/pull-down register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x24000000</resetValue> <fields> <field> <name>PUPDR15</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>30</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR14</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>28</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR13</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>26</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR12</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>24</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR11</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>22</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR10</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR9</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR8</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR7</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR6</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR5</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR4</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR3</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR2</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR1</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR0</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>IDR</name> <displayName>IDR</displayName> <description>GPIO port input data register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IDR15</name> <description>Port input data (y = 0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR14</name> <description>Port input data (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR13</name> <description>Port input data (y = 0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR12</name> <description>Port input data (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR11</name> <description>Port input data (y = 0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR10</name> <description>Port input data (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR9</name> <description>Port input data (y = 0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR8</name> <description>Port input data (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR7</name> <description>Port input data (y = 0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR6</name> <description>Port input data (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR5</name> <description>Port input data (y = 0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR4</name> <description>Port input data (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR3</name> <description>Port input data (y = 0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR2</name> <description>Port input data (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR1</name> <description>Port input data (y = 0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR0</name> <description>Port input data (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ODR</name> <displayName>ODR</displayName> <description>GPIO port output data register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ODR15</name> <description>Port output data (y = 0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR14</name> <description>Port output data (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR13</name> <description>Port output data (y = 0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR12</name> <description>Port output data (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR11</name> <description>Port output data (y = 0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR10</name> <description>Port output data (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR9</name> <description>Port output data (y = 0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR8</name> <description>Port output data (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR7</name> <description>Port output data (y = 0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR6</name> <description>Port output data (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR5</name> <description>Port output data (y = 0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR4</name> <description>Port output data (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR3</name> <description>Port output data (y = 0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR2</name> <description>Port output data (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR1</name> <description>Port output data (y = 0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR0</name> <description>Port output data (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>BSRR</name> <displayName>BSRR</displayName> <description>GPIO port bit set/reset register</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BR15</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR14</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR13</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR12</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR11</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR10</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR9</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR8</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR7</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR6</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR5</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR4</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR3</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR2</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR1</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR0</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS15</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS14</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS13</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS12</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS11</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS10</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS9</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS8</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS7</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS6</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS5</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS4</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS3</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS2</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS1</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS0</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>LCKR</name> <displayName>LCKR</displayName> <description>GPIO port configuration lock register</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>LCKK</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK15</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK14</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK13</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK12</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK11</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK10</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK9</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK8</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK7</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK6</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK5</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK4</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK3</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK2</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK1</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK0</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>AFRL</name> <displayName>AFRL</displayName> <description>GPIO alternate function low register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>AFSEL7</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>28</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFSEL6</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>24</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFSEL5</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>20</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFSEL4</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFSEL3</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>12</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFSEL2</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFSEL1</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFSEL0</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>AFRH</name> <displayName>AFRH</displayName> <description>GPIO alternate function high register</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>AFSEL15</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>28</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFSEL14</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>24</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFSEL13</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>20</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFSEL12</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFSEL11</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>12</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFSEL10</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFSEL9</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFSEL8</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>BRR</name> <displayName>BRR</displayName> <description>port bit reset register</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BR0</name> <description>Port Reset bit</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR1</name> <description>Port Reset bit</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR2</name> <description>Port Reset bit</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR3</name> <description>Port Reset bit</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR4</name> <description>Port Reset bit</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR5</name> <description>Port Reset bit</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR6</name> <description>Port Reset bit</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR7</name> <description>Port Reset bit</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR8</name> <description>Port Reset bit</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR9</name> <description>Port Reset bit</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR10</name> <description>Port Reset bit</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR11</name> <description>Port Reset bit</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR12</name> <description>Port Reset bit</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR13</name> <description>Port Reset bit</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR14</name> <description>Port Reset bit</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR15</name> <description>Port Reset bit</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>GPIOB</name> <description>General-purpose I/Os</description> <groupName>GPIO</groupName> <baseAddress>0x50000400</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>MODER</name> <displayName>MODER</displayName> <description>GPIO port mode register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0xFFFFFFFF</resetValue> <fields> <field> <name>MODER15</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>30</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER14</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>28</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER13</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>26</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER12</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>24</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER11</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>22</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER10</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER9</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER8</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER7</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER6</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER5</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER4</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER3</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER2</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER1</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER0</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>OTYPER</name> <displayName>OTYPER</displayName> <description>GPIO port output type register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OT15</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT14</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT13</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT12</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT11</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT10</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT9</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT8</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT7</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT6</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT5</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT4</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT3</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT2</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT1</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT0</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OSPEEDR</name> <displayName>OSPEEDR</displayName> <description>GPIO port output speed register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OSPEEDR15</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>30</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR14</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>28</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR13</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>26</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR12</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>24</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR11</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>22</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR10</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR9</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR8</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR7</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR6</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR5</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR4</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR3</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR2</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR1</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR0</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>PUPDR</name> <displayName>PUPDR</displayName> <description>GPIO port pull-up/pull-down register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PUPDR15</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>30</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR14</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>28</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR13</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>26</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR12</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>24</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR11</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>22</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR10</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR9</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR8</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR7</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR6</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR5</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR4</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR3</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR2</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR1</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR0</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>IDR</name> <displayName>IDR</displayName> <description>GPIO port input data register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IDR15</name> <description>Port input data (y = 0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR14</name> <description>Port input data (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR13</name> <description>Port input data (y = 0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR12</name> <description>Port input data (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR11</name> <description>Port input data (y = 0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR10</name> <description>Port input data (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR9</name> <description>Port input data (y = 0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR8</name> <description>Port input data (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR7</name> <description>Port input data (y = 0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR6</name> <description>Port input data (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR5</name> <description>Port input data (y = 0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR4</name> <description>Port input data (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR3</name> <description>Port input data (y = 0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR2</name> <description>Port input data (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR1</name> <description>Port input data (y = 0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR0</name> <description>Port input data (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ODR</name> <displayName>ODR</displayName> <description>GPIO port output data register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ODR15</name> <description>Port output data (y = 0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR14</name> <description>Port output data (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR13</name> <description>Port output data (y = 0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR12</name> <description>Port output data (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR11</name> <description>Port output data (y = 0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR10</name> <description>Port output data (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR9</name> <description>Port output data (y = 0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR8</name> <description>Port output data (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR7</name> <description>Port output data (y = 0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR6</name> <description>Port output data (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR5</name> <description>Port output data (y = 0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR4</name> <description>Port output data (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR3</name> <description>Port output data (y = 0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR2</name> <description>Port output data (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR1</name> <description>Port output data (y = 0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR0</name> <description>Port output data (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>BSRR</name> <displayName>BSRR</displayName> <description>GPIO port bit set/reset register</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BR15</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR14</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR13</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR12</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR11</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR10</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR9</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR8</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR7</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR6</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR5</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR4</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR3</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR2</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR1</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR0</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS15</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS14</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS13</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS12</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS11</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS10</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS9</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS8</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS7</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS6</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS5</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS4</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS3</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS2</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS1</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS0</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>LCKR</name> <displayName>LCKR</displayName> <description>GPIO port configuration lock register</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>LCKK</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK15</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK14</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK13</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK12</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK11</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK10</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK9</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK8</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK7</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK6</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK5</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK4</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK3</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK2</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK1</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK0</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>AFRL</name> <displayName>AFRL</displayName> <description>GPIO alternate function low register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>AFSEL7</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>28</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFSEL6</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>24</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFSEL5</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>20</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFSEL4</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFSEL3</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>12</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFSEL2</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFSEL1</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFSEL0</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>AFRH</name> <displayName>AFRH</displayName> <description>GPIO alternate function high register</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>AFSEL15</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>28</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFSEL14</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>24</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFSEL13</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>20</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFSEL12</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFSEL11</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>12</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFSEL10</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFSEL9</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFSEL8</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>BRR</name> <displayName>BRR</displayName> <description>port bit reset register</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BR0</name> <description>Port Reset bit</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR1</name> <description>Port Reset bit</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR2</name> <description>Port Reset bit</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR3</name> <description>Port Reset bit</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR4</name> <description>Port Reset bit</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR5</name> <description>Port Reset bit</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR6</name> <description>Port Reset bit</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR7</name> <description>Port Reset bit</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR8</name> <description>Port Reset bit</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR9</name> <description>Port Reset bit</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR10</name> <description>Port Reset bit</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR11</name> <description>Port Reset bit</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR12</name> <description>Port Reset bit</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR13</name> <description>Port Reset bit</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR14</name> <description>Port Reset bit</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR15</name> <description>Port Reset bit</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral derivedFrom="GPIOB"> <name>GPIOC</name> <baseAddress>0x50000800</baseAddress> </peripheral> <peripheral derivedFrom="GPIOB"> <name>GPIOD</name> <baseAddress>0x50000C00</baseAddress> </peripheral> <peripheral derivedFrom="GPIOB"> <name>GPIOF</name> <baseAddress>0x50001400</baseAddress> </peripheral> <peripheral> <name>CRC</name> <description>Cyclic redundancy check calculation unit</description> <groupName>CRC</groupName> <baseAddress>0x40023000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>CEC</name> <description>CEC global interrupt</description> <value>30</value> </interrupt> <registers> <register> <name>DR</name> <displayName>DR</displayName> <description>Data register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0xFFFFFFFF</resetValue> <fields> <field> <name>DR</name> <description>Data register bits</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>IDR</name> <displayName>IDR</displayName> <description>Independent data register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IDR</name> <description>General-purpose 32-bit data register bits</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CR</name> <displayName>CR</displayName> <description>Control register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <resetValue>0x00000000</resetValue> <fields> <field> <name>REV_OUT</name> <description>Reverse output data</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>REV_IN</name> <description>Reverse input data</description> <bitOffset>5</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> <field> <name>POLYSIZE</name> <description>Polynomial size</description> <bitOffset>3</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> <field> <name>RESET</name> <description>RESET bit</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> </fields> </register> <register> <name>INIT</name> <displayName>INIT</displayName> <description>Initial CRC value</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0xFFFFFFFF</resetValue> <fields> <field> <name>CRC_INIT</name> <description>Programmable initial CRC value</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>POL</name> <displayName>POL</displayName> <description>polynomial</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x04C11DB7</resetValue> <fields> <field> <name>POL</name> <description>Programmable polynomial</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>EXTI</name> <description>External interrupt/event controller</description> <groupName>EXTI</groupName> <baseAddress>0x40021800</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>PVD</name> <description>Power voltage detector interrupt</description> <value>1</value> </interrupt> <interrupt> <name>EXTI0_1</name> <description>EXTI line 0 & 1 interrupt</description> <value>5</value> </interrupt> <interrupt> <name>EXTI2_3</name> <description>EXTI line 2 & 3 interrupt</description> <value>6</value> </interrupt> <interrupt> <name>EXTI4_15</name> <description>EXTI line 4 to 15 interrupt</description> <value>7</value> </interrupt> <registers> <register> <name>RTSR1</name> <displayName>RTSR1</displayName> <description>EXTI rising trigger selection register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TR0</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR1</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR2</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR3</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR4</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR5</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR6</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR7</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR8</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR9</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR10</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR11</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR12</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR13</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR14</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR15</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR16</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>FTSR1</name> <displayName>FTSR1</displayName> <description>EXTI falling trigger selection register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TR0</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR1</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR2</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR3</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR4</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR5</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR6</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR7</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR8</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR9</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR10</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR11</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR12</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR13</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR14</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR15</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR16</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SWIER1</name> <displayName>SWIER1</displayName> <description>EXTI software interrupt event register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SWIER0</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER1</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER2</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER3</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER4</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER5</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER6</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER7</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER8</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER9</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER10</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER11</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER12</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER13</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER14</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER15</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER16</name> <description>Rising trigger event configuration bit of Configurable Event input</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>RPR1</name> <displayName>RPR1</displayName> <description>EXTI rising edge pending register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>RPIF0</name> <description>configurable event inputs x rising edge Pending bit.</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RPIF1</name> <description>configurable event inputs x rising edge Pending bit.</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RPIF2</name> <description>configurable event inputs x rising edge Pending bit.</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RPIF3</name> <description>configurable event inputs x rising edge Pending bit.</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RPIF4</name> <description>configurable event inputs x rising edge Pending bit.</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RPIF5</name> <description>configurable event inputs x rising edge Pending bit</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RPIF6</name> <description>configurable event inputs x rising edge Pending bit.</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RPIF7</name> <description>configurable event inputs x rising edge Pending bit.</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RPIF8</name> <description>configurable event inputs x rising edge Pending bit.</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RPIF9</name> <description>configurable event inputs x rising edge Pending bit.</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RPIF10</name> <description>configurable event inputs x rising edge Pending bit.</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RPIF11</name> <description>configurable event inputs x rising edge Pending bit.</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RPIF12</name> <description>configurable event inputs x rising edge Pending bit.</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RPIF13</name> <description>configurable event inputs x rising edge Pending bit.</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RPIF14</name> <description>configurable event inputs x rising edge Pending bit.</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RPIF15</name> <description>configurable event inputs x rising edge Pending bit.</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RPIF16</name> <description>configurable event inputs x rising edge Pending bit.</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>FPR1</name> <displayName>FPR1</displayName> <description>EXTI falling edge pending register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FPIF0</name> <description>configurable event inputs x falling edge pending bit.</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FPIF1</name> <description>configurable event inputs x falling edge pending bit.</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FPIF2</name> <description>configurable event inputs x falling edge pending bit.</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FPIF3</name> <description>configurable event inputs x falling edge pending bit.</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FPIF4</name> <description>configurable event inputs x falling edge pending bit.</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FPIF5</name> <description>configurable event inputs x falling edge pending bit.</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FPIF6</name> <description>configurable event inputs x falling edge pending bit.</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FPIF7</name> <description>configurable event inputs x falling edge pending bit.</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FPIF8</name> <description>configurable event inputs x falling edge pending bit.</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FPIF9</name> <description>configurable event inputs x falling edge pending bit.</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FPIF10</name> <description>configurable event inputs x falling edge pending bit.</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FPIF11</name> <description>configurable event inputs x falling edge pending bit.</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FPIF12</name> <description>configurable event inputs x falling edge pending bit.</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FPIF13</name> <description>configurable event inputs x falling edge pending bit.</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FPIF14</name> <description>configurable event inputs x falling edge pending bit.</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FPIF15</name> <description>configurable event inputs x falling edge pending bit.</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FPIF16</name> <description>configurable event inputs x falling edge pending bit.</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>EXTICR1</name> <displayName>EXTICR1</displayName> <description>EXTI external interrupt selection register</description> <addressOffset>0x60</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>EXTI0_7</name> <description>GPIO port selection</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>EXTI8_15</name> <description>GPIO port selection</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>EXTI16_23</name> <description>GPIO port selection</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>EXTI24_31</name> <description>GPIO port selection</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>EXTICR2</name> <displayName>EXTICR2</displayName> <description>EXTI external interrupt selection register</description> <addressOffset>0x64</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>EXTI0_7</name> <description>GPIO port selection</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>EXTI8_15</name> <description>GPIO port selection</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>EXTI16_23</name> <description>GPIO port selection</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>EXTI24_31</name> <description>GPIO port selection</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>EXTICR3</name> <displayName>EXTICR3</displayName> <description>EXTI external interrupt selection register</description> <addressOffset>0x68</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>EXTI0_7</name> <description>GPIO port selection</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>EXTI8_15</name> <description>GPIO port selection</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>EXTI16_23</name> <description>GPIO port selection</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>EXTI24_31</name> <description>GPIO port selection</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>EXTICR4</name> <displayName>EXTICR4</displayName> <description>EXTI external interrupt selection register</description> <addressOffset>0x6C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>EXTI0_7</name> <description>GPIO port selection</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>EXTI8_15</name> <description>GPIO port selection</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>EXTI16_23</name> <description>GPIO port selection</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>EXTI24_31</name> <description>GPIO port selection</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IMR1</name> <displayName>IMR1</displayName> <description>EXTI CPU wakeup with interrupt mask register</description> <addressOffset>0x80</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0xFFF80000</resetValue> <fields> <field> <name>IM0</name> <description>CPU wakeup with interrupt mask on event input</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IM1</name> <description>CPU wakeup with interrupt mask on event input</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IM2</name> <description>CPU wakeup with interrupt mask on event input</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IM3</name> <description>CPU wakeup with interrupt mask on event input</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IM4</name> <description>CPU wakeup with interrupt mask on event input</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IM5</name> <description>CPU wakeup with interrupt mask on event input</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IM6</name> <description>CPU wakeup with interrupt mask on event input</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IM7</name> <description>CPU wakeup with interrupt mask on event input</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IM8</name> <description>CPU wakeup with interrupt mask on event input</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IM9</name> <description>CPU wakeup with interrupt mask on event input</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IM10</name> <description>CPU wakeup with interrupt mask on event input</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IM11</name> <description>CPU wakeup with interrupt mask on event input</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IM12</name> <description>CPU wakeup with interrupt mask on event input</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IM13</name> <description>CPU wakeup with interrupt mask on event input</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IM14</name> <description>CPU wakeup with interrupt mask on event input</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IM15</name> <description>CPU wakeup with interrupt mask on event input</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IM16</name> <description>CPU wakeup with interrupt mask on event input</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IM19</name> <description>CPU wakeup with interrupt mask on event input</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IM20</name> <description>CPU wakeup with interrupt mask on event input</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IM21</name> <description>CPU wakeup with interrupt mask on event input</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IM22</name> <description>CPU wakeup with interrupt mask on event input</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IM23</name> <description>CPU wakeup with interrupt mask on event input</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IM24</name> <description>CPU wakeup with interrupt mask on event input</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IM25</name> <description>CPU wakeup with interrupt mask on event input</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IM26</name> <description>CPU wakeup with interrupt mask on event input</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IM28</name> <description>CPU wakeup with interrupt mask on event input</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IM29</name> <description>CPU wakeup with interrupt mask on event input</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IM30</name> <description>CPU wakeup with interrupt mask on event input</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IM31</name> <description>CPU wakeup with interrupt mask on event input</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>EMR1</name> <displayName>EMR1</displayName> <description>EXTI CPU wakeup with event mask register</description> <addressOffset>0x84</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>EM0</name> <description>CPU wakeup with event mask on event input</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EM1</name> <description>CPU wakeup with event mask on event input</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EM2</name> <description>CPU wakeup with event mask on event input</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EM3</name> <description>CPU wakeup with event mask on event input</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EM4</name> <description>CPU wakeup with event mask on event input</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EM5</name> <description>CPU wakeup with event mask on event input</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EM6</name> <description>CPU wakeup with event mask on event input</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EM7</name> <description>CPU wakeup with event mask on event input</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EM8</name> <description>CPU wakeup with event mask on event input</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EM9</name> <description>CPU wakeup with event mask on event input</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EM10</name> <description>CPU wakeup with event mask on event input</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EM11</name> <description>CPU wakeup with event mask on event input</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EM12</name> <description>CPU wakeup with event mask on event input</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EM13</name> <description>CPU wakeup with event mask on event input</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EM14</name> <description>CPU wakeup with event mask on event input</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EM15</name> <description>CPU wakeup with event mask on event input</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EM16</name> <description>CPU wakeup with event mask on event input</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EM19</name> <description>CPU wakeup with event mask on event input</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EM21</name> <description>CPU wakeup with event mask on event input</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EM23</name> <description>CPU wakeup with event mask on event input</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EM25</name> <description>CPU wakeup with event mask on event input</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EM26</name> <description>CPU wakeup with event mask on event input</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EM28</name> <description>CPU wakeup with event mask on event input</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EM29</name> <description>CPU wakeup with event mask on event input</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EM30</name> <description>CPU wakeup with event mask on event input</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EM31</name> <description>CPU wakeup with event mask on event input</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>TIM16</name> <description>General purpose timers</description> <groupName>TIM</groupName> <baseAddress>0x40014400</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>TIM16</name> <description>TIM16 global interrupt</description> <value>21</value> </interrupt> <registers> <register> <name>CR1</name> <displayName>CR1</displayName> <description>control register 1</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CEN</name> <description>Counter enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UDIS</name> <description>Update disable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>URS</name> <description>Update request source</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OPM</name> <description>One-pulse mode</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ARPE</name> <description>Auto-reload preload enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CKD</name> <description>Clock division</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>UIFREMAP</name> <description>UIF status bit remapping</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CR2</name> <displayName>CR2</displayName> <description>control register 2</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>OIS1N</name> <description>Output Idle state 1</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OIS1</name> <description>Output Idle state 1</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CCDS</name> <description>Capture/compare DMA selection</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CCUS</name> <description>Capture/compare control update selection</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CCPC</name> <description>Capture/compare preloaded control</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>DIER</name> <displayName>DIER</displayName> <description>DMA/Interrupt enable register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>COMDE</name> <description>COM DMA request enable</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1DE</name> <description>Capture/Compare 1 DMA request enable</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UDE</name> <description>Update DMA request enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BIE</name> <description>Break interrupt enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>COMIE</name> <description>COM interrupt enable</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1IE</name> <description>Capture/Compare 1 interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UIE</name> <description>Update interrupt enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SR</name> <displayName>SR</displayName> <description>status register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CC1OF</name> <description>Capture/Compare 1 overcapture flag</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BIF</name> <description>Break interrupt flag</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>COMIF</name> <description>COM interrupt flag</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1IF</name> <description>Capture/compare 1 interrupt flag</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UIF</name> <description>Update interrupt flag</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>EGR</name> <displayName>EGR</displayName> <description>event generation register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x0000</resetValue> <fields> <field> <name>BG</name> <description>Break generation</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>COMG</name> <description>Capture/Compare control update generation</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1G</name> <description>Capture/compare 1 generation</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UG</name> <description>Update generation</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CCMR1_Output</name> <displayName>CCMR1_Output</displayName> <description>capture/compare mode register (output mode)</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OC1M_2</name> <description>Output Compare 1 mode</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC1M</name> <description>Output Compare 1 mode</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC1PE</name> <description>Output Compare 1 preload enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC1FE</name> <description>Output Compare 1 fast enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1S</name> <description>Capture/Compare 1 selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CCMR1_Input</name> <displayName>CCMR1_Input</displayName> <description>capture/compare mode register 1 (input mode)</description> <alternateRegister>CCMR1_Output</alternateRegister> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IC1F</name> <description>Input capture 1 filter</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>IC1PSC</name> <description>Input capture 1 prescaler</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CC1S</name> <description>Capture/Compare 1 selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CCER</name> <displayName>CCER</displayName> <description>capture/compare enable register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CC1NP</name> <description>Capture/Compare 1 output Polarity</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1NE</name> <description>Capture/Compare 1 complementary output enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1P</name> <description>Capture/Compare 1 output Polarity</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1E</name> <description>Capture/Compare 1 output enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CNT</name> <displayName>CNT</displayName> <description>counter</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <resetValue>0x00000000</resetValue> <fields> <field> <name>CNT</name> <description>counter value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> <access>read-write</access> </field> <field> <name>UIFCPY</name> <description>UIF Copy</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> </fields> </register> <register> <name>PSC</name> <displayName>PSC</displayName> <description>prescaler</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>PSC</name> <description>Prescaler value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>ARR</name> <displayName>ARR</displayName> <description>auto-reload register</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ARR</name> <description>Auto-reload value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>RCR</name> <displayName>RCR</displayName> <description>repetition counter register</description> <addressOffset>0x30</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>REP</name> <description>Repetition counter value</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>CCR1</name> <displayName>CCR1</displayName> <description>capture/compare register 1</description> <addressOffset>0x34</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCR1</name> <description>Capture/Compare 1 value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>BDTR</name> <displayName>BDTR</displayName> <description>break and dead-time register</description> <addressOffset>0x44</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>DTG</name> <description>Dead-time generator setup</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>LOCK</name> <description>Lock configuration</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSSI</name> <description>Off-state selection for Idle mode</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OSSR</name> <description>Off-state selection for Run mode</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BKE</name> <description>Break enable</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BKP</name> <description>Break polarity</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AOE</name> <description>Automatic output enable</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MOE</name> <description>Main output enable</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BKF</name> <description>Break filter</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>BKDSRM</name> <description>Break Disarm</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BKBID</name> <description>Break Bidirectional</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>DCR</name> <displayName>DCR</displayName> <description>DMA control register</description> <addressOffset>0x48</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>DBL</name> <description>DMA burst length</description> <bitOffset>8</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>DBA</name> <description>DMA base address</description> <bitOffset>0</bitOffset> <bitWidth>5</bitWidth> </field> </fields> </register> <register> <name>DMAR</name> <displayName>DMAR</displayName> <description>DMA address for full transfer</description> <addressOffset>0x4C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>DMAB</name> <description>DMA register for burst accesses</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>AF1</name> <displayName>AF1</displayName> <description>TIM17 option register 1</description> <addressOffset>0x60</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>BKINE</name> <description>BRK BKIN input enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BKCMP1E</name> <description>BRK COMP1 enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BKCMP2E</name> <description>BRK COMP2 enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BKDFBK1E</name> <description>BRK DFSDM_BREAK1 enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BKINP</name> <description>BRK BKIN input polarity</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BKCMP1P</name> <description>BRK COMP1 input polarity</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BKCMP2P</name> <description>BRK COMP2 input polarit</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>TISEL</name> <displayName>TISEL</displayName> <description>input selection register</description> <addressOffset>0x68</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>TI1SEL</name> <description>selects input</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral derivedFrom="TIM16"> <name>TIM17</name> <baseAddress>0x40014800</baseAddress> <interrupt> <name>TIM17</name> <description>TIM17 global interrupt</description> <value>22</value> </interrupt> </peripheral> <peripheral> <name>USART1</name> <description>Universal synchronous asynchronous receiver transmitter</description> <groupName>USART</groupName> <baseAddress>0x40013800</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>USART1</name> <description>USART1 global interrupt</description> <value>27</value> </interrupt> <registers> <register> <name>CR1</name> <displayName>CR1</displayName> <description>Control register 1</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>RXFFIE</name> <description>RXFIFO Full interrupt enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXFEIE</name> <description>TXFIFO empty interrupt enable</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FIFOEN</name> <description>FIFO mode enable</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>M1</name> <description>Word length</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EOBIE</name> <description>End of Block interrupt enable</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RTOIE</name> <description>Receiver timeout interrupt enable</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DEAT</name> <description>DEAT</description> <bitOffset>21</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>DEDT</name> <description>DEDT</description> <bitOffset>16</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>OVER8</name> <description>Oversampling mode</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CMIE</name> <description>Character match interrupt enable</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MME</name> <description>Mute mode enable</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>M0</name> <description>Word length</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WAKE</name> <description>Receiver wakeup method</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PCE</name> <description>Parity control enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PS</name> <description>Parity selection</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PEIE</name> <description>PE interrupt enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXEIE</name> <description>interrupt enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIE</name> <description>Transmission complete interrupt enable</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RXNEIE</name> <description>RXNE interrupt enable</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDLEIE</name> <description>IDLE interrupt enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TE</name> <description>Transmitter enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RE</name> <description>Receiver enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UESM</name> <description>USART enable in Stop mode</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UE</name> <description>USART enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CR2</name> <displayName>CR2</displayName> <description>Control register 2</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>ADD4_7</name> <description>Address of the USART node</description> <bitOffset>28</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>ADD0_3</name> <description>Address of the USART node</description> <bitOffset>24</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>RTOEN</name> <description>Receiver timeout enable</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ABRMOD</name> <description>Auto baud rate mode</description> <bitOffset>21</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>ABREN</name> <description>Auto baud rate enable</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MSBFIRST</name> <description>Most significant bit first</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TAINV</name> <description>Binary data inversion</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXINV</name> <description>TX pin active level inversion</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RXINV</name> <description>RX pin active level inversion</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWAP</name> <description>Swap TX/RX pins</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LINEN</name> <description>LIN mode enable</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STOP</name> <description>STOP bits</description> <bitOffset>12</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CLKEN</name> <description>Clock enable</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CPOL</name> <description>Clock polarity</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CPHA</name> <description>Clock phase</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LBCL</name> <description>Last bit clock pulse</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LBDIE</name> <description>LIN break detection interrupt enable</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LBDL</name> <description>LIN break detection length</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADDM7</name> <description>7-bit Address Detection/4-bit Address Detection</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DIS_NSS</name> <description>When the DSI_NSS bit is set, the NSS pin input will be ignored</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SLVEN</name> <description>Synchronous Slave mode enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CR3</name> <displayName>CR3</displayName> <description>Control register 3</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>TXFTCFG</name> <description>TXFIFO threshold configuration</description> <bitOffset>29</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>RXFTIE</name> <description>RXFIFO threshold interrupt enable</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RXFTCFG</name> <description>Receive FIFO threshold configuration</description> <bitOffset>25</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>TCBGTIE</name> <description>Tr Complete before guard time, interrupt enable</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXFTIE</name> <description>threshold interrupt enable</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WUFIE</name> <description>Wakeup from Stop mode interrupt enable</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WUS</name> <description>Wakeup from Stop mode interrupt flag selection</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>SCARCNT</name> <description>Smartcard auto-retry count</description> <bitOffset>17</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>DEP</name> <description>Driver enable polarity selection</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DEM</name> <description>Driver enable mode</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DDRE</name> <description>DMA Disable on Reception Error</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OVRDIS</name> <description>Overrun Disable</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ONEBIT</name> <description>One sample bit method enable</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTSIE</name> <description>CTS interrupt enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTSE</name> <description>CTS enable</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RTSE</name> <description>RTS enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMAT</name> <description>DMA enable transmitter</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMAR</name> <description>DMA enable receiver</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SCEN</name> <description>Smartcard mode enable</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NACK</name> <description>Smartcard NACK enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HDSEL</name> <description>Half-duplex selection</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IRLP</name> <description>Ir low-power</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IREN</name> <description>Ir mode enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EIE</name> <description>Error interrupt enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>BRR</name> <displayName>BRR</displayName> <description>Baud rate register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>BRR_4_15</name> <description>BRR_4_15</description> <bitOffset>4</bitOffset> <bitWidth>12</bitWidth> </field> <field> <name>BRR_0_3</name> <description>BRR_0_3</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>GTPR</name> <displayName>GTPR</displayName> <description>Guard time and prescaler register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>GT</name> <description>Guard time value</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>PSC</name> <description>Prescaler value</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>RTOR</name> <displayName>RTOR</displayName> <description>Receiver timeout register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>BLEN</name> <description>Block Length</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>RTO</name> <description>Receiver timeout value</description> <bitOffset>0</bitOffset> <bitWidth>24</bitWidth> </field> </fields> </register> <register> <name>RQR</name> <displayName>RQR</displayName> <description>Request register</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x0000</resetValue> <fields> <field> <name>TXFRQ</name> <description>Transmit data flush request</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RXFRQ</name> <description>Receive data flush request</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MMRQ</name> <description>Mute mode request</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SBKRQ</name> <description>Send break request</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ABRRQ</name> <description>Auto baud rate request</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ISR</name> <displayName>ISR</displayName> <description>Interrupt & status register</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00C0</resetValue> <fields> <field> <name>TXFT</name> <description>TXFIFO threshold flag</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RXFT</name> <description>RXFIFO threshold flag</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCBGT</name> <description>Transmission complete before guard time flag</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RXFF</name> <description>RXFIFO Full</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXFE</name> <description>TXFIFO Empty</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>REACK</name> <description>REACK</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEACK</name> <description>TEACK</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WUF</name> <description>WUF</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RWU</name> <description>RWU</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SBKF</name> <description>SBKF</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CMF</name> <description>CMF</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BUSY</name> <description>BUSY</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ABRF</name> <description>ABRF</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ABRE</name> <description>ABRE</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UDR</name> <description>SPI slave underrun error flag</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EOBF</name> <description>EOBF</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RTOF</name> <description>RTOF</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTS</name> <description>CTS</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTSIF</name> <description>CTSIF</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LBDF</name> <description>LBDF</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXE</name> <description>TXE</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TC</name> <description>TC</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RXNE</name> <description>RXNE</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDLE</name> <description>IDLE</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ORE</name> <description>ORE</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NF</name> <description>NF</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FE</name> <description>FE</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PE</name> <description>PE</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ICR</name> <displayName>ICR</displayName> <description>Interrupt flag clear register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x0000</resetValue> <fields> <field> <name>WUCF</name> <description>Wakeup from Stop mode clear flag</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CMCF</name> <description>Character match clear flag</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UDRCF</name> <description>SPI slave underrun clear flag</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EOBCF</name> <description>End of block clear flag</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RTOCF</name> <description>Receiver timeout clear flag</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTSCF</name> <description>CTS clear flag</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LBDCF</name> <description>LIN break detection clear flag</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCBGTCF</name> <description>Transmission complete before Guard time clear flag</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCCF</name> <description>Transmission complete clear flag</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXFECF</name> <description>TXFIFO empty clear flag</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDLECF</name> <description>Idle line detected clear flag</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ORECF</name> <description>Overrun error clear flag</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NCF</name> <description>Noise detected clear flag</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FECF</name> <description>Framing error clear flag</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PECF</name> <description>Parity error clear flag</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>RDR</name> <displayName>RDR</displayName> <description>Receive data register</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x0000</resetValue> <fields> <field> <name>RDR</name> <description>Receive data value</description> <bitOffset>0</bitOffset> <bitWidth>9</bitWidth> </field> </fields> </register> <register> <name>TDR</name> <displayName>TDR</displayName> <description>Transmit data register</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>TDR</name> <description>Transmit data value</description> <bitOffset>0</bitOffset> <bitWidth>9</bitWidth> </field> </fields> </register> <register> <name>PRESC</name> <displayName>PRESC</displayName> <description>Prescaler register</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>PRESCALER</name> <description>Clock prescaler</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral derivedFrom="USART1"> <name>USART2</name> <baseAddress>0x40004400</baseAddress> <interrupt> <name>USART2</name> <description>USART2 global interrupt</description> <value>28</value> </interrupt> </peripheral> <peripheral> <name>SPI1</name> <description>Serial peripheral interface/Inter-IC sound</description> <groupName>SPI</groupName> <baseAddress>0x40013000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>SPI1</name> <description>SPI1 global interrupt</description> <value>25</value> </interrupt> <registers> <register> <name>CR1</name> <displayName>CR1</displayName> <description>control register 1</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>BIDIMODE</name> <description>Bidirectional data mode enable</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BIDIOE</name> <description>Output enable in bidirectional mode</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CRCEN</name> <description>Hardware CRC calculation enable</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CRCNEXT</name> <description>CRC transfer next</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DFF</name> <description>Data frame format</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RXONLY</name> <description>Receive only</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SSM</name> <description>Software slave management</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SSI</name> <description>Internal slave select</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LSBFIRST</name> <description>Frame format</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPE</name> <description>SPI enable</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR</name> <description>Baud rate control</description> <bitOffset>3</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>MSTR</name> <description>Master selection</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CPOL</name> <description>Clock polarity</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CPHA</name> <description>Clock phase</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CR2</name> <displayName>CR2</displayName> <description>control register 2</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>RXDMAEN</name> <description>Rx buffer DMA enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXDMAEN</name> <description>Tx buffer DMA enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SSOE</name> <description>SS output enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NSSP</name> <description>NSS pulse management</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRF</name> <description>Frame format</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ERRIE</name> <description>Error interrupt enable</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RXNEIE</name> <description>RX buffer not empty interrupt enable</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXEIE</name> <description>Tx buffer empty interrupt enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DS</name> <description>Data size</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>FRXTH</name> <description>FIFO reception threshold</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LDMA_RX</name> <description>Last DMA transfer for reception</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LDMA_TX</name> <description>Last DMA transfer for transmission</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SR</name> <displayName>SR</displayName> <description>status register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <resetValue>0x0002</resetValue> <fields> <field> <name>RXNE</name> <description>Receive buffer not empty</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>TXE</name> <description>Transmit buffer empty</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>CHSIDE</name> <description>Channel side</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>UDR</name> <description>Underrun flag</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>CRCERR</name> <description>CRC error flag</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>MODF</name> <description>Mode fault</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>OVR</name> <description>Overrun flag</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>BSY</name> <description>Busy flag</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>TIFRFE</name> <description>TI frame format error</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>FRLVL</name> <description>FIFO reception level</description> <bitOffset>9</bitOffset> <bitWidth>2</bitWidth> <access>read-only</access> </field> <field> <name>FTLVL</name> <description>FIFO transmission level</description> <bitOffset>11</bitOffset> <bitWidth>2</bitWidth> <access>read-only</access> </field> </fields> </register> <register> <name>DR</name> <displayName>DR</displayName> <description>data register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>DR</name> <description>Data register</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CRCPR</name> <displayName>CRCPR</displayName> <description>CRC polynomial register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0007</resetValue> <fields> <field> <name>CRCPOLY</name> <description>CRC polynomial register</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>RXCRCR</name> <displayName>RXCRCR</displayName> <description>RX CRC register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x0000</resetValue> <fields> <field> <name>RxCRC</name> <description>Rx CRC register</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>TXCRCR</name> <displayName>TXCRCR</displayName> <description>TX CRC register</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x0000</resetValue> <fields> <field> <name>TxCRC</name> <description>Tx CRC register</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>I2SCFGR</name> <displayName>I2SCFGR</displayName> <description>configuration register</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CHLEN</name> <description>Channel length (number of bits per audio channel)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DATLEN</name> <description>Data length to be transferred</description> <bitOffset>1</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CKPOL</name> <description>Inactive state clock polarity</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>I2SSTD</name> <description>standard selection</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PCMSYNC</name> <description>PCM frame synchronization</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>I2SCFG</name> <description>I2S configuration mode</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>SE2</name> <description>I2S enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>I2SMOD</name> <description>I2S mode selection</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>I2SPR</name> <displayName>I2SPR</displayName> <description>prescaler register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>I2SDIV</name> <description>linear prescaler</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>ODD</name> <description>Odd factor for the prescaler</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MCKOE</name> <description>Master clock output enable</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral derivedFrom="SPI1"> <name>SPI2</name> <baseAddress>0x40003800</baseAddress> <interrupt> <name>SPI2</name> <description>SPI2 global interrupt</description> <value>26</value> </interrupt> </peripheral> <peripheral> <name>TIM1</name> <description>Advanced-timers</description> <groupName>TIM</groupName> <baseAddress>0x40012C00</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>TIM1_BRK_UP_TRG_COM</name> <description>TIM1 break, update, trigger</description> <value>13</value> </interrupt> <interrupt> <name>TIM1_CC</name> <description>TIM1 Capture Compare interrupt</description> <value>14</value> </interrupt> <registers> <register> <name>CR1</name> <displayName>CR1</displayName> <description>control register 1</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CEN</name> <description>Counter enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OPM</name> <description>One-pulse mode</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UDIS</name> <description>Update disable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>URS</name> <description>Update request source</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DIR</name> <description>Direction</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CMS</name> <description>Center-aligned mode selection</description> <bitOffset>5</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>ARPE</name> <description>Auto-reload preload enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CKD</name> <description>Clock division</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>UIFREMAP</name> <description>UIF status bit remapping</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CR2</name> <displayName>CR2</displayName> <description>control register 2</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>MMS2</name> <description>Master mode selection 2</description> <bitOffset>20</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>OIS6</name> <description>Output Idle state 6 (OC6 output)</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OIS5</name> <description>Output Idle state 5 (OC5 output)</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OIS4</name> <description>Output Idle state 4</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OIS3N</name> <description>Output Idle state 3</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OIS3</name> <description>Output Idle state 3</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OIS2N</name> <description>Output Idle state 2</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OIS2</name> <description>Output Idle state 2</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OIS1N</name> <description>Output Idle state 1</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OIS1</name> <description>Output Idle state 1</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TI1S</name> <description>TI1 selection</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MMS</name> <description>Master mode selection</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>CCDS</name> <description>Capture/compare DMA selection</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CCUS</name> <description>Capture/compare control update selection</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CCPC</name> <description>Capture/compare preloaded control</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SMCR</name> <displayName>SMCR</displayName> <description>slave mode control register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>SMS</name> <description>Slave mode selection</description> <bitOffset>0</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OCCS</name> <description>OCREF clear selection</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TS_4</name> <description>Trigger selection</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>MSM</name> <description>Master/Slave mode</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ETF</name> <description>External trigger filter</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>ETPS</name> <description>External trigger prescaler</description> <bitOffset>12</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>ECE</name> <description>External clock enable</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ETP</name> <description>External trigger polarity</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SMS_3</name> <description>Slave mode selection - bit 3</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TS</name> <description>Trigger selection</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>DIER</name> <displayName>DIER</displayName> <description>DMA/Interrupt enable register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>UIE</name> <description>Update interrupt enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1IE</name> <description>Capture/Compare 1 interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2IE</name> <description>Capture/Compare 2 interrupt enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3IE</name> <description>Capture/Compare 3 interrupt enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4IE</name> <description>Capture/Compare 4 interrupt enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>COMIE</name> <description>COM interrupt enable</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIE</name> <description>Trigger interrupt enable</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BIE</name> <description>Break interrupt enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UDE</name> <description>Update DMA request enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1DE</name> <description>Capture/Compare 1 DMA request enable</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2DE</name> <description>Capture/Compare 2 DMA request enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3DE</name> <description>Capture/Compare 3 DMA request enable</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4DE</name> <description>Capture/Compare 4 DMA request enable</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>COMDE</name> <description>COM DMA request enable</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TDE</name> <description>Trigger DMA request enable</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SR</name> <displayName>SR</displayName> <description>status register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>UIF</name> <description>Update interrupt flag</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1IF</name> <description>Capture/compare 1 interrupt flag</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2IF</name> <description>Capture/Compare 2 interrupt flag</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3IF</name> <description>Capture/Compare 3 interrupt flag</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4IF</name> <description>Capture/Compare 4 interrupt flag</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>COMIF</name> <description>COM interrupt flag</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIF</name> <description>Trigger interrupt flag</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BIF</name> <description>Break interrupt flag</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>B2IF</name> <description>Break 2 interrupt flag</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1OF</name> <description>Capture/Compare 1 overcapture flag</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2OF</name> <description>Capture/compare 2 overcapture flag</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3OF</name> <description>Capture/Compare 3 overcapture flag</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4OF</name> <description>Capture/Compare 4 overcapture flag</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SBIF</name> <description>System Break interrupt flag</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC5IF</name> <description>Compare 5 interrupt flag</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC6IF</name> <description>Compare 6 interrupt flag</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>EGR</name> <displayName>EGR</displayName> <description>event generation register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x0000</resetValue> <fields> <field> <name>UG</name> <description>Update generation</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1G</name> <description>Capture/compare 1 generation</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2G</name> <description>Capture/compare 2 generation</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3G</name> <description>Capture/compare 3 generation</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4G</name> <description>Capture/compare 4 generation</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>COMG</name> <description>Capture/Compare control update generation</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TG</name> <description>Trigger generation</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BG</name> <description>Break generation</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>B2G</name> <description>Break 2 generation</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CCMR1_Output</name> <displayName>CCMR1_Output</displayName> <description>capture/compare mode register 1 (output mode)</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CC1S</name> <description>Capture/Compare 1 selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OC1FE</name> <description>Output Compare 1 fast enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC1PE</name> <description>Output Compare 1 preload enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC1M</name> <description>Output Compare 1 mode</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC1CE</name> <description>Output Compare 1 clear enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2S</name> <description>Capture/Compare 2 selection</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OC2FE</name> <description>Output Compare 2 fast enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC2PE</name> <description>Output Compare 2 preload enable</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC2M</name> <description>Output Compare 2 mode</description> <bitOffset>12</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC2CE</name> <description>Output Compare 2 clear enable</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC1M_3</name> <description>Output Compare 1 mode - bit 3</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC2M_3</name> <description>Output Compare 2 mode - bit 3</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CCMR1_Input</name> <displayName>CCMR1_Input</displayName> <description>capture/compare mode register 1 (output mode)</description> <alternateRegister>CCMR1_Output</alternateRegister> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CC1S</name> <description>Capture/Compare 1 selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OC1FE</name> <description>Output Compare 1 fast enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC1PE</name> <description>Output Compare 1 preload enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC1M</name> <description>Output Compare 1 mode</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC1CE</name> <description>Output Compare 1 clear enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2S</name> <description>Capture/Compare 2 selection</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OC2FE</name> <description>Output Compare 2 fast enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC2PE</name> <description>Output Compare 2 preload enable</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC2M</name> <description>Output Compare 2 mode</description> <bitOffset>12</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC2CE</name> <description>Output Compare 2 clear enable</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CCMR2_Output</name> <displayName>CCMR2_Output</displayName> <description>capture/compare mode register 2 (output mode)</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CC3S</name> <description>Capture/Compare 3 selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OC3FE</name> <description>Output compare 3 fast enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC3PE</name> <description>Output compare 3 preload enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC3M</name> <description>Output compare 3 mode</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC3CE</name> <description>Output compare 3 clear enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4S</name> <description>Capture/Compare 4 selection</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OC4FE</name> <description>Output compare 4 fast enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC4PE</name> <description>Output compare 4 preload enable</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC4M</name> <description>Output compare 4 mode</description> <bitOffset>12</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC4CE</name> <description>Output compare 4 clear enable</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC3M_3</name> <description>Output Compare 3 mode - bit 3</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC4M_3</name> <description>Output Compare 4 mode - bit 3</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CCMR2_Input</name> <displayName>CCMR2_Input</displayName> <description>capture/compare mode register 2 (output mode)</description> <alternateRegister>CCMR2_Output</alternateRegister> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CC3S</name> <description>Capture/Compare 3 selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OC3FE</name> <description>Output compare 3 fast enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC3PE</name> <description>Output compare 3 preload enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC3M</name> <description>Output compare 3 mode</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC3CE</name> <description>Output compare 3 clear enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4S</name> <description>Capture/Compare 4 selection</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OC4FE</name> <description>Output compare 4 fast enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC4PE</name> <description>Output compare 4 preload enable</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC4M</name> <description>Output compare 4 mode</description> <bitOffset>12</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC4CE</name> <description>Output compare 4 clear enable</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CCER</name> <displayName>CCER</displayName> <description>capture/compare enable register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CC1E</name> <description>Capture/Compare 1 output enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1P</name> <description>Capture/Compare 1 output Polarity</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1NE</name> <description>Capture/Compare 1 complementary output enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1NP</name> <description>Capture/Compare 1 output Polarity</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2E</name> <description>Capture/Compare 2 output enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2P</name> <description>Capture/Compare 2 output Polarity</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2NE</name> <description>Capture/Compare 2 complementary output enable</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2NP</name> <description>Capture/Compare 2 output Polarity</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3E</name> <description>Capture/Compare 3 output enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3P</name> <description>Capture/Compare 3 output Polarity</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3NE</name> <description>Capture/Compare 3 complementary output enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3NP</name> <description>Capture/Compare 3 output Polarity</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4E</name> <description>Capture/Compare 4 output enable</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4P</name> <description>Capture/Compare 3 output Polarity</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4NP</name> <description>Capture/Compare 4 complementary output polarity</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC5E</name> <description>Capture/Compare 5 output enable</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC5P</name> <description>Capture/Compare 5 output polarity</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC6E</name> <description>Capture/Compare 6 output enable</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC6P</name> <description>Capture/Compare 6 output polarity</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CNT</name> <displayName>CNT</displayName> <description>counter</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <resetValue>0x00000000</resetValue> <fields> <field> <name>CNT</name> <description>counter value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> <access>read-write</access> </field> <field> <name>UIFCPY</name> <description>UIF copy</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> </fields> </register> <register> <name>PSC</name> <displayName>PSC</displayName> <description>prescaler</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>PSC</name> <description>Prescaler value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>ARR</name> <displayName>ARR</displayName> <description>auto-reload register</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ARR</name> <description>Auto-reload value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>RCR</name> <displayName>RCR</displayName> <description>repetition counter register</description> <addressOffset>0x30</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>REP</name> <description>Repetition counter value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CCR1</name> <displayName>CCR1</displayName> <description>capture/compare register 1</description> <addressOffset>0x34</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCR1</name> <description>Capture/Compare 1 value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CCR2</name> <displayName>CCR2</displayName> <description>capture/compare register 2</description> <addressOffset>0x38</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCR2</name> <description>Capture/Compare 2 value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CCR3</name> <displayName>CCR3</displayName> <description>capture/compare register 3</description> <addressOffset>0x3C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCR3</name> <description>Capture/Compare value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CCR4</name> <displayName>CCR4</displayName> <description>capture/compare register 4</description> <addressOffset>0x40</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCR4</name> <description>Capture/Compare value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>BDTR</name> <displayName>BDTR</displayName> <description>break and dead-time register</description> <addressOffset>0x44</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>DTG</name> <description>Dead-time generator setup</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>LOCK</name> <description>Lock configuration</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSSI</name> <description>Off-state selection for Idle mode</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OSSR</name> <description>Off-state selection for Run mode</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BKE</name> <description>Break enable</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BKP</name> <description>Break polarity</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AOE</name> <description>Automatic output enable</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MOE</name> <description>Main output enable</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BKF</name> <description>Break filter</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>BK2F</name> <description>Break 2 filter</description> <bitOffset>20</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>BK2E</name> <description>Break 2 enable</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BK2P</name> <description>Break 2 polarity</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BKDSRM</name> <description>Break Disarm</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BK2DSRM</name> <description>Break2 Disarm</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BKBID</name> <description>Break Bidirectional</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BK2ID</name> <description>Break2 bidirectional</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>DCR</name> <displayName>DCR</displayName> <description>DMA control register</description> <addressOffset>0x48</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>DBL</name> <description>DMA burst length</description> <bitOffset>8</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>DBA</name> <description>DMA base address</description> <bitOffset>0</bitOffset> <bitWidth>5</bitWidth> </field> </fields> </register> <register> <name>DMAR</name> <displayName>DMAR</displayName> <description>DMA address for full transfer</description> <addressOffset>0x4C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>DMAB</name> <description>DMA register for burst accesses</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>OR1</name> <displayName>OR1</displayName> <description>option register 1</description> <addressOffset>0x50</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>OCREF_CLR</name> <description>Ocref_clr source selection</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CCMR3_Output</name> <displayName>CCMR3_Output</displayName> <description>capture/compare mode register 2 (output mode)</description> <addressOffset>0x54</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OC6M_bit3</name> <description>Output Compare 6 mode bit 3</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC5M_bit3</name> <description>Output Compare 5 mode bit 3</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC6CE</name> <description>Output compare 6 clear enable</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC6M</name> <description>Output compare 6 mode</description> <bitOffset>12</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC6PE</name> <description>Output compare 6 preload enable</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC6FE</name> <description>Output compare 6 fast enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC5CE</name> <description>Output compare 5 clear enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC5M</name> <description>Output compare 5 mode</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC5PE</name> <description>Output compare 5 preload enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC5FE</name> <description>Output compare 5 fast enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CCR5</name> <displayName>CCR5</displayName> <description>capture/compare register 4</description> <addressOffset>0x58</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCR5</name> <description>Capture/Compare value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>GC5C1</name> <description>Group Channel 5 and Channel 1</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GC5C2</name> <description>Group Channel 5 and Channel 2</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GC5C3</name> <description>Group Channel 5 and Channel 3</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CCR6</name> <displayName>CCR6</displayName> <description>capture/compare register 4</description> <addressOffset>0x5C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCR6</name> <description>Capture/Compare value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>AF1</name> <displayName>AF1</displayName> <description>DMA address for full transfer</description> <addressOffset>0x60</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000001</resetValue> <fields> <field> <name>BKINE</name> <description>BRK BKIN input enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BKCMP1E</name> <description>BRK COMP1 enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BKCMP2E</name> <description>BRK COMP2 enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BKINP</name> <description>BRK BKIN input polarity</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BKCMP1P</name> <description>BRK COMP1 input polarity</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BKCMP2P</name> <description>BRK COMP2 input polarity</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ETRSEL</name> <description>ETR source selection</description> <bitOffset>14</bitOffset> <bitWidth>3</bitWidth> </field> </fields> </register> <register> <name>AF2</name> <displayName>AF2</displayName> <description>DMA address for full transfer</description> <addressOffset>0x64</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000001</resetValue> <fields> <field> <name>BK2INE</name> <description>BRK2 BKIN input enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BK2CMP1E</name> <description>BRK2 COMP1 enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BK2CMP2E</name> <description>BRK2 COMP2 enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BK2DFBK0E</name> <description>BRK2 DFSDM_BREAK0 enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BK2INP</name> <description>BRK2 BKIN input polarity</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BK2CMP1P</name> <description>BRK2 COMP1 input polarity</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BK2CMP2P</name> <description>BRK2 COMP2 input polarity</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>TISEL</name> <displayName>TISEL</displayName> <description>TIM1 timer input selection register</description> <addressOffset>0x68</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TI1SEL3_0</name> <description>selects TI1[0] to TI1[15] input</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>TI2SEL3_0</name> <description>selects TI2[0] to TI2[15] input</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>TI3SEL3_0</name> <description>selects TI3[0] to TI3[15] input</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>TI4SEL3_0</name> <description>selects TI4[0] to TI4[15] input</description> <bitOffset>24</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>ADC</name> <description>Analog to Digital Converter instance 1</description> <groupName>ADC</groupName> <baseAddress>0x40012400</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>ADC_COMP</name> <description>ADC and COMP interrupts</description> <value>12</value> </interrupt> <registers> <register> <name>ISR</name> <displayName>ISR</displayName> <description>ADC interrupt and status register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCRDY</name> <description>Channel Configuration Ready flag</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EOCAL</name> <description>End Of Calibration flag</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AWD3</name> <description>ADC analog watchdog 3 flag</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AWD2</name> <description>ADC analog watchdog 2 flag</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AWD1</name> <description>ADC analog watchdog 1 flag</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OVR</name> <description>ADC group regular overrun flag</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EOS</name> <description>ADC group regular end of sequence conversions flag</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EOC</name> <description>ADC group regular end of unitary conversion flag</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EOSMP</name> <description>ADC group regular end of sampling flag</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADRDY</name> <description>ADC ready flag</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>IER</name> <displayName>IER</displayName> <description>ADC interrupt enable register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCRDYIE</name> <description>Channel Configuration Ready Interrupt enable</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EOCALIE</name> <description>End of calibration interrupt enable</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AWD3IE</name> <description>ADC analog watchdog 3 interrupt</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AWD2IE</name> <description>ADC analog watchdog 2 interrupt</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AWD1IE</name> <description>ADC analog watchdog 1 interrupt</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OVRIE</name> <description>ADC group regular overrun interrupt</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EOSIE</name> <description>ADC group regular end of sequence conversions interrupt</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EOCIE</name> <description>ADC group regular end of unitary conversion interrupt</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EOSMPIE</name> <description>ADC group regular end of sampling interrupt</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADRDYIE</name> <description>ADC ready interrupt</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CR</name> <displayName>CR</displayName> <description>ADC control register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ADCAL</name> <description>ADC calibration</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADVREGEN</name> <description>ADC voltage regulator enable</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADSTP</name> <description>ADC group regular conversion stop</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADSTART</name> <description>ADC group regular conversion start</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADDIS</name> <description>ADC disable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADEN</name> <description>ADC enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CFGR1</name> <displayName>CFGR1</displayName> <description>ADC configuration register 1</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>AWDCH1CH</name> <description>ADC analog watchdog 1 monitored channel selection</description> <bitOffset>26</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>AWD1EN</name> <description>ADC analog watchdog 1 enable on scope ADC group regular</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AWD1SGL</name> <description>ADC analog watchdog 1 monitoring a single channel or all channels</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHSELRMOD</name> <description>Mode selection of the ADC_CHSELR register</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DISCEN</name> <description>ADC group regular sequencer discontinuous mode</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AUTOFF</name> <description>Auto-off mode</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WAIT</name> <description>Wait conversion mode</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CONT</name> <description>ADC group regular continuous conversion mode</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OVRMOD</name> <description>ADC group regular overrun configuration</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EXTEN</name> <description>ADC group regular external trigger polarity</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>EXTSEL</name> <description>ADC group regular external trigger source</description> <bitOffset>6</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>ALIGN</name> <description>ADC data alignement</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RES</name> <description>ADC data resolution</description> <bitOffset>3</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>SCANDIR</name> <description>Scan sequence direction</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMACFG</name> <description>ADC DMA transfer configuration</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMAEN</name> <description>ADC DMA transfer enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CFGR2</name> <displayName>CFGR2</displayName> <description>ADC configuration register 2</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CKMODE</name> <description>ADC clock mode</description> <bitOffset>30</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>LFTRIG</name> <description>Low frequency trigger mode enable</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TOVS</name> <description>ADC oversampling discontinuous mode (triggered mode) for ADC group regular</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OVSS</name> <description>ADC oversampling shift</description> <bitOffset>5</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>OVSR</name> <description>ADC oversampling ratio</description> <bitOffset>2</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OVSE</name> <description>ADC oversampler enable on scope ADC group regular</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SMPR</name> <displayName>SMPR</displayName> <description>ADC sampling time register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SMP1</name> <description>Sampling time selection</description> <bitOffset>0</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>SMP2</name> <description>Sampling time selection</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>SMPSEL</name> <description>Channel sampling time selection</description> <bitOffset>8</bitOffset> <bitWidth>19</bitWidth> </field> </fields> </register> <register> <name>AWD1TR</name> <displayName>AWD1TR</displayName> <description>watchdog threshold register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0FFF0000</resetValue> <fields> <field> <name>HT1</name> <description>ADC analog watchdog 1 threshold high</description> <bitOffset>16</bitOffset> <bitWidth>12</bitWidth> </field> <field> <name>LT1</name> <description>ADC analog watchdog 1 threshold low</description> <bitOffset>0</bitOffset> <bitWidth>12</bitWidth> </field> </fields> </register> <register> <name>AWD2TR</name> <displayName>AWD2TR</displayName> <description>watchdog threshold register</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0FFF0000</resetValue> <fields> <field> <name>HT2</name> <description>ADC analog watchdog 2 threshold high</description> <bitOffset>16</bitOffset> <bitWidth>12</bitWidth> </field> <field> <name>LT2</name> <description>ADC analog watchdog 2 threshold low</description> <bitOffset>0</bitOffset> <bitWidth>12</bitWidth> </field> </fields> </register> <register> <name>CHSELR</name> <displayName>CHSELR</displayName> <description>channel selection register</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0FFF0000</resetValue> <fields> <field> <name>CHSEL</name> <description>Channel-x selection</description> <bitOffset>0</bitOffset> <bitWidth>19</bitWidth> </field> </fields> </register> <register> <name>CHSELR_1</name> <displayName>CHSELR_1</displayName> <description>channel selection register CHSELRMOD = 1 in ADC_CFGR1</description> <alternateRegister>CHSELR</alternateRegister> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SQ1</name> <description>conversion of the sequence</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>SQ2</name> <description>conversion of the sequence</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>SQ3</name> <description>conversion of the sequence</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>SQ4</name> <description>conversion of the sequence</description> <bitOffset>12</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>SQ5</name> <description>conversion of the sequence</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>SQ6</name> <description>conversion of the sequence</description> <bitOffset>20</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>SQ7</name> <description>conversion of the sequence</description> <bitOffset>24</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>SQ8</name> <description>conversion of the sequence</description> <bitOffset>28</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>AWD3TR</name> <displayName>AWD3TR</displayName> <description>watchdog threshold register</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0FFF0000</resetValue> <fields> <field> <name>HT3</name> <description>ADC analog watchdog 3 threshold high</description> <bitOffset>16</bitOffset> <bitWidth>12</bitWidth> </field> <field> <name>LT3</name> <description>ADC analog watchdog 3 threshold high</description> <bitOffset>0</bitOffset> <bitWidth>12</bitWidth> </field> </fields> </register> <register> <name>DR</name> <displayName>DR</displayName> <description>ADC group regular conversion data register</description> <addressOffset>0x40</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>regularDATA</name> <description>ADC group regular conversion data</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>AWD2CR</name> <displayName>AWD2CR</displayName> <description>ADC analog watchdog 2 configuration register</description> <addressOffset>0xA0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>AWD2CH</name> <description>ADC analog watchdog 2 monitored channel selection</description> <bitOffset>0</bitOffset> <bitWidth>19</bitWidth> </field> </fields> </register> <register> <name>AWD3CR</name> <displayName>AWD3CR</displayName> <description>ADC analog watchdog 3 configuration register</description> <addressOffset>0xA4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>AWD3CH</name> <description>ADC analog watchdog 3 monitored channel selection</description> <bitOffset>0</bitOffset> <bitWidth>19</bitWidth> </field> </fields> </register> <register> <name>CALFACT</name> <displayName>CALFACT</displayName> <description>ADC calibration factors register</description> <addressOffset>0xB4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CALFACT</name> <description>ADC calibration factor in single-ended mode</description> <bitOffset>0</bitOffset> <bitWidth>7</bitWidth> </field> </fields> </register> <register> <name>CCR</name> <displayName>CCR</displayName> <description>ADC common control register</description> <addressOffset>0x308</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PRESC</name> <description>ADC prescaler</description> <bitOffset>18</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>VREFEN</name> <description>VREFINT enable</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TSEN</name> <description>Temperature sensor enable</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>VBATEN</name> <description>VBAT enable</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>SYSCFG</name> <description>System configuration controller</description> <groupName>SYSCFG</groupName> <baseAddress>0x40010000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x30</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>CFGR1</name> <displayName>CFGR1</displayName> <description>SYSCFG configuration register 1</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>I2C_PAx_FMP</name> <description>Fast Mode Plus (FM+) driving capability activation bits</description> <bitOffset>22</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>I2C2_FMP</name> <description>FM+ driving capability activation for I2C2</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>I2C1_FMP</name> <description>FM+ driving capability activation for I2C1</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>I2C_PBx_FMP</name> <description>Fast Mode Plus (FM+) driving capability activation bits</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>BOOSTEN</name> <description>I/O analog switch voltage booster enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IR_MOD</name> <description>IR Modulation Envelope signal selection.</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>IR_POL</name> <description>IR output polarity selection</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PA11_PA12_RMP</name> <description>PA11 and PA12 remapping bit.</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MEM_MODE</name> <description>Memory mapping selection bits</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CFGR2</name> <displayName>CFGR2</displayName> <description>SYSCFG configuration register 1</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>LOCKUP_LOCK</name> <description>Cortex-M0+ LOCKUP bit enable bit</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SRAM_PARITY_LOCK</name> <description>SRAM parity lock bit</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PVD_LOCK</name> <description>PVD lock enable bit</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ECC_LOCK</name> <description>ECC error lock bit</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SRAM_PEF</name> <description>SRAM parity error flag</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PA1_CDEN</name> <description>PA1_CDEN</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PA3_CDEN</name> <description>PA3_CDEN</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PA5_CDEN</name> <description>PA5_CDEN</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PA6_CDEN</name> <description>PA6_CDEN</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PA13_CDEN</name> <description>PA13_CDEN</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PB0_CDEN</name> <description>PB0_CDEN</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PB1_CDEN</name> <description>PB1_CDEN</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PB2_CDEN</name> <description>PB2_CDEN</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>TAMP</name> <description>Tamper and backup registers</description> <groupName>TAMP</groupName> <baseAddress>0x4000B000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>CR1</name> <displayName>CR1</displayName> <description>control register 1</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0xFFFF0000</resetValue> <fields> <field> <name>TAMP1E</name> <description>TAMP1E</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TAMP2E</name> <description>TAMP2E</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ITAMP1E</name> <description>ITAMP1E</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ITAMP3E</name> <description>ITAMP3E</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ITAMP4E</name> <description>ITAMP4E</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ITAMP5E</name> <description>ITAMP5E</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ITAMP6E</name> <description>ITAMP6E</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CR2</name> <displayName>CR2</displayName> <description>control register 2</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TAMP1NOER</name> <description>TAMP1NOER</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TAMP2NOER</name> <description>TAMP2NOER</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TAMP1MSK</name> <description>TAMP1MSK</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TAMP2MSK</name> <description>TAMP2MSK</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TAMP1TRG</name> <description>TAMP1TRG</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TAMP2TRG</name> <description>TAMP2TRG</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>FLTCR</name> <displayName>FLTCR</displayName> <description>TAMP filter control register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TAMPFREQ</name> <description>TAMPFREQ</description> <bitOffset>0</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>TAMPFLT</name> <description>TAMPFLT</description> <bitOffset>3</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>TAMPPRCH</name> <description>TAMPPRCH</description> <bitOffset>5</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>TAMPPUDIS</name> <description>TAMPPUDIS</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>IER</name> <displayName>IER</displayName> <description>TAMP interrupt enable register</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TAMP1IE</name> <description>TAMP1IE</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TAMP2IE</name> <description>TAMP2IE</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ITAMP1IE</name> <description>ITAMP1IE</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ITAMP3IE</name> <description>ITAMP3IE</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ITAMP4IE</name> <description>ITAMP4IE</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ITAMP5IE</name> <description>ITAMP5IE</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ITAMP6IE</name> <description>ITAMP6IE</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SR</name> <displayName>SR</displayName> <description>TAMP status register</description> <addressOffset>0x30</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TAMP1F</name> <description>TAMP1F</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TAMP2F</name> <description>TAMP2F</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ITAMP1F</name> <description>ITAMP1F</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ITAMP3F</name> <description>ITAMP3F</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ITAMP4F</name> <description>ITAMP4F</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ITAMP5F</name> <description>ITAMP5F</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ITAMP6F</name> <description>ITAMP6F</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ITAMP7F</name> <description>ITAMP7F</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>MISR</name> <displayName>MISR</displayName> <description>TAMP masked interrupt status register</description> <addressOffset>0x34</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TAMP1MF</name> <description>TAMP1MF:</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TAMP2MF</name> <description>TAMP2MF</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ITAMP1MF</name> <description>ITAMP1MF</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ITAMP3MF</name> <description>ITAMP3MF</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ITAMP4MF</name> <description>ITAMP4MF</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ITAMP5MF</name> <description>ITAMP5MF</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ITAMP6MF</name> <description>ITAMP6MF</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SCR</name> <displayName>SCR</displayName> <description>TAMP status clear register</description> <addressOffset>0x3C</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CTAMP1F</name> <description>CTAMP1F</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTAMP2F</name> <description>CTAMP2F</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CITAMP1F</name> <description>CITAMP1F</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CITAMP3F</name> <description>CITAMP3F</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CITAMP4F</name> <description>CITAMP4F</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CITAMP5F</name> <description>CITAMP5F</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CITAMP6F</name> <description>CITAMP6F</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CITAMP7F</name> <description>CITAMP7F</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>BKP0R</name> <displayName>BKP0R</displayName> <description>TAMP backup register</description> <addressOffset>0x100</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BKP1R</name> <displayName>BKP1R</displayName> <description>TAMP backup register</description> <addressOffset>0x104</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BKP2R</name> <displayName>BKP2R</displayName> <description>TAMP backup register</description> <addressOffset>0x108</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BKP3R</name> <displayName>BKP3R</displayName> <description>TAMP backup register</description> <addressOffset>0x10C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BKP4R</name> <displayName>BKP4R</displayName> <description>TAMP backup register</description> <addressOffset>0x110</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>I2C1</name> <description>Inter-integrated circuit</description> <groupName>I2C</groupName> <baseAddress>0x40005400</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>I2C1</name> <description>I2C1 global interrupt</description> <value>23</value> </interrupt> <registers> <register> <name>CR1</name> <displayName>CR1</displayName> <description>Control register 1</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PE</name> <description>Peripheral enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXIE</name> <description>TX Interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RXIE</name> <description>RX Interrupt enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADDRIE</name> <description>Address match interrupt enable (slave only)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NACKIE</name> <description>Not acknowledge received interrupt enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STOPIE</name> <description>STOP detection Interrupt enable</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIE</name> <description>Transfer Complete interrupt enable</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ERRIE</name> <description>Error interrupts enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DNF</name> <description>Digital noise filter</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>ANFOFF</name> <description>Analog noise filter OFF</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXDMAEN</name> <description>DMA transmission requests enable</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RXDMAEN</name> <description>DMA reception requests enable</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SBC</name> <description>Slave byte control</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NOSTRETCH</name> <description>Clock stretching disable</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WUPEN</name> <description>Wakeup from STOP enable</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GCEN</name> <description>General call enable</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SMBHEN</name> <description>SMBus Host address enable</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SMBDEN</name> <description>SMBus Device Default address enable</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ALERTEN</name> <description>SMBUS alert enable</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PECEN</name> <description>PEC enable</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CR2</name> <displayName>CR2</displayName> <description>Control register 2</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PECBYTE</name> <description>Packet error checking byte</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AUTOEND</name> <description>Automatic end mode (master mode)</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RELOAD</name> <description>NBYTES reload mode</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NBYTES</name> <description>Number of bytes</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>NACK</name> <description>NACK generation (slave mode)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STOP</name> <description>Stop generation (master mode)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>START</name> <description>Start generation</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HEAD10R</name> <description>10-bit address header only read direction (master receiver mode)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADD10</name> <description>10-bit addressing mode (master mode)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RD_WRN</name> <description>Transfer direction (master mode)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SADD</name> <description>Slave address bit (master mode)</description> <bitOffset>0</bitOffset> <bitWidth>10</bitWidth> </field> </fields> </register> <register> <name>OAR1</name> <displayName>OAR1</displayName> <description>Own address register 1</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OA1_0</name> <description>Interface address</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OA1_7_1</name> <description>Interface address</description> <bitOffset>1</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>OA1_8_9</name> <description>Interface address</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OA1MODE</name> <description>Own Address 1 10-bit mode</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OA1EN</name> <description>Own Address 1 enable</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OAR2</name> <displayName>OAR2</displayName> <description>Own address register 2</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OA2</name> <description>Interface address</description> <bitOffset>1</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>OA2MSK</name> <description>Own Address 2 masks</description> <bitOffset>8</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OA2EN</name> <description>Own Address 2 enable</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>TIMINGR</name> <displayName>TIMINGR</displayName> <description>Timing register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SCLL</name> <description>SCL low period (master mode)</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>SCLH</name> <description>SCL high period (master mode)</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>SDADEL</name> <description>Data hold time</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>SCLDEL</name> <description>Data setup time</description> <bitOffset>20</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>PRESC</name> <description>Timing prescaler</description> <bitOffset>28</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>TIMEOUTR</name> <displayName>TIMEOUTR</displayName> <description>Status register 1</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TIMEOUTA</name> <description>Bus timeout A</description> <bitOffset>0</bitOffset> <bitWidth>12</bitWidth> </field> <field> <name>TIDLE</name> <description>Idle clock timeout detection</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIMOUTEN</name> <description>Clock timeout enable</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIMEOUTB</name> <description>Bus timeout B</description> <bitOffset>16</bitOffset> <bitWidth>12</bitWidth> </field> <field> <name>TEXTEN</name> <description>Extended clock timeout enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ISR</name> <displayName>ISR</displayName> <description>Interrupt and Status register</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <resetValue>0x00000001</resetValue> <fields> <field> <name>ADDCODE</name> <description>Address match code (Slave mode)</description> <bitOffset>17</bitOffset> <bitWidth>7</bitWidth> <access>read-only</access> </field> <field> <name>DIR</name> <description>Transfer direction (Slave mode)</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>BUSY</name> <description>Bus busy</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>ALERT</name> <description>SMBus alert</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>TIMEOUT</name> <description>Timeout or t_low detection flag</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>PECERR</name> <description>PEC Error in reception</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>OVR</name> <description>Overrun/Underrun (slave mode)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>ARLO</name> <description>Arbitration lost</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>BERR</name> <description>Bus error</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>TCR</name> <description>Transfer Complete Reload</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>TC</name> <description>Transfer Complete (master mode)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>STOPF</name> <description>Stop detection flag</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>NACKF</name> <description>Not acknowledge received flag</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>ADDR</name> <description>Address matched (slave mode)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>RXNE</name> <description>Receive data register not empty (receivers)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>TXIS</name> <description>Transmit interrupt status (transmitters)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TXE</name> <description>Transmit data register empty (transmitters)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>ICR</name> <displayName>ICR</displayName> <description>Interrupt clear register</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ALERTCF</name> <description>Alert flag clear</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIMOUTCF</name> <description>Timeout detection flag clear</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PECCF</name> <description>PEC Error flag clear</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OVRCF</name> <description>Overrun/Underrun flag clear</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ARLOCF</name> <description>Arbitration lost flag clear</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BERRCF</name> <description>Bus error flag clear</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STOPCF</name> <description>Stop detection flag clear</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NACKCF</name> <description>Not Acknowledge flag clear</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADDRCF</name> <description>Address Matched flag clear</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>PECR</name> <displayName>PECR</displayName> <description>PEC register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PEC</name> <description>Packet error checking register</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>RXDR</name> <displayName>RXDR</displayName> <description>Receive data register</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>RXDATA</name> <description>8-bit receive data</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>TXDR</name> <displayName>TXDR</displayName> <description>Transmit data register</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TXDATA</name> <description>8-bit transmit data</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral derivedFrom="I2C1"> <name>I2C2</name> <baseAddress>0x40005800</baseAddress> <interrupt> <name>I2C2</name> <description>I2C2 global interrupt</description> <value>24</value> </interrupt> </peripheral> <peripheral> <name>RTC</name> <description>Real-time clock</description> <groupName>RTC</groupName> <baseAddress>0x40002800</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>RTC_TAMP</name> <description>RTC and TAMP interrupts</description> <value>2</value> </interrupt> <registers> <register> <name>TR</name> <displayName>TR</displayName> <description>time register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PM</name> <description>AM/PM notation</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HT</name> <description>Hour tens in BCD format</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>HU</name> <description>Hour units in BCD format</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>MNT</name> <description>Minute tens in BCD format</description> <bitOffset>12</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>MNU</name> <description>Minute units in BCD format</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>ST</name> <description>Second tens in BCD format</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>SU</name> <description>Second units in BCD format</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>DR</name> <displayName>DR</displayName> <description>date register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00002101</resetValue> <fields> <field> <name>YT</name> <description>Year tens in BCD format</description> <bitOffset>20</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>YU</name> <description>Year units in BCD format</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>WDU</name> <description>Week day units</description> <bitOffset>13</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>MT</name> <description>Month tens in BCD format</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MU</name> <description>Month units in BCD format</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>DT</name> <description>Date tens in BCD format</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DU</name> <description>Date units in BCD format</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>SSR</name> <displayName>SSR</displayName> <description>sub second register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SS</name> <description>Sub second value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>ICSR</name> <displayName>ICSR</displayName> <description>initialization and status register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <resetValue>0x00000007</resetValue> <fields> <field> <name>ALRAWF</name> <description>Alarm A write flag</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>ALRBWF</name> <description>Alarm B write flag</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>WUTWF</name> <description>Wakeup timer write flag</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>SHPF</name> <description>Shift operation pending</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>INITS</name> <description>Initialization status flag</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>RSF</name> <description>Registers synchronization flag</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>INITF</name> <description>Initialization flag</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>INIT</name> <description>Initialization mode</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>RECALPF</name> <description>Recalibration pending Flag</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> </fields> </register> <register> <name>PRER</name> <displayName>PRER</displayName> <description>prescaler register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x007F00FF</resetValue> <fields> <field> <name>PREDIV_A</name> <description>Asynchronous prescaler factor</description> <bitOffset>16</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>PREDIV_S</name> <description>Synchronous prescaler factor</description> <bitOffset>0</bitOffset> <bitWidth>15</bitWidth> </field> </fields> </register> <register> <name>WUTR</name> <displayName>WUTR</displayName> <description>wakeup timer register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000FFFF</resetValue> <fields> <field> <name>WUT</name> <description>Wakeup auto-reload value bits</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CR</name> <displayName>CR</displayName> <description>control register</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>WUCKSEL</name> <description>WUCKSEL</description> <bitOffset>0</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>TSEDGE</name> <description>TSEDGE</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>REFCKON</name> <description>REFCKON</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BYPSHAD</name> <description>BYPSHAD</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FMT</name> <description>FMT</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ALRAE</name> <description>ALRAE</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ALRBE</name> <description>ALRBE</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WUTE</name> <description>WUTE</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TSE</name> <description>TSE</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ALRAIE</name> <description>ALRAIE</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ALRBIE</name> <description>ALRBIE</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WUTIE</name> <description>WUTIE</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TSIE</name> <description>TSIE</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADD1H</name> <description>ADD1H</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SUB1H</name> <description>SUB1H</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BKP</name> <description>BKP</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>COSEL</name> <description>COSEL</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>POL</name> <description>POL</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OSEL</name> <description>OSEL</description> <bitOffset>21</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>COE</name> <description>COE</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ITSE</name> <description>ITSE</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TAMPTS</name> <description>TAMPTS</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TAMPOE</name> <description>TAMPOE</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TAMPALRM_PU</name> <description>TAMPALRM_PU</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TAMPALRM_TYPE</name> <description>TAMPALRM_TYPE</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OUT2EN</name> <description>OUT2EN</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>WPR</name> <displayName>WPR</displayName> <description>write protection register</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>KEY</name> <description>Write protection key</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>CALR</name> <displayName>CALR</displayName> <description>calibration register</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CALP</name> <description>Increase frequency of RTC by 488.5 ppm</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CALW8</name> <description>Use an 8-second calibration cycle period</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CALW16</name> <description>Use a 16-second calibration cycle period</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CALM</name> <description>Calibration minus</description> <bitOffset>0</bitOffset> <bitWidth>9</bitWidth> </field> </fields> </register> <register> <name>SHIFTR</name> <displayName>SHIFTR</displayName> <description>shift control register</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ADD1S</name> <description>Add one second</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SUBFS</name> <description>Subtract a fraction of a second</description> <bitOffset>0</bitOffset> <bitWidth>15</bitWidth> </field> </fields> </register> <register> <name>TSTR</name> <displayName>TSTR</displayName> <description>time stamp time register</description> <addressOffset>0x30</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SU</name> <description>Second units in BCD format</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>ST</name> <description>Second tens in BCD format</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>MNU</name> <description>Minute units in BCD format</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>MNT</name> <description>Minute tens in BCD format</description> <bitOffset>12</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>HU</name> <description>Hour units in BCD format</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>HT</name> <description>Hour tens in BCD format</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PM</name> <description>AM/PM notation</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>TSDR</name> <displayName>TSDR</displayName> <description>time stamp date register</description> <addressOffset>0x34</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>WDU</name> <description>Week day units</description> <bitOffset>13</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>MT</name> <description>Month tens in BCD format</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MU</name> <description>Month units in BCD format</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>DT</name> <description>Date tens in BCD format</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DU</name> <description>Date units in BCD format</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>TSSSR</name> <displayName>TSSSR</displayName> <description>timestamp sub second register</description> <addressOffset>0x38</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SS</name> <description>Sub second value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>ALRMAR</name> <displayName>ALRMAR</displayName> <description>alarm A register</description> <addressOffset>0x40</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MSK4</name> <description>Alarm A date mask</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WDSEL</name> <description>Week day selection</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DT</name> <description>Date tens in BCD format</description> <bitOffset>28</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DU</name> <description>Date units or day in BCD format</description> <bitOffset>24</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>MSK3</name> <description>Alarm A hours mask</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PM</name> <description>AM/PM notation</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HT</name> <description>Hour tens in BCD format</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>HU</name> <description>Hour units in BCD format</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>MSK2</name> <description>Alarm A minutes mask</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MNT</name> <description>Minute tens in BCD format</description> <bitOffset>12</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>MNU</name> <description>Minute units in BCD format</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>MSK1</name> <description>Alarm A seconds mask</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ST</name> <description>Second tens in BCD format</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>SU</name> <description>Second units in BCD format</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>ALRMASSR</name> <displayName>ALRMASSR</displayName> <description>alarm A sub second register</description> <addressOffset>0x44</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MASKSS</name> <description>Mask the most-significant bits starting at this bit</description> <bitOffset>24</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>SS</name> <description>Sub seconds value</description> <bitOffset>0</bitOffset> <bitWidth>15</bitWidth> </field> </fields> </register> <register> <name>ALRMBR</name> <displayName>ALRMBR</displayName> <description>alarm B register</description> <addressOffset>0x48</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MSK4</name> <description>Alarm B date mask</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WDSEL</name> <description>Week day selection</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DT</name> <description>Date tens in BCD format</description> <bitOffset>28</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DU</name> <description>Date units or day in BCD format</description> <bitOffset>24</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>MSK3</name> <description>Alarm B hours mask</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PM</name> <description>AM/PM notation</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HT</name> <description>Hour tens in BCD format</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>HU</name> <description>Hour units in BCD format</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>MSK2</name> <description>Alarm B minutes mask</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MNT</name> <description>Minute tens in BCD format</description> <bitOffset>12</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>MNU</name> <description>Minute units in BCD format</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>MSK1</name> <description>Alarm B seconds mask</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ST</name> <description>Second tens in BCD format</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>SU</name> <description>Second units in BCD format</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>ALRMBSSR</name> <displayName>ALRMBSSR</displayName> <description>alarm B sub second register</description> <addressOffset>0x4C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MASKSS</name> <description>Mask the most-significant bits starting at this bit</description> <bitOffset>24</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>SS</name> <description>Sub seconds value</description> <bitOffset>0</bitOffset> <bitWidth>15</bitWidth> </field> </fields> </register> <register> <name>SR</name> <displayName>SR</displayName> <description>status register</description> <addressOffset>0x50</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ALRAF</name> <description>ALRAF</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ALRBF</name> <description>ALRBF</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WUTF</name> <description>WUTF</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TSF</name> <description>TSF</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TSOVF</name> <description>TSOVF</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ITSF</name> <description>ITSF</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>MISR</name> <displayName>MISR</displayName> <description>masked interrupt status register</description> <addressOffset>0x54</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ALRAMF</name> <description>ALRAMF</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ALRBMF</name> <description>ALRBMF</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WUTMF</name> <description>WUTMF</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TSMF</name> <description>TSMF</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TSOVMF</name> <description>TSOVMF</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ITSMF</name> <description>ITSMF</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SCR</name> <displayName>SCR</displayName> <description>status clear register</description> <addressOffset>0x5C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CALRAF</name> <description>CALRAF</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CALRBF</name> <description>CALRBF</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CWUTF</name> <description>CWUTF</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTSF</name> <description>CTSF</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTSOVF</name> <description>CTSOVF</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CITSF</name> <description>CITSF</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>TIM14</name> <description>General purpose timers</description> <groupName>TIM</groupName> <baseAddress>0x40002000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>TIM14</name> <description>TIM14 global interrupt</description> <value>19</value> </interrupt> <registers> <register> <name>CR1</name> <displayName>CR1</displayName> <description>control register 1</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>UIFREMAP</name> <description>UIF status bit remapping</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CKD</name> <description>Clock division</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>ARPE</name> <description>Auto-reload preload enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OPM</name> <description>One-pulse mode</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>URS</name> <description>Update request source</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UDIS</name> <description>Update disable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CEN</name> <description>Counter enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>DIER</name> <displayName>DIER</displayName> <description>DMA/Interrupt enable register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CC1IE</name> <description>Capture/Compare 1 interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UIE</name> <description>Update interrupt enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SR</name> <displayName>SR</displayName> <description>status register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CC1OF</name> <description>Capture/Compare 1 overcapture flag</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1IF</name> <description>Capture/compare 1 interrupt flag</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UIF</name> <description>Update interrupt flag</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>EGR</name> <displayName>EGR</displayName> <description>event generation register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CC1G</name> <description>Capture/compare 1 generation</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UG</name> <description>Update generation</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CCMR1_Output</name> <displayName>CCMR1_Output</displayName> <description>capture/compare mode register 1 (output mode)</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CC1S</name> <description>CC1S</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OC1FE</name> <description>OC1FE</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC1PE</name> <description>OC1PE</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC1M</name> <description>OC1M</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC1CE</name> <description>OC1CE</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC1M_3</name> <description>Output Compare 1 mode - bit 3</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CCMR1_Input</name> <displayName>CCMR1_Input</displayName> <description>capture/compare mode register 1 (input mode)</description> <alternateRegister>CCMR1_Output</alternateRegister> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IC1F</name> <description>Input capture 1 filter</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>ICPCS</name> <description>Input capture 1 prescaler</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CC1S</name> <description>Capture/Compare 1 selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CCER</name> <displayName>CCER</displayName> <description>capture/compare enable register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CC1NP</name> <description>Capture/Compare 1 output Polarity</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1P</name> <description>Capture/Compare 1 output Polarity</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1E</name> <description>Capture/Compare 1 output enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CNT</name> <displayName>CNT</displayName> <description>counter</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CNT</name> <description>low counter value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>UIFCPY</name> <description>UIF Copy</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>PSC</name> <displayName>PSC</displayName> <description>prescaler</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>PSC</name> <description>Prescaler value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>ARR</name> <displayName>ARR</displayName> <description>auto-reload register</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ARR</name> <description>Low Auto-reload value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CCR1</name> <displayName>CCR1</displayName> <description>capture/compare register 1</description> <addressOffset>0x34</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCR1</name> <description>Low Capture/Compare 1 value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>TISEL</name> <displayName>TISEL</displayName> <description>TIM timer input selection register</description> <addressOffset>0x68</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>TISEL</name> <description>TI1[0] to TI1[15] input selection</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>TIM2</name> <description>General-purpose-timers</description> <groupName>TIM</groupName> <baseAddress>0x40000000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>TIM2</name> <description>TIM2 global interrupt</description> <value>15</value> </interrupt> <interrupt> <name>TIM3</name> <description>TIM3 global interrupt</description> <value>16</value> </interrupt> <registers> <register> <name>CR1</name> <displayName>CR1</displayName> <description>control register 1</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>UIFREMAP</name> <description>UIF status bit remapping</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CKD</name> <description>Clock division</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>ARPE</name> <description>Auto-reload preload enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CMS</name> <description>Center-aligned mode selection</description> <bitOffset>5</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DIR</name> <description>Direction</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OPM</name> <description>One-pulse mode</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>URS</name> <description>Update request source</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UDIS</name> <description>Update disable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CEN</name> <description>Counter enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CR2</name> <displayName>CR2</displayName> <description>control register 2</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>TI1S</name> <description>TI1 selection</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MMS</name> <description>Master mode selection</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>CCDS</name> <description>Capture/compare DMA selection</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SMCR</name> <displayName>SMCR</displayName> <description>slave mode control register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>TS_4_3</name> <description>Trigger selection</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>SMS_3</name> <description>Slave mode selection - bit 3</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ETP</name> <description>External trigger polarity</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ECE</name> <description>External clock enable</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ETPS</name> <description>External trigger prescaler</description> <bitOffset>12</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>ETF</name> <description>External trigger filter</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>MSM</name> <description>Master/Slave mode</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TS</name> <description>Trigger selection</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OCCS</name> <description>OCREF clear selection</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SMS</name> <description>Slave mode selection</description> <bitOffset>0</bitOffset> <bitWidth>3</bitWidth> </field> </fields> </register> <register> <name>DIER</name> <displayName>DIER</displayName> <description>DMA/Interrupt enable register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>TDE</name> <description>Trigger DMA request enable</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4DE</name> <description>Capture/Compare 4 DMA request enable</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3DE</name> <description>Capture/Compare 3 DMA request enable</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2DE</name> <description>Capture/Compare 2 DMA request enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1DE</name> <description>Capture/Compare 1 DMA request enable</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UDE</name> <description>Update DMA request enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIE</name> <description>Trigger interrupt enable</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4IE</name> <description>Capture/Compare 4 interrupt enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3IE</name> <description>Capture/Compare 3 interrupt enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2IE</name> <description>Capture/Compare 2 interrupt enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1IE</name> <description>Capture/Compare 1 interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UIE</name> <description>Update interrupt enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SR</name> <displayName>SR</displayName> <description>status register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CC4OF</name> <description>Capture/Compare 4 overcapture flag</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3OF</name> <description>Capture/Compare 3 overcapture flag</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2OF</name> <description>Capture/compare 2 overcapture flag</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1OF</name> <description>Capture/Compare 1 overcapture flag</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIF</name> <description>Trigger interrupt flag</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4IF</name> <description>Capture/Compare 4 interrupt flag</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3IF</name> <description>Capture/Compare 3 interrupt flag</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2IF</name> <description>Capture/Compare 2 interrupt flag</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1IF</name> <description>Capture/compare 1 interrupt flag</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UIF</name> <description>Update interrupt flag</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>EGR</name> <displayName>EGR</displayName> <description>event generation register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x0000</resetValue> <fields> <field> <name>TG</name> <description>Trigger generation</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4G</name> <description>Capture/compare 4 generation</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3G</name> <description>Capture/compare 3 generation</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2G</name> <description>Capture/compare 2 generation</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1G</name> <description>Capture/compare 1 generation</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UG</name> <description>Update generation</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CCMR1_Output</name> <displayName>CCMR1_Output</displayName> <description>capture/compare mode register 1 (output mode)</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OC2M_3</name> <description>Output Compare 2 mode - bit 3</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC1M_3</name> <description>Output Compare 1 mode - bit 3</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC2CE</name> <description>Output compare 2 clear enable</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC2M</name> <description>Output compare 2 mode</description> <bitOffset>12</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC2PE</name> <description>Output compare 2 preload enable</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC2FE</name> <description>Output compare 2 fast enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2S</name> <description>Capture/Compare 2 selection</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OC1CE</name> <description>Output compare 1 clear enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC1M</name> <description>Output compare 1 mode</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC1PE</name> <description>Output compare 1 preload enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC1FE</name> <description>Output compare 1 fast enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1S</name> <description>Capture/Compare 1 selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CCMR1_Input</name> <displayName>CCMR1_Input</displayName> <description>capture/compare mode register 1 (input mode)</description> <alternateRegister>CCMR1_Output</alternateRegister> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IC2F</name> <description>Input capture 2 filter</description> <bitOffset>12</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>IC2PSC</name> <description>Input capture 2 prescaler</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CC2S</name> <description>Capture/compare 2 selection</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>IC1F</name> <description>Input capture 1 filter</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>IC1PSC</name> <description>Input capture 1 prescaler</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CC1S</name> <description>Capture/Compare 1 selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CCMR2_Output</name> <displayName>CCMR2_Output</displayName> <description>capture/compare mode register 2 (output mode)</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OC4M_3</name> <description>Output Compare 4 mode - bit 3</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC3M_3</name> <description>Output Compare 3 mode - bit 3</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC4CE</name> <description>Output compare 4 clear enable</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC4M</name> <description>Output compare 4 mode</description> <bitOffset>12</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC4PE</name> <description>Output compare 4 preload enable</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC4FE</name> <description>Output compare 4 fast enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4S</name> <description>Capture/Compare 4 selection</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OC3CE</name> <description>Output compare 3 clear enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC3M</name> <description>Output compare 3 mode</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC3PE</name> <description>Output compare 3 preload enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC3FE</name> <description>Output compare 3 fast enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3S</name> <description>Capture/Compare 3 selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CCMR2_Input</name> <displayName>CCMR2_Input</displayName> <description>capture/compare mode register 2 (input mode)</description> <alternateRegister>CCMR2_Output</alternateRegister> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IC4F</name> <description>Input capture 4 filter</description> <bitOffset>12</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>IC4PSC</name> <description>Input capture 4 prescaler</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CC4S</name> <description>Capture/Compare 4 selection</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>IC3F</name> <description>Input capture 3 filter</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>IC3PSC</name> <description>Input capture 3 prescaler</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CC3S</name> <description>Capture/Compare 3 selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CCER</name> <displayName>CCER</displayName> <description>capture/compare enable register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CC4NP</name> <description>Capture/Compare 4 output Polarity</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4P</name> <description>Capture/Compare 3 output Polarity</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4E</name> <description>Capture/Compare 4 output enable</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3NP</name> <description>Capture/Compare 3 output Polarity</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3P</name> <description>Capture/Compare 3 output Polarity</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3E</name> <description>Capture/Compare 3 output enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2NP</name> <description>Capture/Compare 2 output Polarity</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2P</name> <description>Capture/Compare 2 output Polarity</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2E</name> <description>Capture/Compare 2 output enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1NP</name> <description>Capture/Compare 1 output Polarity</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1P</name> <description>Capture/Compare 1 output Polarity</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1E</name> <description>Capture/Compare 1 output enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CNT</name> <displayName>CNT</displayName> <description>counter</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CNT_H</name> <description>High counter value (TIM2 only)</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>CNT_L</name> <description>Low counter value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>PSC</name> <displayName>PSC</displayName> <description>prescaler</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>PSC</name> <description>Prescaler value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>ARR</name> <displayName>ARR</displayName> <description>auto-reload register</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ARR_H</name> <description>High Auto-reload value (TIM2 only)</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>ARR_L</name> <description>Low Auto-reload value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CCR1</name> <displayName>CCR1</displayName> <description>capture/compare register 1</description> <addressOffset>0x34</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCR1_H</name> <description>High Capture/Compare 1 value (TIM2 only)</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>CCR1_L</name> <description>Low Capture/Compare 1 value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CCR2</name> <displayName>CCR2</displayName> <description>capture/compare register 2</description> <addressOffset>0x38</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCR2_H</name> <description>High Capture/Compare 2 value (TIM2 only)</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>CCR2_L</name> <description>Low Capture/Compare 2 value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CCR3</name> <displayName>CCR3</displayName> <description>capture/compare register 3</description> <addressOffset>0x3C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCR3_H</name> <description>High Capture/Compare value (TIM2 only)</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>CCR3_L</name> <description>Low Capture/Compare value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CCR4</name> <displayName>CCR4</displayName> <description>capture/compare register 4</description> <addressOffset>0x40</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCR4_H</name> <description>High Capture/Compare value (TIM2 only)</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>CCR4_L</name> <description>Low Capture/Compare value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>DCR</name> <displayName>DCR</displayName> <description>DMA control register</description> <addressOffset>0x48</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>DBL</name> <description>DMA burst length</description> <bitOffset>8</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>DBA</name> <description>DMA base address</description> <bitOffset>0</bitOffset> <bitWidth>5</bitWidth> </field> </fields> </register> <register> <name>DMAR</name> <displayName>DMAR</displayName> <description>DMA address for full transfer</description> <addressOffset>0x4C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>DMAB</name> <description>DMA register for burst accesses</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>OR1</name> <displayName>OR1</displayName> <description>TIM option register</description> <addressOffset>0x50</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>IOCREF_CLR</name> <description>IOCREF_CLR</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>AF1</name> <displayName>AF1</displayName> <description>TIM alternate function option register 1</description> <addressOffset>0x60</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>ETRSEL</name> <description>External trigger source selection</description> <bitOffset>14</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>TISEL</name> <displayName>TISEL</displayName> <description>TIM alternate function option register 1</description> <addressOffset>0x68</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>TI1SEL</name> <description>TI1SEL</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>TI2SEL</name> <description>TI2SEL</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral derivedFrom="TIM2"> <name>TIM3</name> <baseAddress>0x40000400</baseAddress> </peripheral> <peripheral> <name>NVIC</name> <description>Nested Vectored Interrupt Controller</description> <groupName>NVIC</groupName> <baseAddress>0xE000E100</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x33D</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>ISER</name> <displayName>ISER</displayName> <description>Interrupt Set Enable Register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SETENA</name> <description>SETENA</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>ICER</name> <displayName>ICER</displayName> <description>Interrupt Clear Enable Register</description> <addressOffset>0x80</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CLRENA</name> <description>CLRENA</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>ISPR</name> <displayName>ISPR</displayName> <description>Interrupt Set-Pending Register</description> <addressOffset>0x100</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SETPEND</name> <description>SETPEND</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>ICPR</name> <displayName>ICPR</displayName> <description>Interrupt Clear-Pending Register</description> <addressOffset>0x180</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CLRPEND</name> <description>CLRPEND</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>IPR0</name> <displayName>IPR0</displayName> <description>Interrupt Priority Register 0</description> <addressOffset>0x300</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PRI_0</name> <description>priority for interrupt 0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>PRI_1</name> <description>priority for interrupt 1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>PRI_2</name> <description>priority for interrupt 2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>PRI_3</name> <description>priority for interrupt 3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR1</name> <displayName>IPR1</displayName> <description>Interrupt Priority Register 1</description> <addressOffset>0x304</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PRI_4</name> <description>priority for interrupt n</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>PRI_5</name> <description>priority for interrupt n</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>PRI_6</name> <description>priority for interrupt n</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>PRI_7</name> <description>priority for interrupt n</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR2</name> <displayName>IPR2</displayName> <description>Interrupt Priority Register 2</description> <addressOffset>0x308</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PRI_8</name> <description>priority for interrupt n</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>PRI_9</name> <description>priority for interrupt n</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>PRI_10</name> <description>priority for interrupt n</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>PRI_11</name> <description>priority for interrupt n</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR3</name> <displayName>IPR3</displayName> <description>Interrupt Priority Register 3</description> <addressOffset>0x30C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PRI_12</name> <description>priority for interrupt n</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>PRI_13</name> <description>priority for interrupt n</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>PRI_14</name> <description>priority for interrupt n</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>PRI_15</name> <description>priority for interrupt n</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR4</name> <displayName>IPR4</displayName> <description>Interrupt Priority Register 4</description> <addressOffset>0x310</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PRI_16</name> <description>priority for interrupt n</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>PRI_17</name> <description>priority for interrupt n</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>PRI_18</name> <description>priority for interrupt n</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>PRI_19</name> <description>priority for interrupt n</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR5</name> <displayName>IPR5</displayName> <description>Interrupt Priority Register 5</description> <addressOffset>0x314</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PRI_20</name> <description>priority for interrupt n</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>PRI_21</name> <description>priority for interrupt n</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>PRI_22</name> <description>priority for interrupt n</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>PRI_23</name> <description>priority for interrupt n</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR6</name> <displayName>IPR6</displayName> <description>Interrupt Priority Register 6</description> <addressOffset>0x318</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PRI_24</name> <description>priority for interrupt n</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>PRI_25</name> <description>priority for interrupt n</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>PRI_26</name> <description>priority for interrupt n</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>PRI_27</name> <description>priority for interrupt n</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR7</name> <displayName>IPR7</displayName> <description>Interrupt Priority Register 7</description> <addressOffset>0x31C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PRI_28</name> <description>priority for interrupt n</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>PRI_29</name> <description>priority for interrupt n</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>PRI_30</name> <description>priority for interrupt n</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>PRI_31</name> <description>priority for interrupt n</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR8</name> <displayName>IPR8</displayName> <description>Interrupt Priority Register 8</description> <addressOffset>0x320</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> </register> </registers> </peripheral> <peripheral> <name>MPU</name> <description>Memory protection unit</description> <groupName>MPU</groupName> <baseAddress>0xE000ED90</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x15</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>MPU_TYPER</name> <displayName>MPU_TYPER</displayName> <description>MPU type register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0X00000800</resetValue> <fields> <field> <name>SEPARATE</name> <description>Separate flag</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DREGION</name> <description>Number of MPU data regions</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IREGION</name> <description>Number of MPU instruction regions</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>MPU_CTRL</name> <displayName>MPU_CTRL</displayName> <description>MPU control register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0X00000000</resetValue> <fields> <field> <name>ENABLE</name> <description>Enables the MPU</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HFNMIENA</name> <description>Enables the operation of MPU during hard fault</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PRIVDEFENA</name> <description>Enable priviliged software access to default memory map</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>MPU_RNR</name> <displayName>MPU_RNR</displayName> <description>MPU region number register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0X00000000</resetValue> <fields> <field> <name>REGION</name> <description>MPU region</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>MPU_RBAR</name> <displayName>MPU_RBAR</displayName> <description>MPU region base address register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0X00000000</resetValue> <fields> <field> <name>REGION</name> <description>MPU region field</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>VALID</name> <description>MPU region number valid</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADDR</name> <description>Region base address field</description> <bitOffset>5</bitOffset> <bitWidth>27</bitWidth> </field> </fields> </register> <register> <name>MPU_RASR</name> <displayName>MPU_RASR</displayName> <description>MPU region attribute and size register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0X00000000</resetValue> <fields> <field> <name>ENABLE</name> <description>Region enable bit.</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SIZE</name> <description>Size of the MPU protection region</description> <bitOffset>1</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>SRD</name> <description>Subregion disable bits</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>B</name> <description>memory attribute</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>C</name> <description>memory attribute</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>S</name> <description>Shareable memory attribute</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEX</name> <description>memory attribute</description> <bitOffset>19</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>AP</name> <description>Access permission</description> <bitOffset>24</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>XN</name> <description>Instruction access disable bit</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>STK</name> <description>SysTick timer</description> <groupName>STK</groupName> <baseAddress>0xE000E010</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x11</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>CSR</name> <displayName>CSR</displayName> <description>SysTick control and status register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0X00000000</resetValue> <fields> <field> <name>ENABLE</name> <description>Counter enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TICKINT</name> <description>SysTick exception request enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CLKSOURCE</name> <description>Clock source selection</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>COUNTFLAG</name> <description>COUNTFLAG</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>RVR</name> <displayName>RVR</displayName> <description>SysTick reload value register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0X00000000</resetValue> <fields> <field> <name>RELOAD</name> <description>RELOAD value</description> <bitOffset>0</bitOffset> <bitWidth>24</bitWidth> </field> </fields> </register> <register> <name>CVR</name> <displayName>CVR</displayName> <description>SysTick current value register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0X00000000</resetValue> <fields> <field> <name>CURRENT</name> <description>Current counter value</description> <bitOffset>0</bitOffset> <bitWidth>24</bitWidth> </field> </fields> </register> <register> <name>CALIB</name> <displayName>CALIB</displayName> <description>SysTick calibration value register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0X00000000</resetValue> <fields> <field> <name>TENMS</name> <description>Calibration value</description> <bitOffset>0</bitOffset> <bitWidth>24</bitWidth> </field> <field> <name>SKEW</name> <description>SKEW flag: Indicates whether the TENMS value is exact</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NOREF</name> <description>NOREF flag. Reads as zero</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>SCB</name> <description>System control block</description> <groupName>SCB</groupName> <baseAddress>0xE000ED00</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x41</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>CPUID</name> <displayName>CPUID</displayName> <description>CPUID base register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x410FC241</resetValue> <fields> <field> <name>Revision</name> <description>Revision number</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>PartNo</name> <description>Part number of the processor</description> <bitOffset>4</bitOffset> <bitWidth>12</bitWidth> </field> <field> <name>Architecture</name> <description>Reads as 0xF</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>Variant</name> <description>Variant number</description> <bitOffset>20</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>Implementer</name> <description>Implementer code</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>ICSR</name> <displayName>ICSR</displayName> <description>Interrupt control and state register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>VECTACTIVE</name> <description>Active vector</description> <bitOffset>0</bitOffset> <bitWidth>9</bitWidth> </field> <field> <name>RETTOBASE</name> <description>Return to base level</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>VECTPENDING</name> <description>Pending vector</description> <bitOffset>12</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>ISRPENDING</name> <description>Interrupt pending flag</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PENDSTCLR</name> <description>SysTick exception clear-pending bit</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PENDSTSET</name> <description>SysTick exception set-pending bit</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PENDSVCLR</name> <description>PendSV clear-pending bit</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PENDSVSET</name> <description>PendSV set-pending bit</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NMIPENDSET</name> <description>NMI set-pending bit.</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>VTOR</name> <displayName>VTOR</displayName> <description>Vector table offset register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TBLOFF</name> <description>Vector table base offset field</description> <bitOffset>7</bitOffset> <bitWidth>25</bitWidth> </field> </fields> </register> <register> <name>AIRCR</name> <displayName>AIRCR</displayName> <description>Application interrupt and reset control register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>VECTCLRACTIVE</name> <description>VECTCLRACTIVE</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SYSRESETREQ</name> <description>SYSRESETREQ</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ENDIANESS</name> <description>ENDIANESS</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>VECTKEYSTAT</name> <description>Register key</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>SCR</name> <displayName>SCR</displayName> <description>System control register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SLEEPONEXIT</name> <description>SLEEPONEXIT</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SLEEPDEEP</name> <description>SLEEPDEEP</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SEVEONPEND</name> <description>Send Event on Pending bit</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CCR</name> <displayName>CCR</displayName> <description>Configuration and control register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>NONBASETHRDENA</name> <description>Configures how the processor enters Thread mode</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>USERSETMPEND</name> <description>USERSETMPEND</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UNALIGN__TRP</name> <description>UNALIGN_ TRP</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DIV_0_TRP</name> <description>DIV_0_TRP</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BFHFNMIGN</name> <description>BFHFNMIGN</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STKALIGN</name> <description>STKALIGN</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SHPR2</name> <displayName>SHPR2</displayName> <description>System handler priority registers</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PRI_11</name> <description>Priority of system handler 11</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>SHPR3</name> <displayName>SHPR3</displayName> <description>System handler priority registers</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PRI_14</name> <description>Priority of system handler 14</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>PRI_15</name> <description>Priority of system handler 15</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>VREFBUF</name> <description>System configuration controller</description> <groupName>VREFBUF</groupName> <baseAddress>0x40010030</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x50</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>CSR</name> <displayName>CSR</displayName> <description>VREFBUF control and status register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <resetValue>0x00000002</resetValue> <fields> <field> <name>ENVR</name> <description>Voltage reference buffer mode enable This bit is used to enable the voltage reference buffer mode.</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>HIZ</name> <description>High impedance mode This bit controls the analog switch to connect or not the VREF+ pin. Refer to Table196: VREF buffer modes for the mode descriptions depending on ENVR bit configuration.</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>VRR</name> <description>Voltage reference buffer ready</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>VRS</name> <description>Voltage reference scale These bits select the value generated by the voltage reference buffer. Other: Reserved</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>CCR</name> <displayName>CCR</displayName> <description>VREFBUF calibration control register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TRIM</name> <description>Trimming code These bits are automatically initialized after reset with the trimming value stored in the Flash memory during the production test. Writing into these bits allows to tune the internal reference buffer voltage.</description> <bitOffset>0</bitOffset> <bitWidth>6</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>DBG</name> <description>MCU debug component</description> <groupName>DBG</groupName> <baseAddress>0x40015800</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>IDCODE</name> <displayName>IDCODE</displayName> <description>DBGMCU_IDCODE</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DEV_ID</name> <description>Device identifier</description> <bitOffset>0</bitOffset> <bitWidth>12</bitWidth> </field> <field> <name>REV_ID</name> <description>Revision identifie</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CR</name> <displayName>CR</displayName> <description>Debug MCU configuration register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DBG_STOP</name> <description>Debug Stop mode</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_STANDBY</name> <description>Debug Standby mode</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>APB_FZ1</name> <displayName>APB_FZ1</displayName> <description>Debug MCU APB1 freeze register1</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DBG_TIM2_STOP</name> <description>TIM2 counter stopped when core is halted</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_TIM3_STOP</name> <description>TIM3 counter stopped when core is halted</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_RTC_STOP</name> <description>RTC counter stopped when core is halted</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_WWDG_STOP</name> <description>Window watchdog counter stopped when core is halted</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_IWDG_STOP</name> <description>Independent watchdog counter stopped when core is halted</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_I2C1_STOP</name> <description>I2C1 SMBUS timeout counter stopped when core is halted</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>APB_FZ2</name> <displayName>APB_FZ2</displayName> <description>Debug MCU APB1 freeze register 2</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DBG_TIM1_STOP</name> <description>TIM1 counter stopped when core is halted</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_TIM14_STOP</name> <description>DBG_TIM14_STOP</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_TIM16_STOP</name> <description>DBG_TIM16_STOP</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_TIM17_STOP</name> <description>DBG_TIM17_STOP</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>NVIC_STIR</name> <description>Nested vectored interrupt controller</description> <groupName>NVIC</groupName> <baseAddress>0xE000EF00</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x5</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>STIR</name> <displayName>STIR</displayName> <description>Software trigger interrupt register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>INTID</name> <description>Software generated interrupt ID</description> <bitOffset>0</bitOffset> <bitWidth>9</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>SCB_ACTRL</name> <description>System control block ACTLR</description> <groupName>SCB</groupName> <baseAddress>0xE000E008</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x5</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>ACTRL</name> <displayName>ACTRL</displayName> <description>Auxiliary control register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DISMCYCINT</name> <description>DISMCYCINT</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DISDEFWBUF</name> <description>DISDEFWBUF</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DISFOLD</name> <description>DISFOLD</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DISFPCA</name> <description>DISFPCA</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DISOOFP</name> <description>DISOOFP</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>FPU_CPACR</name> <description>Floating point unit CPACR</description> <groupName>FPU</groupName> <baseAddress>0xE000ED88</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x5</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>CPACR</name> <displayName>CPACR</displayName> <description>Coprocessor access control register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000000</resetValue> <fields> <field> <name>CP</name> <description>CP</description> <bitOffset>20</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>FPU</name> <description>Floting point unit</description> <groupName>FPU</groupName> <baseAddress>0xE000EF34</baseAddress> <addressBlock> <offset>0x0</offset> <size>0xD</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>FPCCR</name> <displayName>FPCCR</displayName> <description>Floating-point context control register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>LSPACT</name> <description>LSPACT</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>USER</name> <description>USER</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>THREAD</name> <description>THREAD</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HFRDY</name> <description>HFRDY</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MMRDY</name> <description>MMRDY</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BFRDY</name> <description>BFRDY</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MONRDY</name> <description>MONRDY</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LSPEN</name> <description>LSPEN</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ASPEN</name> <description>ASPEN</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>FPCAR</name> <displayName>FPCAR</displayName> <description>Floating-point context address register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ADDRESS</name> <description>Location of unpopulated floating-point</description> <bitOffset>3</bitOffset> <bitWidth>29</bitWidth> </field> </fields> </register> <register> <name>FPSCR</name> <displayName>FPSCR</displayName> <description>Floating-point status control register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IOC</name> <description>Invalid operation cumulative exception bit</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DZC</name> <description>Division by zero cumulative exception bit.</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OFC</name> <description>Overflow cumulative exception bit</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UFC</name> <description>Underflow cumulative exception bit</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IXC</name> <description>Inexact cumulative exception bit</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDC</name> <description>Input denormal cumulative exception bit.</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RMode</name> <description>Rounding Mode control field</description> <bitOffset>22</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>FZ</name> <description>Flush-to-zero mode control bit:</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DN</name> <description>Default NaN mode control bit</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AHP</name> <description>Alternative half-precision control bit</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>V</name> <description>Overflow condition code flag</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>C</name> <description>Carry condition code flag</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>Z</name> <description>Zero condition code flag</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>N</name> <description>Negative condition code flag</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>SYSCFG_ITLINE</name> <description>System configuration controller</description> <groupName>SYSCFG</groupName> <baseAddress>0x40010080</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x180</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>ITLINE0</name> <displayName>ITLINE0</displayName> <description>interrupt line 0 status register</description> <addressOffset>0x80</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>WWDG</name> <description>Window watchdog interrupt pending flag</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ITLINE1</name> <displayName>ITLINE1</displayName> <description>interrupt line 1 status register</description> <addressOffset>0x84</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PVDOUT</name> <description>PVD supply monitoring interrupt request pending (EXTI line 16).</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ITLINE2</name> <displayName>ITLINE2</displayName> <description>interrupt line 2 status register</description> <addressOffset>0x88</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TAMP</name> <description>TAMP</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RTC</name> <description>RTC</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ITLINE3</name> <displayName>ITLINE3</displayName> <description>interrupt line 3 status register</description> <addressOffset>0x8C</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FLASH_ITF</name> <description>FLASH_ITF</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FLASH_ECC</name> <description>FLASH_ECC</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ITLINE4</name> <displayName>ITLINE4</displayName> <description>interrupt line 4 status register</description> <addressOffset>0x90</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>RCC</name> <description>RCC</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ITLINE5</name> <displayName>ITLINE5</displayName> <description>interrupt line 5 status register</description> <addressOffset>0x94</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>EXTI0</name> <description>EXTI0</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EXTI1</name> <description>EXTI1</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ITLINE6</name> <displayName>ITLINE6</displayName> <description>interrupt line 6 status register</description> <addressOffset>0x98</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>EXTI2</name> <description>EXTI2</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EXTI3</name> <description>EXTI3</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ITLINE7</name> <displayName>ITLINE7</displayName> <description>interrupt line 7 status register</description> <addressOffset>0x9C</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>EXTI4</name> <description>EXTI4</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EXTI5</name> <description>EXTI5</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EXTI6</name> <description>EXTI6</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EXTI7</name> <description>EXTI7</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EXTI8</name> <description>EXTI8</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EXTI9</name> <description>EXTI9</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EXTI10</name> <description>EXTI10</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EXTI11</name> <description>EXTI11</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EXTI12</name> <description>EXTI12</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EXTI13</name> <description>EXTI13</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EXTI14</name> <description>EXTI14</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EXTI15</name> <description>EXTI15</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ITLINE9</name> <displayName>ITLINE9</displayName> <description>interrupt line 9 status register</description> <addressOffset>0xA4</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DMA1_CH1</name> <description>DMA1_CH1</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ITLINE10</name> <displayName>ITLINE10</displayName> <description>interrupt line 10 status register</description> <addressOffset>0xA8</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DMA1_CH2</name> <description>DMA1_CH1</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMA1_CH3</name> <description>DMA1_CH3</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ITLINE11</name> <displayName>ITLINE11</displayName> <description>interrupt line 11 status register</description> <addressOffset>0xAC</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DMAMUX</name> <description>DMAMUX</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMA1_CH4</name> <description>DMA1_CH4</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMA1_CH5</name> <description>DMA1_CH5</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ITLINE12</name> <displayName>ITLINE12</displayName> <description>interrupt line 12 status register</description> <addressOffset>0xB0</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ADC</name> <description>ADC</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ITLINE13</name> <displayName>ITLINE13</displayName> <description>interrupt line 13 status register</description> <addressOffset>0xB4</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TIM1_CCU</name> <description>TIM1_CCU</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM1_TRG</name> <description>TIM1_TRG</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM1_UPD</name> <description>TIM1_UPD</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM1_BRK</name> <description>TIM1_BRK</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ITLINE14</name> <displayName>ITLINE14</displayName> <description>interrupt line 14 status register</description> <addressOffset>0xB8</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TIM1_CC</name> <description>TIM1_CC</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ITLINE15</name> <displayName>ITLINE15</displayName> <description>interrupt line 15 status register</description> <addressOffset>0xBC</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TIM2</name> <description>TIM2</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ITLINE16</name> <displayName>ITLINE16</displayName> <description>interrupt line 16 status register</description> <addressOffset>0xC0</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TIM3</name> <description>TIM3</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ITLINE19</name> <displayName>ITLINE19</displayName> <description>interrupt line 19 status register</description> <addressOffset>0xCC</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TIM14</name> <description>TIM14</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ITLINE21</name> <displayName>ITLINE21</displayName> <description>interrupt line 21 status register</description> <addressOffset>0xD4</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TIM16</name> <description>TIM16</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ITLINE22</name> <displayName>ITLINE22</displayName> <description>interrupt line 22 status register</description> <addressOffset>0xD8</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TIM17</name> <description>TIM17</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ITLINE23</name> <displayName>ITLINE23</displayName> <description>interrupt line 23 status register</description> <addressOffset>0xDC</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>I2C1</name> <description>I2C1</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ITLINE24</name> <displayName>ITLINE24</displayName> <description>interrupt line 24 status register</description> <addressOffset>0xE0</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>I2C2</name> <description>I2C2</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ITLINE25</name> <displayName>ITLINE25</displayName> <description>interrupt line 25 status register</description> <addressOffset>0xE4</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SPI1</name> <description>SPI1</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ITLINE26</name> <displayName>ITLINE26</displayName> <description>interrupt line 26 status register</description> <addressOffset>0xE8</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SPI2</name> <description>SPI2</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ITLINE27</name> <displayName>ITLINE27</displayName> <description>interrupt line 27 status register</description> <addressOffset>0xEC</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>USART1</name> <description>USART1</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ITLINE28</name> <displayName>ITLINE28</displayName> <description>interrupt line 28 status register</description> <addressOffset>0xF0</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>USART2</name> <description>USART2</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ITLINE29</name> <displayName>ITLINE29</displayName> <description>interrupt line 29 status register</description> <addressOffset>0xF4</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>USART5</name> <description>USART5</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> </peripherals> </device>