Added module for RTC DS3231.

Inc/ds3231.h

@@ -3,39 +3,51 @@
 #define DS3231_H
 
 /* i2c slave address of the DS3231 chip */
-#define DS3231_I2C_WRADDR  0xD0
-#define DS3231_I2C_RDADDR  0xD1
+#define DS3231_I2C_ADDR             0xD0
 
 /* timekeeping registers */
-#define DS3231_TIME_CAL_ADDR        0x00
-#define DS3231_CALENDAR_ADDR        0x03
-#define DS3231_ALARM1_ADDR          0x07
-#define DS3231_ALARM2_ADDR          0x0B
-#define DS3231_CONTROL_ADDR         0x0E
-#define DS3231_STATUS_ADDR          0x0F
-#define DS3231_AGING_OFFSET_ADDR    0x10
-#define DS3231_TEMPERATURE_ADDR     0x11
+#define DS3231_ADDR_TIME            0x00
+#define DS3231_ADDR_CALENDAR        0x03
+#define DS3231_ADDR_ALARM1          0x07
+#define DS3231_ADDR_ALARM2          0x0B
+#define DS3231_ADDR_CONTROL         0x0E
+#define DS3231_ADDR_STATUS          0x0F
+#define DS3231_ADDR_AGING_OFFSET    0x10
+#define DS3231_ADDR_TEMPERATURE     0x11
 
-// control register bits
-#define DS3231_A1IE     0x01
-#define DS3231_A2IE     0x02
-#define DS3231_INTCN    0x04
-#define DS3231_RS1	    0x08
-#define DS3231_RS2	    0x10
-#define DS3231_CONV	    0x20
-#define DS3231_BBSQW	  0x40
-#define DS3231_OSC_OSC	0x80
+/* control register bits */
+#define DS3231_A1IE                 0x01
+#define DS3231_A2IE                 0x02
+#define DS3231_INTCN                0x04
+#define DS3231_RS1	                0x08
+#define DS3231_RS2	                0x10
+#define DS3231_CONV	                0x20
+#define DS3231_BBSQW	              0x40
+#define DS3231_OSC_OSC	            0x80
+
+/* control/status register bits */
+#define DS3231_A1F                  0x01
+#define DS3231_A2F                  0x02
+#define DS3231_BSY                  0x04
+#define DS3231_EN32kHz              0x08
+#define DS3231_OSF                  0x80
 
 /* square-wave output frequency */
-#define DS3231_1HZ	    0x00
-#define DS3231_1024HZ	  DS3231_RS1
-#define DS3231_4096HZ	  DS3231_RS2
-#define DS3231_8192HZ	  (DS3231_RS1 | DS3231_RS2)
+#define DS3231_1HZ	                0x00
+#define DS3231_1024HZ	              DS3231_RS1
+#define DS3231_4096HZ	              DS3231_RS2
+#define DS3231_8192HZ	              (DS3231_RS1 | DS3231_RS2)
 
-/* status register bits */
-#define DS3231_A1F      0x01
-#define DS3231_A2F      0x02
-#define DS3231_OSF      0x80
+/* number of bytes */
+#define DS3231_SIZE_TIME            3
+#define DS3231_SIZE_CALENDAR        4
+#define DS3231_SIZE_ALARM1          4
+#define DS3231_SIZE_ALARM2          3
+#define DS3231_SIZE_CONTROL         1
+#define DS3231_SIZE_STATUS          1
+#define DS3231_SIZE_AGOFFS          1
+#define DS3231_SIZE_TEMPERATURE     2
+#define DS3231_SIZE_ALL             19
 
 /* RTC Status */
 typedef enum {
@@ -50,47 +62,91 @@ typedef enum {
  */
 typedef struct {
   /**
-   * @brief  Seconds
+   * @brief  00h: Seconds
    */
   uint8_t Sec;
   /**
-   * @brief  Minutes
+   * @brief  01h: Minutes
    */
   uint8_t Min;
   /**
-   * @brief  Hours
+   * @brief  02h: Hours
    */
   uint8_t Hr;
   /**
-   * @brief  Week Day
+   * @brief  03h: Week Day
    */
   uint8_t WD;
   /**
-   * @brief  Day of Month
+   * @brief  04h: Day of Month
    */
   uint8_t Day;
   /**
-   * @brief  Month
+   * @brief  05h: Month
    */
   uint8_t Mon;
   /**
-   * @brief  Year
+   * @brief  06h: Year
    */
   uint8_t Year;
+  /**
+   * @brief  07h: Alarm 1 Seconds
+   */
+  uint8_t A1SS;
+  /**
+   * @brief  08h: Alarm 1 Minutes
+   */
+  uint8_t A1MM;
+  /**
+   * @brief  09h: Alarm 1 Hours
+   */
+  uint8_t A1HH;
+  /**
+   * @brief  0Ah: Alarm 1 Day / Date
+   */
+  uint8_t A1DD;
+  /**
+   * @brief  0Bh: Alarm 2 Minutes
+   */
+  uint8_t A2MM;
+  /**
+   * @brief  0Ch: Alarm 2 Hours
+   */
+  uint8_t A2HH;
+  /**
+   * @brief  0Dh: Alarm 2 Day  / Date
+   */
+  uint8_t A2DD;
+  /**
+   * @brief  0Eh: Control
+   */
+  uint8_t Ctrl;
+  /**
+   * @brief  0Fh: Control/Status
+   */
+  uint8_t CtSt;
+  /**
+   * @brief  10h: Aging Offset
+   */
+  uint8_t AgOffset;
+  /**
+   * @brief  11h: MSB of Temp
+   */
+  uint8_t TempH;
+  /**
+   * @brief  12h: LSB of Temp
+   */
+  uint8_t TempL;
 } rtc_t;
-/*
-void RTC_Init(void);
 
+void RTC_Init(void);
 void RTC_ReadAll(rtc_t * data);
-void RTC_ReadTime(rtc_t * data);
-void RTC_ReadCalendar(rtc_t * data);
-
-void RTC_WriteAll(rtc_t * data);
+void RTC_WriteTimeCalendar(rtc_t * data);
 void RTC_WriteTime(rtc_t * data);
 void RTC_WriteHHMM(rtc_t * data);
 void RTC_WriteCalendar(rtc_t * data);
 
 uint8_t bcd2bin(uint8_t bcd);
 uint8_t bin2bcd(uint8_t bin);
-*/
+
 #endif // DS3231_H

MNC-IN12x5.cbp

@@ -100,6 +100,9 @@
 		<Unit filename="Inc/stm32g0xx_it.h" />
 		<Unit filename="Makefile" />
 		<Unit filename="ReadMe.txt" />
+		<Unit filename="Src/ds3231.c">
+			<Option compilerVar="CC" />
+		</Unit>
 		<Unit filename="Src/main.c">
 			<Option compilerVar="CC" />
 		</Unit>

Makefile

@@ -41,6 +41,7 @@ BUILD_DIR = build
 C_SOURCES =  \
 Src/main.c \
 Src/stm32g0xx_it.c \
+Src/ds3231.c \
 Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_utils.c \
 Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_exti.c \
 Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_gpio.c \

Src/ds3231.c

@@ -0,0 +1,214 @@
+#include "main.h"
+
+#define RTC_TX_BUF_SIZE 4
+
+static uint8_t i2cBufTX[RTC_TX_BUF_SIZE] = {0};
+
+/**
+ * @brief Инициализация RTC
+ */
+void RTC_Init(void) {
+  /* Clear flags */
+  Flag.I2C_TX_End = 0;
+
+  /* Source: Address of the I2C TX buffer. */
+  DMA1_Channel3->CMAR = (uint32_t)&i2cBufTX;
+  /* Destination: I2C TX data register. */
+  DMA1_Channel3->CPAR = (uint32_t)&(I2C1->TXDR);
+  /* Set DMA data transfer length (I2C TX buffer length). */
+  DMA1_Channel3->CNDTR = RTC_TX_BUF_SIZE;
+  /* Enable DMA channels for I2C */
+  DMA1_Channel3->CCR |= DMA_CCR_EN;
+
+  /* Fill buffer with register address and register value */
+  i2cBufTX[0] = DS3231_ADDR_CONTROL;
+  i2cBufTX[1] = DS3231_1HZ; // set 1 Hz output squware
+  i2cBufTX[2] = 0x0; // disable 32 kHz output
+
+  /* Wait for I2C */
+  while ( I2C1->ISR & I2C_ISR_BUSY ) {};
+/*
+  LL_I2C_SetSlaveAddr(I2C1, DS3231_I2C_ADDR);
+  LL_I2C_SetTransferRequest(I2C1, LL_I2C_REQUEST_WRITE);
+  LL_I2C_SetTransferSize(I2C1, 3); // controll addr + 2 bytes of data
+*/
+  /* Set the device address and number bytes to send. */
+  I2C1->CR2 &= ~( I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RD_WRN);
+  I2C1->CR2 |= ( DS3231_I2C_ADDR | 3 << I2C_CR2_NBYTES_Pos );
+  /* Enable I2C DMA requests. */
+  I2C1->CR1 |= ( I2C_CR1_TXDMAEN );
+  /* Send a start signal. */
+  I2C1->CR2 |= ( I2C_CR2_START );
+  /* (DMA is now running.) */
+}
+
+/**
+ * @brief Чтение всех регистров DS3231
+ */
+void RTC_ReadAll(rtc_t * data) {
+  Flag.I2C_RX_End = 0;
+  Flag.I2C_TX_End = 0;
+
+  /* Source: Address of the I2C RX buffer. */
+  DMA1_Channel2->CMAR = (uint32_t)data;
+  /* Destination: I2C RX data register. */
+  DMA1_Channel2->CPAR = (uint32_t)&(I2C1->RXDR);
+  /* Set DMA data transfer length (I2C RX buffer length). */
+  DMA1_Channel2->CNDTR = DS3231_SIZE_ALL;
+  /* Enable DMA channels for I2C RX */
+  DMA1_Channel2->CCR |= DMA_CCR_EN;
+
+  /* wait for i2c */
+  while ( I2C1->ISR & I2C_ISR_BUSY ) {};
+
+  /* send first register address 00h */
+  I2C1->CR2 &= ~( I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RD_WRN);
+  I2C1->CR2 |= ( DS3231_I2C_ADDR | 1 << I2C_CR2_NBYTES_Pos );
+
+  I2C1->CR2 |= ( I2C_CR2_START );
+
+  while ( !( I2C1->CR2 & I2C_CR2_START ) ) {};
+  I2C1->TXDR = DS3231_ADDR_TIME;
+
+  while ( I2C1->ISR & I2C_ISR_BUSY ) {};
+  /* Reading all */
+/*
+  LL_I2C_SetSlaveAddr(I2C1, DS3231_I2C_ADDR);
+  LL_I2C_SetTransferRequest(I2C1, LL_I2C_REQUEST_READ);
+  LL_I2C_SetTransferSize(I2C1, DS3231_SIZE_ALL);
+*/
+  I2C1->CR2 &= ~( I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RD_WRN);
+  I2C1->CR2 |= ( DS3231_I2C_ADDR | DS3231_SIZE_ALL << I2C_CR2_NBYTES_Pos | I2C_CR2_RD_WRN);
+
+  I2C1->CR1 |= ( I2C_CR1_RXDMAEN );
+  I2C1->CR2 |= ( I2C_CR2_START );
+
+}
+
+/**
+ * @brief Запись времени и календаря
+ */
+void RTC_WriteTimeCalendar(rtc_t * data) {
+  Flag.I2C_TX_End = 0;
+
+  DMA1_Channel3->CMAR = (uint32_t)data;
+  DMA1_Channel3->CPAR = (uint32_t)&(I2C1->TXDR);
+  DMA1_Channel3->CNDTR = DS3231_SIZE_TIME + DS3231_SIZE_CALENDAR;
+
+  while ( I2C1->ISR & I2C_ISR_BUSY ) {};
+
+  I2C1->CR2 &= ~( I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RD_WRN);
+  I2C1->CR2 |= ( DS3231_I2C_ADDR | (DS3231_SIZE_TIME + DS3231_SIZE_CALENDAR + 1) << I2C_CR2_NBYTES_Pos );
+  I2C1->CR1 |= ( I2C_CR1_TXDMAEN );
+  I2C1->CR2 |= ( I2C_CR2_START );
+
+  while ( !( I2C1->CR2 & I2C_CR2_START ) ) {};
+  I2C1->TXDR = DS3231_ADDR_TIME; // send reg addr when START finish
+
+  DMA1_Channel3->CCR |= DMA_CCR_EN; // and launch DMA for data to transfer
+}
+
+/**
+ * @brief Запись времени
+ */
+void RTC_WriteTime(rtc_t * data) {
+  Flag.I2C_TX_End = 0;
+
+  DMA1_Channel3->CMAR = (uint32_t)data;
+  DMA1_Channel3->CPAR = (uint32_t)&(I2C1->TXDR);
+  DMA1_Channel3->CNDTR = DS3231_SIZE_TIME;
+
+  while ( I2C1->ISR & I2C_ISR_BUSY ) {};
+
+  I2C1->CR2 &= ~( I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RD_WRN);
+  I2C1->CR2 |= ( DS3231_I2C_ADDR | (DS3231_SIZE_TIME + 1) << I2C_CR2_NBYTES_Pos );
+  I2C1->CR1 |= ( I2C_CR1_TXDMAEN );
+  I2C1->CR2 |= ( I2C_CR2_START );
+
+  while ( !( I2C1->CR2 & I2C_CR2_START ) ) {};
+  I2C1->TXDR = DS3231_ADDR_TIME;
+
+  DMA1_Channel3->CCR |= DMA_CCR_EN;
+}
+
+/**
+ * @brief Запись часов
+ */
+void RTC_WriteHH(rtc_t * data) {
+  Flag.I2C_TX_End = 0; // некому установить этот флаг в 1
+
+  while ( I2C1->ISR & I2C_ISR_BUSY ) {};
+
+  I2C1->CR2 &= ~( I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RD_WRN);
+  I2C1->CR2 |= ( DS3231_I2C_ADDR | 2 << I2C_CR2_NBYTES_Pos );
+  I2C1->CR2 |= ( I2C_CR2_START );
+
+  while ( !( I2C1->CR2 & I2C_CR2_START ) ) {};
+  I2C1->TXDR = (DS3231_ADDR_TIME + 2);
+
+  while ((I2C1->ISR & I2C_ISR_TXE) == 0) { __NOP(); };
+  I2C1->TXDR = data->Hr;
+}
+
+/**
+ * @brief Запись часов и минут
+ */
+void RTC_WriteHHMM(rtc_t * data) {
+  Flag.I2C_TX_End = 0;
+
+  DMA1_Channel3->CMAR = (uint32_t)&i2cBufTX;
+  DMA1_Channel3->CPAR = (uint32_t)&(I2C1->TXDR);
+  DMA1_Channel3->CNDTR = 3; // addr + mm + hh
+  DMA1_Channel3->CCR |= DMA_CCR_EN;
+
+  /* Fill buffer with register address and register value */
+  i2cBufTX[0] = DS3231_ADDR_TIME + 1; // skip seconds
+  i2cBufTX[1] = data->Min;
+  i2cBufTX[2] = data->Hr;
+
+  while ( I2C1->ISR & I2C_ISR_BUSY ) {};
+
+  I2C1->CR2 &= ~( I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RD_WRN);
+  I2C1->CR2 |= ( DS3231_I2C_ADDR | 3 << I2C_CR2_NBYTES_Pos );
+  I2C1->CR1 |= ( I2C_CR1_TXDMAEN );
+  I2C1->CR2 |= ( I2C_CR2_START );
+}
+
+/**
+ * @brief Запись календаря
+ */
+void RTC_WriteCalendar(rtc_t * data) {
+  Flag.I2C_TX_End = 0;
+
+  DMA1_Channel3->CMAR = (uint32_t)&(data->WD);
+  DMA1_Channel3->CPAR = (uint32_t)&(I2C1->TXDR);
+  DMA1_Channel3->CNDTR = DS3231_SIZE_CALENDAR;
+
+  while ( I2C1->ISR & I2C_ISR_BUSY ) {};
+
+  I2C1->CR2 &= ~( I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RD_WRN);
+  I2C1->CR2 |= ( DS3231_I2C_ADDR | (DS3231_SIZE_CALENDAR + 1) << I2C_CR2_NBYTES_Pos );
+  I2C1->CR1 |= ( I2C_CR1_TXDMAEN );
+  I2C1->CR2 |= ( I2C_CR2_START );
+
+  while ( !( I2C1->CR2 & I2C_CR2_START ) ) {};
+  I2C1->TXDR = DS3231_ADDR_CALENDAR;
+
+  DMA1_Channel3->CCR |= DMA_CCR_EN;
+}
+
+/**
+ * @brief Convert BCD value to Binary
+ */
+uint8_t bcd2bin(uint8_t bcd)
+{
+  return (10 * (bcd >> 4) + (bcd & 0x0f));
+}
+
+/**
+ * @brief Convert Binary value to BCD
+ */
+uint8_t bin2bcd(uint8_t bin)
+{
+  return (((bin / 10 ) << 4) | (bin % 10));
+}

Src/main.c

@@ -39,8 +39,6 @@ typedef enum {
 /* USER CODE BEGIN PD */
 #define SPI_BUFFER_SIZE  5
 
-#define RTC_RX_BUF_SIZE  0x12
-#define RTC_TX_BUF_SIZE  7
 /* USER CODE END PD */
 
 /* Private macro -------------------------------------------------------------*/
@@ -73,8 +71,7 @@ static const uint16_t nixieCathodeMap[4][10] = {
 };
 static const uint8_t nixieCathodeMask[4][2] = {{0x00, 0x3f}, {0xc0, 0x0f}, {0xf0, 0x03}, {0xc0, 0x00}};
 static uint8_t tubesBuffer[SPI_BUFFER_SIZE] = {0};
-static uint8_t i2cBufTX[RTC_TX_BUF_SIZE] = {0};
-static uint8_t i2cBufRX[RTC_RX_BUF_SIZE] = {0};
+static rtc_t Clock;
 
 /* USER CODE END PV */
 
@@ -91,8 +88,6 @@ static void MX_TIM17_Init(void);
 /* USER CODE BEGIN PFP */
 static void showDigit(tube_pos_t pos, uint8_t dig);
 static void SPI_StartTX(void);
-static void RTC_Init(void);
-static void RTC_ReadAll(void);
 /* USER CODE END PFP */
 
 /* Private user code ---------------------------------------------------------*/
@@ -172,34 +167,19 @@ int main(void)
   /* Set DMA data transfer length (SPI buffer length). */
   DMA1_Channel1->CNDTR = SPI_BUFFER_SIZE;
 
-  /* Source: Address of the I2C RX buffer. */
-  DMA1_Channel2->CMAR = (uint32_t)&i2cBufRX;
-  /* Destination: I2C RX data register. */
-  DMA1_Channel2->CPAR = (uint32_t)&(I2C1->RXDR);
-  /* Set DMA data transfer length (I2C RX buffer length). */
-  DMA1_Channel2->CNDTR = RTC_RX_BUF_SIZE;
-
-  /* Source: Address of the I2C TX buffer. */
-  DMA1_Channel3->CMAR = (uint32_t)&i2cBufTX;
-  /* Destination: I2C TX data register. */
-  DMA1_Channel3->CPAR = (uint32_t)&(I2C1->TXDR);
-  /* Set DMA data transfer length (I2C TX buffer length). */
-  DMA1_Channel3->CNDTR = RTC_TX_BUF_SIZE;
-
   /* Enable SPI+DMA transfer */
   SPI1->CR2 |= SPI_CR2_TXDMAEN;
   SPI1->CR1 |= SPI_CR1_SPE;
 
-  /* Enable DMA channels for I2C */
-  DMA1_Channel2->CCR |= DMA_CCR_EN; // LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_2);
-  DMA1_Channel3->CCR |= DMA_CCR_EN; // LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_3);
-
   /* USER CODE END 2 */
 
   /* USER CODE BEGIN WHILE */
-  RTC_Init();
+  SPI_StartTX();
 
   IN15_OFF;
+  IN15_P;
+  RTC_ReadAll(&Clock);
+  while (Flag.I2C_RX_End == 0) {};
 
   /* Infinite loop */
   while (1)
@@ -214,7 +194,7 @@ int main(void)
     showDigit(Tube_E, 4);
     SPI_StartTX();
 */
-    RTC_ReadAll();
+    RTC_ReadAll(&Clock);
 
     if (Flag.RTC_IRQ != 0) {
       Flag.RTC_IRQ = 0;
@@ -231,10 +211,10 @@ int main(void)
     showDigit(Tube_D, 7);
     showDigit(Tube_E, 8);
 */
-    showDigit(Tube_A, i2cBufRX[1] >> 4);
-    showDigit(Tube_B, i2cBufRX[1] & 0xf);
-    showDigit(Tube_D, i2cBufRX[0] >> 4);
-    showDigit(Tube_E, i2cBufRX[0] & 0xf);
+    showDigit(Tube_A, Clock.Min >> 4);
+    showDigit(Tube_B, Clock.Min & 0xf);
+    showDigit(Tube_D, Clock.Sec >> 4);
+    showDigit(Tube_E, Clock.Sec & 0xf);
     SPI_StartTX();
 
     //__WFI();
@@ -247,64 +227,6 @@ static void SPI_StartTX(void) {
   LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_1);
 }
 
-static void RTC_Init(void) {
-  /* Clear flags */
-  Flag.I2C_RX_End = 0;
-  Flag.I2C_TX_End = 0;
-  return;
-  /* Wait for I2C */
-  while ( I2C1->ISR & I2C_ISR_BUSY ) {};
-
-  /* Fill buffer with register address and register value */
-  i2cBufTX[0] = DS3231_CONTROL_ADDR;
-  i2cBufTX[1] = 0x0; // set 1 Hz output squware
-  i2cBufTX[2] = 0x0; // disable 32 kHz output
-
-  LL_I2C_SetSlaveAddr(I2C1, I2C_ADDR_RTC);
-//  LL_I2C_SetTransferRequest(I2C1, LL_I2C_REQUEST_WRITE);
-  LL_I2C_SetTransferSize(I2C1, 3); // controll addr + 2 bytes of data
-//  LL_I2C_EnableDMAReq_TX(I2C1);
-//  LL_I2C_GenerateStartCondition(I2C1);
-
-  /* Set AUTOEND mode, the device address and number bytes to send. */
-//  I2C1->CR2 &= ~( I2C_CR2_SADD | I2C_CR2_NBYTES);
-//  I2C1->CR2 = ( I2C_ADDR_RTC << I2C_CR2_SADD_Pos | 3 << I2C_CR2_NBYTES_Pos );
-  /* Enable I2C DMA requests. */
-  I2C1->CR1 |= ( I2C_CR1_TXDMAEN );
-  /* Send a start signal. */
-  I2C1->CR2 |= ( I2C_CR2_START );
-  /* (DMA is now running.) */
-}
-
-static void RTC_ReadAll(void) {
-
-  while ( I2C1->ISR & I2C_ISR_BUSY ) {};
-/*
-  DMA1_Channel3->CMAR = (uint32_t)&i2cBufTX;
-  DMA1_Channel3->CPAR = (uint32_t)&(I2C1->TXDR);
-  DMA1_Channel3->CNDTR = RTC_TX_BUF_SIZE;
-*/
-  LL_I2C_SetSlaveAddr(I2C1, I2C_ADDR_RTC);
-  LL_I2C_SetTransferRequest(I2C1, LL_I2C_REQUEST_WRITE);
-  LL_I2C_SetTransferSize(I2C1, 1);
-//  i2cBufTX[0] = DS3231_TIME_CAL_ADDR;
-//  LL_I2C_EnableDMAReq_TX(I2C1);
-  LL_I2C_GenerateStartCondition(I2C1);
-  while ( !( I2C1->CR2 & I2C_CR2_START ) ) {};
-  I2C1->TXDR = 0x0;
-
-  while ( I2C1->ISR & I2C_ISR_BUSY ) {};
-
-  Flag.I2C_RX_End = 0;
-  Flag.I2C_TX_End = 0;
-  /* Reading all from address 00h */
-  LL_I2C_SetSlaveAddr(I2C1, I2C_ADDR_RTC);
-  LL_I2C_SetTransferRequest(I2C1, LL_I2C_REQUEST_READ);
-  LL_I2C_SetTransferSize(I2C1, 0x12); // Clock + Calendar = 7 bytes
-  LL_I2C_EnableDMAReq_RX(I2C1);
-  LL_I2C_GenerateStartCondition(I2C1);
-}
-
 /**
   * @brief System Clock Configuration
   * @retval None
@@ -393,7 +315,7 @@ static void MX_I2C1_Init(void)
 
   LL_DMA_SetChannelPriorityLevel(DMA1, LL_DMA_CHANNEL_2, LL_DMA_PRIORITY_MEDIUM);
 
-  LL_DMA_SetMode(DMA1, LL_DMA_CHANNEL_2, LL_DMA_MODE_CIRCULAR);
+//  LL_DMA_SetMode(DMA1, LL_DMA_CHANNEL_2, LL_DMA_MODE_CIRCULAR);
 
   LL_DMA_SetPeriphIncMode(DMA1, LL_DMA_CHANNEL_2, LL_DMA_PERIPH_NOINCREMENT);
 
@@ -410,7 +332,7 @@ static void MX_I2C1_Init(void)
 
   LL_DMA_SetChannelPriorityLevel(DMA1, LL_DMA_CHANNEL_3, LL_DMA_PRIORITY_MEDIUM);
 
-  LL_DMA_SetMode(DMA1, LL_DMA_CHANNEL_3, LL_DMA_MODE_CIRCULAR);
+//  LL_DMA_SetMode(DMA1, LL_DMA_CHANNEL_3, LL_DMA_MODE_CIRCULAR);
 
   LL_DMA_SetPeriphIncMode(DMA1, LL_DMA_CHANNEL_3, LL_DMA_PERIPH_NOINCREMENT);
 

Src/stm32g0xx_it.c

@@ -255,11 +255,6 @@ void TIM16_IRQHandler(void)
 void TIM17_IRQHandler(void)
 {
   /* USER CODE BEGIN TIM17_IRQn 0 */
-  /* check for NACK ??? */
-  if ( (I2C1->ISR & I2C_ISR_NACKF) != 0 ) {
-    I2C1->ICR |= I2C_ICR_NACKCF;
-    IN15_Percent;
-  }
   /* USER CODE END TIM17_IRQn 0 */
   /* USER CODE BEGIN TIM17_IRQn 1 */
 
@@ -272,7 +267,11 @@ void TIM17_IRQHandler(void)
 void I2C1_IRQHandler(void)
 {
   /* USER CODE BEGIN I2C1_IRQn 0 */
-
+  /* check for NACK ??? */
+  if ( (I2C1->ISR & I2C_ISR_NACKF) != 0 ) {
+    I2C1->ICR |= I2C_ICR_NACKCF;
+    IN15_Percent;
+  }
   /* USER CODE END I2C1_IRQn 0 */
 
   /* USER CODE BEGIN I2C1_IRQn 1 */