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|
-
- #ifndef __STM32F030x6_H
- #define __STM32F030x6_H
- #ifdef __cplusplus
- extern "C" {
- #endif
- #define __CM0_REV 0
- #define __MPU_PRESENT 0
- #define __NVIC_PRIO_BITS 2
- #define __Vendor_SysTickConfig 0
-
-
- typedef enum
- {
- NonMaskableInt_IRQn = -14,
- HardFault_IRQn = -13,
- SVC_IRQn = -5,
- PendSV_IRQn = -2,
- SysTick_IRQn = -1,
- WWDG_IRQn = 0,
- RTC_IRQn = 2,
- FLASH_IRQn = 3,
- RCC_IRQn = 4,
- EXTI0_1_IRQn = 5,
- EXTI2_3_IRQn = 6,
- EXTI4_15_IRQn = 7,
- DMA1_Channel1_IRQn = 9,
- DMA1_Channel2_3_IRQn = 10,
- DMA1_Channel4_5_IRQn = 11,
- ADC1_IRQn = 12,
- TIM1_BRK_UP_TRG_COM_IRQn = 13,
- TIM1_CC_IRQn = 14,
- TIM3_IRQn = 16,
- TIM14_IRQn = 19,
- TIM16_IRQn = 21,
- TIM17_IRQn = 22,
- I2C1_IRQn = 23,
- SPI1_IRQn = 25,
- USART1_IRQn = 27
- } IRQn_Type;
- #include "core_cm0.h"
- #include "system_stm32f0xx.h"
- #include <stdint.h>
- typedef struct
- {
- __IO uint32_t ISR;
- __IO uint32_t IER;
- __IO uint32_t CR;
- __IO uint32_t CFGR1;
- __IO uint32_t CFGR2;
- __IO uint32_t SMPR;
- uint32_t RESERVED1;
- uint32_t RESERVED2;
- __IO uint32_t TR;
- uint32_t RESERVED3;
- __IO uint32_t CHSELR;
- uint32_t RESERVED4[5];
- __IO uint32_t DR;
- } ADC_TypeDef;
- typedef struct
- {
- __IO uint32_t CCR;
- } ADC_Common_TypeDef;
- typedef struct
- {
- __IO uint32_t DR;
- __IO uint8_t IDR;
- uint8_t RESERVED0;
- uint16_t RESERVED1;
- __IO uint32_t CR;
- uint32_t RESERVED2;
- __IO uint32_t INIT;
- __IO uint32_t RESERVED3;
- } CRC_TypeDef;
- typedef struct
- {
- __IO uint32_t IDCODE;
- __IO uint32_t CR;
- __IO uint32_t APB1FZ;
- __IO uint32_t APB2FZ;
- }DBGMCU_TypeDef;
- typedef struct
- {
- __IO uint32_t CCR;
- __IO uint32_t CNDTR;
- __IO uint32_t CPAR;
- __IO uint32_t CMAR;
- } DMA_Channel_TypeDef;
- typedef struct
- {
- __IO uint32_t ISR;
- __IO uint32_t IFCR;
- } DMA_TypeDef;
- typedef struct
- {
- __IO uint32_t IMR;
- __IO uint32_t EMR;
- __IO uint32_t RTSR;
- __IO uint32_t FTSR;
- __IO uint32_t SWIER;
- __IO uint32_t PR;
- } EXTI_TypeDef;
- typedef struct
- {
- __IO uint32_t ACR;
- __IO uint32_t KEYR;
- __IO uint32_t OPTKEYR;
- __IO uint32_t SR;
- __IO uint32_t CR;
- __IO uint32_t AR;
- __IO uint32_t RESERVED;
- __IO uint32_t OBR;
- __IO uint32_t WRPR;
- } FLASH_TypeDef;
- typedef struct
- {
- __IO uint16_t RDP;
- __IO uint16_t USER;
- __IO uint16_t DATA0;
- __IO uint16_t DATA1;
- __IO uint16_t WRP0;
- } OB_TypeDef;
- typedef struct
- {
- __IO uint32_t MODER;
- __IO uint32_t OTYPER;
- __IO uint32_t OSPEEDR;
- __IO uint32_t PUPDR;
- __IO uint32_t IDR;
- __IO uint32_t ODR;
- __IO uint32_t BSRR;
- __IO uint32_t LCKR;
- __IO uint32_t AFR[2];
- __IO uint32_t BRR;
- } GPIO_TypeDef;
- typedef struct
- {
- __IO uint32_t CFGR1;
- uint32_t RESERVED;
- __IO uint32_t EXTICR[4];
- __IO uint32_t CFGR2;
- } SYSCFG_TypeDef;
- typedef struct
- {
- __IO uint32_t CR1;
- __IO uint32_t CR2;
- __IO uint32_t OAR1;
- __IO uint32_t OAR2;
- __IO uint32_t TIMINGR;
- __IO uint32_t TIMEOUTR;
- __IO uint32_t ISR;
- __IO uint32_t ICR;
- __IO uint32_t PECR;
- __IO uint32_t RXDR;
- __IO uint32_t TXDR;
- } I2C_TypeDef;
- typedef struct
- {
- __IO uint32_t KR;
- __IO uint32_t PR;
- __IO uint32_t RLR;
- __IO uint32_t SR;
- __IO uint32_t WINR;
- } IWDG_TypeDef;
- typedef struct
- {
- __IO uint32_t CR;
- __IO uint32_t CSR;
- } PWR_TypeDef;
- typedef struct
- {
- __IO uint32_t CR;
- __IO uint32_t CFGR;
- __IO uint32_t CIR;
- __IO uint32_t APB2RSTR;
- __IO uint32_t APB1RSTR;
- __IO uint32_t AHBENR;
- __IO uint32_t APB2ENR;
- __IO uint32_t APB1ENR;
- __IO uint32_t BDCR;
- __IO uint32_t CSR;
- __IO uint32_t AHBRSTR;
- __IO uint32_t CFGR2;
- __IO uint32_t CFGR3;
- __IO uint32_t CR2;
- } RCC_TypeDef;
- typedef struct
- {
- __IO uint32_t TR;
- __IO uint32_t DR;
- __IO uint32_t CR;
- __IO uint32_t ISR;
- __IO uint32_t PRER;
- uint32_t RESERVED1;
- uint32_t RESERVED2;
- __IO uint32_t ALRMAR;
- uint32_t RESERVED3;
- __IO uint32_t WPR;
- __IO uint32_t SSR;
- __IO uint32_t SHIFTR;
- __IO uint32_t TSTR;
- __IO uint32_t TSDR;
- __IO uint32_t TSSSR;
- __IO uint32_t CALR;
- __IO uint32_t TAFCR;
- __IO uint32_t ALRMASSR;
- } RTC_TypeDef;
- typedef struct
- {
- __IO uint32_t CR1;
- __IO uint32_t CR2;
- __IO uint32_t SR;
- __IO uint32_t DR;
- __IO uint32_t CRCPR;
- __IO uint32_t RXCRCR;
- __IO uint32_t TXCRCR;
- __IO uint32_t I2SCFGR;
- } SPI_TypeDef;
- typedef struct
- {
- __IO uint32_t CR1;
- __IO uint32_t CR2;
- __IO uint32_t SMCR;
- __IO uint32_t DIER;
- __IO uint32_t SR;
- __IO uint32_t EGR;
- __IO uint32_t CCMR1;
- __IO uint32_t CCMR2;
- __IO uint32_t CCER;
- __IO uint32_t CNT;
- __IO uint32_t PSC;
- __IO uint32_t ARR;
- __IO uint32_t RCR;
- __IO uint32_t CCR1;
- __IO uint32_t CCR2;
- __IO uint32_t CCR3;
- __IO uint32_t CCR4;
- __IO uint32_t BDTR;
- __IO uint32_t DCR;
- __IO uint32_t DMAR;
- __IO uint32_t OR;
- } TIM_TypeDef;
-
- typedef struct
- {
- __IO uint32_t CR1;
- __IO uint32_t CR2;
- __IO uint32_t CR3;
- __IO uint32_t BRR;
- __IO uint32_t GTPR;
- __IO uint32_t RTOR;
- __IO uint32_t RQR;
- __IO uint32_t ISR;
- __IO uint32_t ICR;
- __IO uint16_t RDR;
- uint16_t RESERVED1;
- __IO uint16_t TDR;
- uint16_t RESERVED2;
- } USART_TypeDef;
- typedef struct
- {
- __IO uint32_t CR;
- __IO uint32_t CFR;
- __IO uint32_t SR;
- } WWDG_TypeDef;
-
- #define FLASH_BASE 0x08000000UL
- #define FLASH_BANK1_END 0x08007FFFUL
- #define SRAM_BASE 0x20000000UL
- #define PERIPH_BASE 0x40000000UL
- #define APBPERIPH_BASE PERIPH_BASE
- #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)
- #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)
- #define TIM3_BASE (APBPERIPH_BASE + 0x00000400UL)
- #define TIM14_BASE (APBPERIPH_BASE + 0x00002000UL)
- #define RTC_BASE (APBPERIPH_BASE + 0x00002800UL)
- #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL)
- #define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL)
- #define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL)
- #define PWR_BASE (APBPERIPH_BASE + 0x00007000UL)
- #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL)
- #define EXTI_BASE (APBPERIPH_BASE + 0x00010400UL)
- #define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL)
- #define ADC_BASE (APBPERIPH_BASE + 0x00012708UL)
- #define TIM1_BASE (APBPERIPH_BASE + 0x00012C00UL)
- #define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL)
- #define USART1_BASE (APBPERIPH_BASE + 0x00013800UL)
- #define TIM16_BASE (APBPERIPH_BASE + 0x00014400UL)
- #define TIM17_BASE (APBPERIPH_BASE + 0x00014800UL)
- #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800UL)
- #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL)
- #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL)
- #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL)
- #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)
- #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)
- #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)
- #define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL)
- #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL)
- #define OB_BASE 0x1FFFF800UL
- #define FLASHSIZE_BASE 0x1FFFF7CCUL
- #define UID_BASE 0x1FFFF7ACUL
- #define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)
- #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000UL)
- #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400UL)
- #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800UL)
- #define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00UL)
- #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400UL)
-
-
- #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
- #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
- #define RTC ((RTC_TypeDef *) RTC_BASE)
- #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
- #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
- #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
- #define PWR ((PWR_TypeDef *) PWR_BASE)
- #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
- #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
- #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
- #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
- #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
- #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
- #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
- #define USART1 ((USART_TypeDef *) USART1_BASE)
- #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
- #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
- #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
- #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
- #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
- #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
- #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
- #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
- #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
- #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
- #define OB ((OB_TypeDef *) OB_BASE)
- #define RCC ((RCC_TypeDef *) RCC_BASE)
- #define CRC ((CRC_TypeDef *) CRC_BASE)
- #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
- #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
- #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
- #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
- #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
- #define LSI_STARTUP_TIME 85U
- #define ADC_ISR_ADRDY_Pos (0U)
- #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos)
- #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk
- #define ADC_ISR_EOSMP_Pos (1U)
- #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos)
- #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk
- #define ADC_ISR_EOC_Pos (2U)
- #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos)
- #define ADC_ISR_EOC ADC_ISR_EOC_Msk
- #define ADC_ISR_EOS_Pos (3U)
- #define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos)
- #define ADC_ISR_EOS ADC_ISR_EOS_Msk
- #define ADC_ISR_OVR_Pos (4U)
- #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos)
- #define ADC_ISR_OVR ADC_ISR_OVR_Msk
- #define ADC_ISR_AWD1_Pos (7U)
- #define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos)
- #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk
- #define ADC_ISR_AWD (ADC_ISR_AWD1)
- #define ADC_ISR_EOSEQ (ADC_ISR_EOS)
- #define ADC_IER_ADRDYIE_Pos (0U)
- #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos)
- #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk
- #define ADC_IER_EOSMPIE_Pos (1U)
- #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos)
- #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk
- #define ADC_IER_EOCIE_Pos (2U)
- #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos)
- #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk
- #define ADC_IER_EOSIE_Pos (3U)
- #define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos)
- #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk
- #define ADC_IER_OVRIE_Pos (4U)
- #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos)
- #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk
- #define ADC_IER_AWD1IE_Pos (7U)
- #define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos)
- #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk
- #define ADC_IER_AWDIE (ADC_IER_AWD1IE)
- #define ADC_IER_EOSEQIE (ADC_IER_EOSIE)
- #define ADC_CR_ADEN_Pos (0U)
- #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos)
- #define ADC_CR_ADEN ADC_CR_ADEN_Msk
- #define ADC_CR_ADDIS_Pos (1U)
- #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos)
- #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk
- #define ADC_CR_ADSTART_Pos (2U)
- #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos)
- #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk
- #define ADC_CR_ADSTP_Pos (4U)
- #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos)
- #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk
- #define ADC_CR_ADCAL_Pos (31U)
- #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos)
- #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk
- #define ADC_CFGR1_DMAEN_Pos (0U)
- #define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos)
- #define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk
- #define ADC_CFGR1_DMACFG_Pos (1U)
- #define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos)
- #define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk
- #define ADC_CFGR1_SCANDIR_Pos (2U)
- #define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos)
- #define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk
- #define ADC_CFGR1_RES_Pos (3U)
- #define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos)
- #define ADC_CFGR1_RES ADC_CFGR1_RES_Msk
- #define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos)
- #define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos)
- #define ADC_CFGR1_ALIGN_Pos (5U)
- #define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos)
- #define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk
- #define ADC_CFGR1_EXTSEL_Pos (6U)
- #define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos)
- #define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk
- #define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos)
- #define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos)
- #define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos)
- #define ADC_CFGR1_EXTEN_Pos (10U)
- #define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos)
- #define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk
- #define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos)
- #define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos)
- #define ADC_CFGR1_OVRMOD_Pos (12U)
- #define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos)
- #define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk
- #define ADC_CFGR1_CONT_Pos (13U)
- #define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos)
- #define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk
- #define ADC_CFGR1_WAIT_Pos (14U)
- #define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos)
- #define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk
- #define ADC_CFGR1_AUTOFF_Pos (15U)
- #define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos)
- #define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk
- #define ADC_CFGR1_DISCEN_Pos (16U)
- #define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos)
- #define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk
- #define ADC_CFGR1_AWD1SGL_Pos (22U)
- #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos)
- #define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk
- #define ADC_CFGR1_AWD1EN_Pos (23U)
- #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos)
- #define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk
- #define ADC_CFGR1_AWD1CH_Pos (26U)
- #define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos)
- #define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk
- #define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos)
- #define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos)
- #define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos)
- #define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos)
- #define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos)
- #define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT)
- #define ADC_CFGR1_AWDSGL (ADC_CFGR1_AWD1SGL)
- #define ADC_CFGR1_AWDEN (ADC_CFGR1_AWD1EN)
- #define ADC_CFGR1_AWDCH (ADC_CFGR1_AWD1CH)
- #define ADC_CFGR1_AWDCH_0 (ADC_CFGR1_AWD1CH_0)
- #define ADC_CFGR1_AWDCH_1 (ADC_CFGR1_AWD1CH_1)
- #define ADC_CFGR1_AWDCH_2 (ADC_CFGR1_AWD1CH_2)
- #define ADC_CFGR1_AWDCH_3 (ADC_CFGR1_AWD1CH_3)
- #define ADC_CFGR1_AWDCH_4 (ADC_CFGR1_AWD1CH_4)
- #define ADC_CFGR2_CKMODE_Pos (30U)
- #define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos)
- #define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk
- #define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos)
- #define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos)
- #define ADC_CFGR2_JITOFFDIV4 (ADC_CFGR2_CKMODE_1)
- #define ADC_CFGR2_JITOFFDIV2 (ADC_CFGR2_CKMODE_0)
- #define ADC_SMPR_SMP_Pos (0U)
- #define ADC_SMPR_SMP_Msk (0x7UL << ADC_SMPR_SMP_Pos)
- #define ADC_SMPR_SMP ADC_SMPR_SMP_Msk
- #define ADC_SMPR_SMP_0 (0x1UL << ADC_SMPR_SMP_Pos)
- #define ADC_SMPR_SMP_1 (0x2UL << ADC_SMPR_SMP_Pos)
- #define ADC_SMPR_SMP_2 (0x4UL << ADC_SMPR_SMP_Pos)
- #define ADC_SMPR1_SMPR (ADC_SMPR_SMP)
- #define ADC_SMPR1_SMPR_0 (ADC_SMPR_SMP_0)
- #define ADC_SMPR1_SMPR_1 (ADC_SMPR_SMP_1)
- #define ADC_SMPR1_SMPR_2 (ADC_SMPR_SMP_2)
- #define ADC_TR1_LT1_Pos (0U)
- #define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos)
- #define ADC_TR1_LT1 ADC_TR1_LT1_Msk
- #define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos)
- #define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos)
- #define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos)
- #define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos)
- #define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos)
- #define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos)
- #define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos)
- #define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos)
- #define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos)
- #define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos)
- #define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos)
- #define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos)
- #define ADC_TR1_HT1_Pos (16U)
- #define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos)
- #define ADC_TR1_HT1 ADC_TR1_HT1_Msk
- #define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos)
- #define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos)
- #define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos)
- #define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos)
- #define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos)
- #define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos)
- #define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos)
- #define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos)
- #define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos)
- #define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos)
- #define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos)
- #define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos)
- #define ADC_TR_HT (ADC_TR1_HT1)
- #define ADC_TR_LT (ADC_TR1_LT1)
- #define ADC_HTR_HT (ADC_TR1_HT1)
- #define ADC_LTR_LT (ADC_TR1_LT1)
- #define ADC_CHSELR_CHSEL_Pos (0U)
- #define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos)
- #define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk
- #define ADC_CHSELR_CHSEL18_Pos (18U)
- #define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos)
- #define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk
- #define ADC_CHSELR_CHSEL17_Pos (17U)
- #define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos)
- #define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk
- #define ADC_CHSELR_CHSEL16_Pos (16U)
- #define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos)
- #define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk
- #define ADC_CHSELR_CHSEL15_Pos (15U)
- #define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos)
- #define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk
- #define ADC_CHSELR_CHSEL14_Pos (14U)
- #define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos)
- #define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk
- #define ADC_CHSELR_CHSEL13_Pos (13U)
- #define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos)
- #define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk
- #define ADC_CHSELR_CHSEL12_Pos (12U)
- #define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos)
- #define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk
- #define ADC_CHSELR_CHSEL11_Pos (11U)
- #define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos)
- #define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk
- #define ADC_CHSELR_CHSEL10_Pos (10U)
- #define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos)
- #define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk
- #define ADC_CHSELR_CHSEL9_Pos (9U)
- #define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos)
- #define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk
- #define ADC_CHSELR_CHSEL8_Pos (8U)
- #define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos)
- #define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk
- #define ADC_CHSELR_CHSEL7_Pos (7U)
- #define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos)
- #define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk
- #define ADC_CHSELR_CHSEL6_Pos (6U)
- #define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos)
- #define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk
- #define ADC_CHSELR_CHSEL5_Pos (5U)
- #define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos)
- #define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk
- #define ADC_CHSELR_CHSEL4_Pos (4U)
- #define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos)
- #define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk
- #define ADC_CHSELR_CHSEL3_Pos (3U)
- #define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos)
- #define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk
- #define ADC_CHSELR_CHSEL2_Pos (2U)
- #define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos)
- #define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk
- #define ADC_CHSELR_CHSEL1_Pos (1U)
- #define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos)
- #define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk
- #define ADC_CHSELR_CHSEL0_Pos (0U)
- #define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos)
- #define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk
- #define ADC_DR_DATA_Pos (0U)
- #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos)
- #define ADC_DR_DATA ADC_DR_DATA_Msk
- #define ADC_DR_DATA_0 (0x0001UL << ADC_DR_DATA_Pos)
- #define ADC_DR_DATA_1 (0x0002UL << ADC_DR_DATA_Pos)
- #define ADC_DR_DATA_2 (0x0004UL << ADC_DR_DATA_Pos)
- #define ADC_DR_DATA_3 (0x0008UL << ADC_DR_DATA_Pos)
- #define ADC_DR_DATA_4 (0x0010UL << ADC_DR_DATA_Pos)
- #define ADC_DR_DATA_5 (0x0020UL << ADC_DR_DATA_Pos)
- #define ADC_DR_DATA_6 (0x0040UL << ADC_DR_DATA_Pos)
- #define ADC_DR_DATA_7 (0x0080UL << ADC_DR_DATA_Pos)
- #define ADC_DR_DATA_8 (0x0100UL << ADC_DR_DATA_Pos)
- #define ADC_DR_DATA_9 (0x0200UL << ADC_DR_DATA_Pos)
- #define ADC_DR_DATA_10 (0x0400UL << ADC_DR_DATA_Pos)
- #define ADC_DR_DATA_11 (0x0800UL << ADC_DR_DATA_Pos)
- #define ADC_DR_DATA_12 (0x1000UL << ADC_DR_DATA_Pos)
- #define ADC_DR_DATA_13 (0x2000UL << ADC_DR_DATA_Pos)
- #define ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos)
- #define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos)
- #define ADC_CCR_VREFEN_Pos (22U)
- #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos)
- #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk
- #define ADC_CCR_TSEN_Pos (23U)
- #define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos)
- #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk
- #define CRC_DR_DR_Pos (0U)
- #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)
- #define CRC_DR_DR CRC_DR_DR_Msk
- #define CRC_IDR_IDR ((uint8_t)0xFFU)
- #define CRC_CR_RESET_Pos (0U)
- #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)
- #define CRC_CR_RESET CRC_CR_RESET_Msk
- #define CRC_CR_REV_IN_Pos (5U)
- #define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos)
- #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk
- #define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos)
- #define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos)
- #define CRC_CR_REV_OUT_Pos (7U)
- #define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos)
- #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk
- #define CRC_INIT_INIT_Pos (0U)
- #define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)
- #define CRC_INIT_INIT CRC_INIT_INIT_Msk
- #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
- #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)
- #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
- #define DBGMCU_IDCODE_REV_ID_Pos (16U)
- #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)
- #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
- #define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos)
- #define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos)
- #define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos)
- #define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos)
- #define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos)
- #define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos)
- #define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos)
- #define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos)
- #define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos)
- #define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos)
- #define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos)
- #define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos)
- #define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos)
- #define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos)
- #define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos)
- #define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos)
- #define DBGMCU_CR_DBG_STOP_Pos (1U)
- #define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)
- #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
- #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
- #define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)
- #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
- #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
- #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos)
- #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
- #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
- #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos)
- #define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
- #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
- #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos)
- #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
- #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
- #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos)
- #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
- #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
- #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos)
- #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
- #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
- #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos)
- #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
- #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (11U)
- #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos)
- #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
- #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos (17U)
- #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos)
- #define DBGMCU_APB2_FZ_DBG_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk
- #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos (18U)
- #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos)
- #define DBGMCU_APB2_FZ_DBG_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk
- #define DMA_ISR_GIF1_Pos (0U)
- #define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos)
- #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk
- #define DMA_ISR_TCIF1_Pos (1U)
- #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos)
- #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk
- #define DMA_ISR_HTIF1_Pos (2U)
- #define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos)
- #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk
- #define DMA_ISR_TEIF1_Pos (3U)
- #define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos)
- #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk
- #define DMA_ISR_GIF2_Pos (4U)
- #define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos)
- #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk
- #define DMA_ISR_TCIF2_Pos (5U)
- #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos)
- #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk
- #define DMA_ISR_HTIF2_Pos (6U)
- #define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos)
- #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk
- #define DMA_ISR_TEIF2_Pos (7U)
- #define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos)
- #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk
- #define DMA_ISR_GIF3_Pos (8U)
- #define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos)
- #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk
- #define DMA_ISR_TCIF3_Pos (9U)
- #define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos)
- #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk
- #define DMA_ISR_HTIF3_Pos (10U)
- #define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos)
- #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk
- #define DMA_ISR_TEIF3_Pos (11U)
- #define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos)
- #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk
- #define DMA_ISR_GIF4_Pos (12U)
- #define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos)
- #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk
- #define DMA_ISR_TCIF4_Pos (13U)
- #define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos)
- #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk
- #define DMA_ISR_HTIF4_Pos (14U)
- #define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos)
- #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk
- #define DMA_ISR_TEIF4_Pos (15U)
- #define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos)
- #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk
- #define DMA_ISR_GIF5_Pos (16U)
- #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos)
- #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk
- #define DMA_ISR_TCIF5_Pos (17U)
- #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos)
- #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk
- #define DMA_ISR_HTIF5_Pos (18U)
- #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos)
- #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk
- #define DMA_ISR_TEIF5_Pos (19U)
- #define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos)
- #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk
- #define DMA_IFCR_CGIF1_Pos (0U)
- #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos)
- #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk
- #define DMA_IFCR_CTCIF1_Pos (1U)
- #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos)
- #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk
- #define DMA_IFCR_CHTIF1_Pos (2U)
- #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos)
- #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk
- #define DMA_IFCR_CTEIF1_Pos (3U)
- #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos)
- #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk
- #define DMA_IFCR_CGIF2_Pos (4U)
- #define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos)
- #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk
- #define DMA_IFCR_CTCIF2_Pos (5U)
- #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos)
- #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk
- #define DMA_IFCR_CHTIF2_Pos (6U)
- #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos)
- #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk
- #define DMA_IFCR_CTEIF2_Pos (7U)
- #define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos)
- #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk
- #define DMA_IFCR_CGIF3_Pos (8U)
- #define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos)
- #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk
- #define DMA_IFCR_CTCIF3_Pos (9U)
- #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos)
- #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk
- #define DMA_IFCR_CHTIF3_Pos (10U)
- #define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos)
- #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk
- #define DMA_IFCR_CTEIF3_Pos (11U)
- #define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos)
- #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk
- #define DMA_IFCR_CGIF4_Pos (12U)
- #define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos)
- #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk
- #define DMA_IFCR_CTCIF4_Pos (13U)
- #define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos)
- #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk
- #define DMA_IFCR_CHTIF4_Pos (14U)
- #define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos)
- #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk
- #define DMA_IFCR_CTEIF4_Pos (15U)
- #define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos)
- #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk
- #define DMA_IFCR_CGIF5_Pos (16U)
- #define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos)
- #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk
- #define DMA_IFCR_CTCIF5_Pos (17U)
- #define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos)
- #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk
- #define DMA_IFCR_CHTIF5_Pos (18U)
- #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos)
- #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk
- #define DMA_IFCR_CTEIF5_Pos (19U)
- #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos)
- #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk
- #define DMA_CCR_EN_Pos (0U)
- #define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos)
- #define DMA_CCR_EN DMA_CCR_EN_Msk
- #define DMA_CCR_TCIE_Pos (1U)
- #define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos)
- #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk
- #define DMA_CCR_HTIE_Pos (2U)
- #define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos)
- #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk
- #define DMA_CCR_TEIE_Pos (3U)
- #define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos)
- #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk
- #define DMA_CCR_DIR_Pos (4U)
- #define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos)
- #define DMA_CCR_DIR DMA_CCR_DIR_Msk
- #define DMA_CCR_CIRC_Pos (5U)
- #define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos)
- #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk
- #define DMA_CCR_PINC_Pos (6U)
- #define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos)
- #define DMA_CCR_PINC DMA_CCR_PINC_Msk
- #define DMA_CCR_MINC_Pos (7U)
- #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos)
- #define DMA_CCR_MINC DMA_CCR_MINC_Msk
- #define DMA_CCR_PSIZE_Pos (8U)
- #define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos)
- #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk
- #define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos)
- #define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos)
- #define DMA_CCR_MSIZE_Pos (10U)
- #define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos)
- #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk
- #define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos)
- #define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos)
- #define DMA_CCR_PL_Pos (12U)
- #define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos)
- #define DMA_CCR_PL DMA_CCR_PL_Msk
- #define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos)
- #define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos)
- #define DMA_CCR_MEM2MEM_Pos (14U)
- #define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos)
- #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk
- #define DMA_CNDTR_NDT_Pos (0U)
- #define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos)
- #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk
- #define DMA_CPAR_PA_Pos (0U)
- #define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)
- #define DMA_CPAR_PA DMA_CPAR_PA_Msk
- #define DMA_CMAR_MA_Pos (0U)
- #define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)
- #define DMA_CMAR_MA DMA_CMAR_MA_Msk
- #define EXTI_IMR_MR0_Pos (0U)
- #define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos)
- #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk
- #define EXTI_IMR_MR1_Pos (1U)
- #define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos)
- #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk
- #define EXTI_IMR_MR2_Pos (2U)
- #define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos)
- #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk
- #define EXTI_IMR_MR3_Pos (3U)
- #define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos)
- #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk
- #define EXTI_IMR_MR4_Pos (4U)
- #define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos)
- #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk
- #define EXTI_IMR_MR5_Pos (5U)
- #define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos)
- #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk
- #define EXTI_IMR_MR6_Pos (6U)
- #define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos)
- #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk
- #define EXTI_IMR_MR7_Pos (7U)
- #define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos)
- #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk
- #define EXTI_IMR_MR8_Pos (8U)
- #define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos)
- #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk
- #define EXTI_IMR_MR9_Pos (9U)
- #define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos)
- #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk
- #define EXTI_IMR_MR10_Pos (10U)
- #define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos)
- #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk
- #define EXTI_IMR_MR11_Pos (11U)
- #define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos)
- #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk
- #define EXTI_IMR_MR12_Pos (12U)
- #define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos)
- #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk
- #define EXTI_IMR_MR13_Pos (13U)
- #define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos)
- #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk
- #define EXTI_IMR_MR14_Pos (14U)
- #define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos)
- #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk
- #define EXTI_IMR_MR15_Pos (15U)
- #define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos)
- #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk
- #define EXTI_IMR_MR17_Pos (17U)
- #define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos)
- #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk
- #define EXTI_IMR_MR19_Pos (19U)
- #define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos)
- #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk
- #define EXTI_IMR_IM0 EXTI_IMR_MR0
- #define EXTI_IMR_IM1 EXTI_IMR_MR1
- #define EXTI_IMR_IM2 EXTI_IMR_MR2
- #define EXTI_IMR_IM3 EXTI_IMR_MR3
- #define EXTI_IMR_IM4 EXTI_IMR_MR4
- #define EXTI_IMR_IM5 EXTI_IMR_MR5
- #define EXTI_IMR_IM6 EXTI_IMR_MR6
- #define EXTI_IMR_IM7 EXTI_IMR_MR7
- #define EXTI_IMR_IM8 EXTI_IMR_MR8
- #define EXTI_IMR_IM9 EXTI_IMR_MR9
- #define EXTI_IMR_IM10 EXTI_IMR_MR10
- #define EXTI_IMR_IM11 EXTI_IMR_MR11
- #define EXTI_IMR_IM12 EXTI_IMR_MR12
- #define EXTI_IMR_IM13 EXTI_IMR_MR13
- #define EXTI_IMR_IM14 EXTI_IMR_MR14
- #define EXTI_IMR_IM15 EXTI_IMR_MR15
- #define EXTI_IMR_IM17 EXTI_IMR_MR17
- #define EXTI_IMR_IM19 EXTI_IMR_MR19
- #define EXTI_IMR_IM_Pos (0U)
- #define EXTI_IMR_IM_Msk (0x8EFFFFUL << EXTI_IMR_IM_Pos)
- #define EXTI_IMR_IM EXTI_IMR_IM_Msk
- #define EXTI_EMR_MR0_Pos (0U)
- #define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos)
- #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk
- #define EXTI_EMR_MR1_Pos (1U)
- #define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos)
- #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk
- #define EXTI_EMR_MR2_Pos (2U)
- #define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos)
- #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk
- #define EXTI_EMR_MR3_Pos (3U)
- #define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos)
- #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk
- #define EXTI_EMR_MR4_Pos (4U)
- #define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos)
- #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk
- #define EXTI_EMR_MR5_Pos (5U)
- #define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos)
- #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk
- #define EXTI_EMR_MR6_Pos (6U)
- #define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos)
- #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk
- #define EXTI_EMR_MR7_Pos (7U)
- #define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos)
- #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk
- #define EXTI_EMR_MR8_Pos (8U)
- #define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos)
- #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk
- #define EXTI_EMR_MR9_Pos (9U)
- #define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos)
- #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk
- #define EXTI_EMR_MR10_Pos (10U)
- #define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos)
- #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk
- #define EXTI_EMR_MR11_Pos (11U)
- #define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos)
- #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk
- #define EXTI_EMR_MR12_Pos (12U)
- #define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos)
- #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk
- #define EXTI_EMR_MR13_Pos (13U)
- #define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos)
- #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk
- #define EXTI_EMR_MR14_Pos (14U)
- #define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos)
- #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk
- #define EXTI_EMR_MR15_Pos (15U)
- #define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos)
- #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk
- #define EXTI_EMR_MR17_Pos (17U)
- #define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos)
- #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk
- #define EXTI_EMR_MR19_Pos (19U)
- #define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos)
- #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk
- #define EXTI_EMR_EM0 EXTI_EMR_MR0
- #define EXTI_EMR_EM1 EXTI_EMR_MR1
- #define EXTI_EMR_EM2 EXTI_EMR_MR2
- #define EXTI_EMR_EM3 EXTI_EMR_MR3
- #define EXTI_EMR_EM4 EXTI_EMR_MR4
- #define EXTI_EMR_EM5 EXTI_EMR_MR5
- #define EXTI_EMR_EM6 EXTI_EMR_MR6
- #define EXTI_EMR_EM7 EXTI_EMR_MR7
- #define EXTI_EMR_EM8 EXTI_EMR_MR8
- #define EXTI_EMR_EM9 EXTI_EMR_MR9
- #define EXTI_EMR_EM10 EXTI_EMR_MR10
- #define EXTI_EMR_EM11 EXTI_EMR_MR11
- #define EXTI_EMR_EM12 EXTI_EMR_MR12
- #define EXTI_EMR_EM13 EXTI_EMR_MR13
- #define EXTI_EMR_EM14 EXTI_EMR_MR14
- #define EXTI_EMR_EM15 EXTI_EMR_MR15
- #define EXTI_EMR_EM17 EXTI_EMR_MR17
- #define EXTI_EMR_EM19 EXTI_EMR_MR19
- #define EXTI_RTSR_TR0_Pos (0U)
- #define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos)
- #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk
- #define EXTI_RTSR_TR1_Pos (1U)
- #define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos)
- #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk
- #define EXTI_RTSR_TR2_Pos (2U)
- #define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos)
- #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk
- #define EXTI_RTSR_TR3_Pos (3U)
- #define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos)
- #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk
- #define EXTI_RTSR_TR4_Pos (4U)
- #define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos)
- #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk
- #define EXTI_RTSR_TR5_Pos (5U)
- #define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos)
- #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk
- #define EXTI_RTSR_TR6_Pos (6U)
- #define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos)
- #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk
- #define EXTI_RTSR_TR7_Pos (7U)
- #define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos)
- #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk
- #define EXTI_RTSR_TR8_Pos (8U)
- #define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos)
- #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk
- #define EXTI_RTSR_TR9_Pos (9U)
- #define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos)
- #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk
- #define EXTI_RTSR_TR10_Pos (10U)
- #define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos)
- #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk
- #define EXTI_RTSR_TR11_Pos (11U)
- #define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos)
- #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk
- #define EXTI_RTSR_TR12_Pos (12U)
- #define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos)
- #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk
- #define EXTI_RTSR_TR13_Pos (13U)
- #define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos)
- #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk
- #define EXTI_RTSR_TR14_Pos (14U)
- #define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos)
- #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk
- #define EXTI_RTSR_TR15_Pos (15U)
- #define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos)
- #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk
- #define EXTI_RTSR_TR16_Pos (16U)
- #define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos)
- #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk
- #define EXTI_RTSR_TR17_Pos (17U)
- #define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos)
- #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk
- #define EXTI_RTSR_TR19_Pos (19U)
- #define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos)
- #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk
- #define EXTI_RTSR_RT0 EXTI_RTSR_TR0
- #define EXTI_RTSR_RT1 EXTI_RTSR_TR1
- #define EXTI_RTSR_RT2 EXTI_RTSR_TR2
- #define EXTI_RTSR_RT3 EXTI_RTSR_TR3
- #define EXTI_RTSR_RT4 EXTI_RTSR_TR4
- #define EXTI_RTSR_RT5 EXTI_RTSR_TR5
- #define EXTI_RTSR_RT6 EXTI_RTSR_TR6
- #define EXTI_RTSR_RT7 EXTI_RTSR_TR7
- #define EXTI_RTSR_RT8 EXTI_RTSR_TR8
- #define EXTI_RTSR_RT9 EXTI_RTSR_TR9
- #define EXTI_RTSR_RT10 EXTI_RTSR_TR10
- #define EXTI_RTSR_RT11 EXTI_RTSR_TR11
- #define EXTI_RTSR_RT12 EXTI_RTSR_TR12
- #define EXTI_RTSR_RT13 EXTI_RTSR_TR13
- #define EXTI_RTSR_RT14 EXTI_RTSR_TR14
- #define EXTI_RTSR_RT15 EXTI_RTSR_TR15
- #define EXTI_RTSR_RT16 EXTI_RTSR_TR16
- #define EXTI_RTSR_RT17 EXTI_RTSR_TR17
- #define EXTI_RTSR_RT19 EXTI_RTSR_TR19
- #define EXTI_FTSR_TR0_Pos (0U)
- #define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos)
- #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk
- #define EXTI_FTSR_TR1_Pos (1U)
- #define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos)
- #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk
- #define EXTI_FTSR_TR2_Pos (2U)
- #define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos)
- #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk
- #define EXTI_FTSR_TR3_Pos (3U)
- #define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos)
- #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk
- #define EXTI_FTSR_TR4_Pos (4U)
- #define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos)
- #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk
- #define EXTI_FTSR_TR5_Pos (5U)
- #define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos)
- #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk
- #define EXTI_FTSR_TR6_Pos (6U)
- #define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos)
- #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk
- #define EXTI_FTSR_TR7_Pos (7U)
- #define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos)
- #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk
- #define EXTI_FTSR_TR8_Pos (8U)
- #define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos)
- #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk
- #define EXTI_FTSR_TR9_Pos (9U)
- #define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos)
- #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk
- #define EXTI_FTSR_TR10_Pos (10U)
- #define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos)
- #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk
- #define EXTI_FTSR_TR11_Pos (11U)
- #define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos)
- #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk
- #define EXTI_FTSR_TR12_Pos (12U)
- #define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos)
- #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk
- #define EXTI_FTSR_TR13_Pos (13U)
- #define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos)
- #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk
- #define EXTI_FTSR_TR14_Pos (14U)
- #define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos)
- #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk
- #define EXTI_FTSR_TR15_Pos (15U)
- #define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos)
- #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk
- #define EXTI_FTSR_TR16_Pos (16U)
- #define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos)
- #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk
- #define EXTI_FTSR_TR17_Pos (17U)
- #define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos)
- #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk
- #define EXTI_FTSR_TR19_Pos (19U)
- #define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos)
- #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk
- #define EXTI_FTSR_FT0 EXTI_FTSR_TR0
- #define EXTI_FTSR_FT1 EXTI_FTSR_TR1
- #define EXTI_FTSR_FT2 EXTI_FTSR_TR2
- #define EXTI_FTSR_FT3 EXTI_FTSR_TR3
- #define EXTI_FTSR_FT4 EXTI_FTSR_TR4
- #define EXTI_FTSR_FT5 EXTI_FTSR_TR5
- #define EXTI_FTSR_FT6 EXTI_FTSR_TR6
- #define EXTI_FTSR_FT7 EXTI_FTSR_TR7
- #define EXTI_FTSR_FT8 EXTI_FTSR_TR8
- #define EXTI_FTSR_FT9 EXTI_FTSR_TR9
- #define EXTI_FTSR_FT10 EXTI_FTSR_TR10
- #define EXTI_FTSR_FT11 EXTI_FTSR_TR11
- #define EXTI_FTSR_FT12 EXTI_FTSR_TR12
- #define EXTI_FTSR_FT13 EXTI_FTSR_TR13
- #define EXTI_FTSR_FT14 EXTI_FTSR_TR14
- #define EXTI_FTSR_FT15 EXTI_FTSR_TR15
- #define EXTI_FTSR_FT16 EXTI_FTSR_TR16
- #define EXTI_FTSR_FT17 EXTI_FTSR_TR17
- #define EXTI_FTSR_FT19 EXTI_FTSR_TR19
- #define EXTI_SWIER_SWIER0_Pos (0U)
- #define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos)
- #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk
- #define EXTI_SWIER_SWIER1_Pos (1U)
- #define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos)
- #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk
- #define EXTI_SWIER_SWIER2_Pos (2U)
- #define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos)
- #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk
- #define EXTI_SWIER_SWIER3_Pos (3U)
- #define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos)
- #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk
- #define EXTI_SWIER_SWIER4_Pos (4U)
- #define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos)
- #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk
- #define EXTI_SWIER_SWIER5_Pos (5U)
- #define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos)
- #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk
- #define EXTI_SWIER_SWIER6_Pos (6U)
- #define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos)
- #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk
- #define EXTI_SWIER_SWIER7_Pos (7U)
- #define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos)
- #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk
- #define EXTI_SWIER_SWIER8_Pos (8U)
- #define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos)
- #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk
- #define EXTI_SWIER_SWIER9_Pos (9U)
- #define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos)
- #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk
- #define EXTI_SWIER_SWIER10_Pos (10U)
- #define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos)
- #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk
- #define EXTI_SWIER_SWIER11_Pos (11U)
- #define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos)
- #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk
- #define EXTI_SWIER_SWIER12_Pos (12U)
- #define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos)
- #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk
- #define EXTI_SWIER_SWIER13_Pos (13U)
- #define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos)
- #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk
- #define EXTI_SWIER_SWIER14_Pos (14U)
- #define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos)
- #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk
- #define EXTI_SWIER_SWIER15_Pos (15U)
- #define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos)
- #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk
- #define EXTI_SWIER_SWIER16_Pos (16U)
- #define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos)
- #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk
- #define EXTI_SWIER_SWIER17_Pos (17U)
- #define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos)
- #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk
- #define EXTI_SWIER_SWIER19_Pos (19U)
- #define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos)
- #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk
- #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
- #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
- #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
- #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
- #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
- #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
- #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
- #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
- #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
- #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
- #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
- #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
- #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
- #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
- #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
- #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
- #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
- #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
- #define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
- #define EXTI_PR_PR0_Pos (0U)
- #define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos)
- #define EXTI_PR_PR0 EXTI_PR_PR0_Msk
- #define EXTI_PR_PR1_Pos (1U)
- #define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos)
- #define EXTI_PR_PR1 EXTI_PR_PR1_Msk
- #define EXTI_PR_PR2_Pos (2U)
- #define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos)
- #define EXTI_PR_PR2 EXTI_PR_PR2_Msk
- #define EXTI_PR_PR3_Pos (3U)
- #define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos)
- #define EXTI_PR_PR3 EXTI_PR_PR3_Msk
- #define EXTI_PR_PR4_Pos (4U)
- #define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos)
- #define EXTI_PR_PR4 EXTI_PR_PR4_Msk
- #define EXTI_PR_PR5_Pos (5U)
- #define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos)
- #define EXTI_PR_PR5 EXTI_PR_PR5_Msk
- #define EXTI_PR_PR6_Pos (6U)
- #define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos)
- #define EXTI_PR_PR6 EXTI_PR_PR6_Msk
- #define EXTI_PR_PR7_Pos (7U)
- #define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos)
- #define EXTI_PR_PR7 EXTI_PR_PR7_Msk
- #define EXTI_PR_PR8_Pos (8U)
- #define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos)
- #define EXTI_PR_PR8 EXTI_PR_PR8_Msk
- #define EXTI_PR_PR9_Pos (9U)
- #define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos)
- #define EXTI_PR_PR9 EXTI_PR_PR9_Msk
- #define EXTI_PR_PR10_Pos (10U)
- #define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos)
- #define EXTI_PR_PR10 EXTI_PR_PR10_Msk
- #define EXTI_PR_PR11_Pos (11U)
- #define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos)
- #define EXTI_PR_PR11 EXTI_PR_PR11_Msk
- #define EXTI_PR_PR12_Pos (12U)
- #define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos)
- #define EXTI_PR_PR12 EXTI_PR_PR12_Msk
- #define EXTI_PR_PR13_Pos (13U)
- #define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos)
- #define EXTI_PR_PR13 EXTI_PR_PR13_Msk
- #define EXTI_PR_PR14_Pos (14U)
- #define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos)
- #define EXTI_PR_PR14 EXTI_PR_PR14_Msk
- #define EXTI_PR_PR15_Pos (15U)
- #define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos)
- #define EXTI_PR_PR15 EXTI_PR_PR15_Msk
- #define EXTI_PR_PR16_Pos (16U)
- #define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos)
- #define EXTI_PR_PR16 EXTI_PR_PR16_Msk
- #define EXTI_PR_PR17_Pos (17U)
- #define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos)
- #define EXTI_PR_PR17 EXTI_PR_PR17_Msk
- #define EXTI_PR_PR19_Pos (19U)
- #define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos)
- #define EXTI_PR_PR19 EXTI_PR_PR19_Msk
- #define EXTI_PR_PIF0 EXTI_PR_PR0
- #define EXTI_PR_PIF1 EXTI_PR_PR1
- #define EXTI_PR_PIF2 EXTI_PR_PR2
- #define EXTI_PR_PIF3 EXTI_PR_PR3
- #define EXTI_PR_PIF4 EXTI_PR_PR4
- #define EXTI_PR_PIF5 EXTI_PR_PR5
- #define EXTI_PR_PIF6 EXTI_PR_PR6
- #define EXTI_PR_PIF7 EXTI_PR_PR7
- #define EXTI_PR_PIF8 EXTI_PR_PR8
- #define EXTI_PR_PIF9 EXTI_PR_PR9
- #define EXTI_PR_PIF10 EXTI_PR_PR10
- #define EXTI_PR_PIF11 EXTI_PR_PR11
- #define EXTI_PR_PIF12 EXTI_PR_PR12
- #define EXTI_PR_PIF13 EXTI_PR_PR13
- #define EXTI_PR_PIF14 EXTI_PR_PR14
- #define EXTI_PR_PIF15 EXTI_PR_PR15
- #define EXTI_PR_PIF16 EXTI_PR_PR16
- #define EXTI_PR_PIF17 EXTI_PR_PR17
- #define EXTI_PR_PIF19 EXTI_PR_PR19
- #define FLASH_ACR_LATENCY_Pos (0U)
- #define FLASH_ACR_LATENCY_Msk (0x1UL << FLASH_ACR_LATENCY_Pos)
- #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
- #define FLASH_ACR_PRFTBE_Pos (4U)
- #define FLASH_ACR_PRFTBE_Msk (0x1UL << FLASH_ACR_PRFTBE_Pos)
- #define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk
- #define FLASH_ACR_PRFTBS_Pos (5U)
- #define FLASH_ACR_PRFTBS_Msk (0x1UL << FLASH_ACR_PRFTBS_Pos)
- #define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk
- #define FLASH_KEYR_FKEYR_Pos (0U)
- #define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFUL << FLASH_KEYR_FKEYR_Pos)
- #define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk
- #define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
- #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos)
- #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk
- #define FLASH_KEY1_Pos (0U)
- #define FLASH_KEY1_Msk (0x45670123UL << FLASH_KEY1_Pos)
- #define FLASH_KEY1 FLASH_KEY1_Msk
- #define FLASH_KEY2_Pos (0U)
- #define FLASH_KEY2_Msk (0xCDEF89ABUL << FLASH_KEY2_Pos)
- #define FLASH_KEY2 FLASH_KEY2_Msk
-
- #define FLASH_OPTKEY1_Pos (0U)
- #define FLASH_OPTKEY1_Msk (0x45670123UL << FLASH_OPTKEY1_Pos)
- #define FLASH_OPTKEY1 FLASH_OPTKEY1_Msk
- #define FLASH_OPTKEY2_Pos (0U)
- #define FLASH_OPTKEY2_Msk (0xCDEF89ABUL << FLASH_OPTKEY2_Pos)
- #define FLASH_OPTKEY2 FLASH_OPTKEY2_Msk
- #define FLASH_SR_BSY_Pos (0U)
- #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)
- #define FLASH_SR_BSY FLASH_SR_BSY_Msk
- #define FLASH_SR_PGERR_Pos (2U)
- #define FLASH_SR_PGERR_Msk (0x1UL << FLASH_SR_PGERR_Pos)
- #define FLASH_SR_PGERR FLASH_SR_PGERR_Msk
- #define FLASH_SR_WRPRTERR_Pos (4U)
- #define FLASH_SR_WRPRTERR_Msk (0x1UL << FLASH_SR_WRPRTERR_Pos)
- #define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk
- #define FLASH_SR_EOP_Pos (5U)
- #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)
- #define FLASH_SR_EOP FLASH_SR_EOP_Msk
- #define FLASH_SR_WRPERR FLASH_SR_WRPRTERR
- #define FLASH_CR_PG_Pos (0U)
- #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)
- #define FLASH_CR_PG FLASH_CR_PG_Msk
- #define FLASH_CR_PER_Pos (1U)
- #define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos)
- #define FLASH_CR_PER FLASH_CR_PER_Msk
- #define FLASH_CR_MER_Pos (2U)
- #define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos)
- #define FLASH_CR_MER FLASH_CR_MER_Msk
- #define FLASH_CR_OPTPG_Pos (4U)
- #define FLASH_CR_OPTPG_Msk (0x1UL << FLASH_CR_OPTPG_Pos)
- #define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk
- #define FLASH_CR_OPTER_Pos (5U)
- #define FLASH_CR_OPTER_Msk (0x1UL << FLASH_CR_OPTER_Pos)
- #define FLASH_CR_OPTER FLASH_CR_OPTER_Msk
- #define FLASH_CR_STRT_Pos (6U)
- #define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos)
- #define FLASH_CR_STRT FLASH_CR_STRT_Msk
- #define FLASH_CR_LOCK_Pos (7U)
- #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)
- #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
- #define FLASH_CR_OPTWRE_Pos (9U)
- #define FLASH_CR_OPTWRE_Msk (0x1UL << FLASH_CR_OPTWRE_Pos)
- #define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk
- #define FLASH_CR_ERRIE_Pos (10U)
- #define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos)
- #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
- #define FLASH_CR_EOPIE_Pos (12U)
- #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)
- #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
- #define FLASH_CR_OBL_LAUNCH_Pos (13U)
- #define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos)
- #define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk
- #define FLASH_AR_FAR_Pos (0U)
- #define FLASH_AR_FAR_Msk (0xFFFFFFFFUL << FLASH_AR_FAR_Pos)
- #define FLASH_AR_FAR FLASH_AR_FAR_Msk
- #define FLASH_OBR_OPTERR_Pos (0U)
- #define FLASH_OBR_OPTERR_Msk (0x1UL << FLASH_OBR_OPTERR_Pos)
- #define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk
- #define FLASH_OBR_RDPRT1_Pos (1U)
- #define FLASH_OBR_RDPRT1_Msk (0x1UL << FLASH_OBR_RDPRT1_Pos)
- #define FLASH_OBR_RDPRT1 FLASH_OBR_RDPRT1_Msk
- #define FLASH_OBR_RDPRT2_Pos (2U)
- #define FLASH_OBR_RDPRT2_Msk (0x1UL << FLASH_OBR_RDPRT2_Pos)
- #define FLASH_OBR_RDPRT2 FLASH_OBR_RDPRT2_Msk
- #define FLASH_OBR_USER_Pos (8U)
- #define FLASH_OBR_USER_Msk (0x77UL << FLASH_OBR_USER_Pos)
- #define FLASH_OBR_USER FLASH_OBR_USER_Msk
- #define FLASH_OBR_IWDG_SW_Pos (8U)
- #define FLASH_OBR_IWDG_SW_Msk (0x1UL << FLASH_OBR_IWDG_SW_Pos)
- #define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk
- #define FLASH_OBR_nRST_STOP_Pos (9U)
- #define FLASH_OBR_nRST_STOP_Msk (0x1UL << FLASH_OBR_nRST_STOP_Pos)
- #define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk
- #define FLASH_OBR_nRST_STDBY_Pos (10U)
- #define FLASH_OBR_nRST_STDBY_Msk (0x1UL << FLASH_OBR_nRST_STDBY_Pos)
- #define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk
- #define FLASH_OBR_nBOOT1_Pos (12U)
- #define FLASH_OBR_nBOOT1_Msk (0x1UL << FLASH_OBR_nBOOT1_Pos)
- #define FLASH_OBR_nBOOT1 FLASH_OBR_nBOOT1_Msk
- #define FLASH_OBR_VDDA_MONITOR_Pos (13U)
- #define FLASH_OBR_VDDA_MONITOR_Msk (0x1UL << FLASH_OBR_VDDA_MONITOR_Pos)
- #define FLASH_OBR_VDDA_MONITOR FLASH_OBR_VDDA_MONITOR_Msk
- #define FLASH_OBR_RAM_PARITY_CHECK_Pos (14U)
- #define FLASH_OBR_RAM_PARITY_CHECK_Msk (0x1UL << FLASH_OBR_RAM_PARITY_CHECK_Pos)
- #define FLASH_OBR_RAM_PARITY_CHECK FLASH_OBR_RAM_PARITY_CHECK_Msk
- #define FLASH_OBR_DATA0_Pos (16U)
- #define FLASH_OBR_DATA0_Msk (0xFFUL << FLASH_OBR_DATA0_Pos)
- #define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk
- #define FLASH_OBR_DATA1_Pos (24U)
- #define FLASH_OBR_DATA1_Msk (0xFFUL << FLASH_OBR_DATA1_Pos)
- #define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk
- #define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
- #define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
- #define FLASH_WRPR_WRP_Pos (0U)
- #define FLASH_WRPR_WRP_Msk (0xFFFFUL << FLASH_WRPR_WRP_Pos)
- #define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk
- #define OB_RDP_RDP_Pos (0U)
- #define OB_RDP_RDP_Msk (0xFFUL << OB_RDP_RDP_Pos)
- #define OB_RDP_RDP OB_RDP_RDP_Msk
- #define OB_RDP_nRDP_Pos (8U)
- #define OB_RDP_nRDP_Msk (0xFFUL << OB_RDP_nRDP_Pos)
- #define OB_RDP_nRDP OB_RDP_nRDP_Msk
- #define OB_USER_USER_Pos (16U)
- #define OB_USER_USER_Msk (0xFFUL << OB_USER_USER_Pos)
- #define OB_USER_USER OB_USER_USER_Msk
- #define OB_USER_nUSER_Pos (24U)
- #define OB_USER_nUSER_Msk (0xFFUL << OB_USER_nUSER_Pos)
- #define OB_USER_nUSER OB_USER_nUSER_Msk
- #define OB_WRP0_WRP0_Pos (0U)
- #define OB_WRP0_WRP0_Msk (0xFFUL << OB_WRP0_WRP0_Pos)
- #define OB_WRP0_WRP0 OB_WRP0_WRP0_Msk
- #define OB_WRP0_nWRP0_Pos (8U)
- #define OB_WRP0_nWRP0_Msk (0xFFUL << OB_WRP0_nWRP0_Pos)
- #define OB_WRP0_nWRP0 OB_WRP0_nWRP0_Msk
- #define GPIO_MODER_MODER0_Pos (0U)
- #define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos)
- #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
- #define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos)
- #define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos)
- #define GPIO_MODER_MODER1_Pos (2U)
- #define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos)
- #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
- #define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos)
- #define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos)
- #define GPIO_MODER_MODER2_Pos (4U)
- #define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos)
- #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
- #define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos)
- #define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos)
- #define GPIO_MODER_MODER3_Pos (6U)
- #define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos)
- #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
- #define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos)
- #define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos)
- #define GPIO_MODER_MODER4_Pos (8U)
- #define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos)
- #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
- #define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos)
- #define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos)
- #define GPIO_MODER_MODER5_Pos (10U)
- #define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos)
- #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
- #define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos)
- #define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos)
- #define GPIO_MODER_MODER6_Pos (12U)
- #define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos)
- #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
- #define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos)
- #define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos)
- #define GPIO_MODER_MODER7_Pos (14U)
- #define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos)
- #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
- #define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos)
- #define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos)
- #define GPIO_MODER_MODER8_Pos (16U)
- #define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos)
- #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
- #define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos)
- #define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos)
- #define GPIO_MODER_MODER9_Pos (18U)
- #define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos)
- #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
- #define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos)
- #define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos)
- #define GPIO_MODER_MODER10_Pos (20U)
- #define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos)
- #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
- #define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos)
- #define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos)
- #define GPIO_MODER_MODER11_Pos (22U)
- #define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos)
- #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
- #define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos)
- #define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos)
- #define GPIO_MODER_MODER12_Pos (24U)
- #define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos)
- #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
- #define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos)
- #define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos)
- #define GPIO_MODER_MODER13_Pos (26U)
- #define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos)
- #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
- #define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos)
- #define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos)
- #define GPIO_MODER_MODER14_Pos (28U)
- #define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos)
- #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
- #define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos)
- #define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos)
- #define GPIO_MODER_MODER15_Pos (30U)
- #define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos)
- #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
- #define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos)
- #define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos)
- #define GPIO_OTYPER_OT_0 (0x00000001U)
- #define GPIO_OTYPER_OT_1 (0x00000002U)
- #define GPIO_OTYPER_OT_2 (0x00000004U)
- #define GPIO_OTYPER_OT_3 (0x00000008U)
- #define GPIO_OTYPER_OT_4 (0x00000010U)
- #define GPIO_OTYPER_OT_5 (0x00000020U)
- #define GPIO_OTYPER_OT_6 (0x00000040U)
- #define GPIO_OTYPER_OT_7 (0x00000080U)
- #define GPIO_OTYPER_OT_8 (0x00000100U)
- #define GPIO_OTYPER_OT_9 (0x00000200U)
- #define GPIO_OTYPER_OT_10 (0x00000400U)
- #define GPIO_OTYPER_OT_11 (0x00000800U)
- #define GPIO_OTYPER_OT_12 (0x00001000U)
- #define GPIO_OTYPER_OT_13 (0x00002000U)
- #define GPIO_OTYPER_OT_14 (0x00004000U)
- #define GPIO_OTYPER_OT_15 (0x00008000U)
- #define GPIO_OSPEEDR_OSPEEDR0_Pos (0U)
- #define GPIO_OSPEEDR_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR0_Pos)
- #define GPIO_OSPEEDR_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0_Msk
- #define GPIO_OSPEEDR_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR0_Pos)
- #define GPIO_OSPEEDR_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR0_Pos)
- #define GPIO_OSPEEDR_OSPEEDR1_Pos (2U)
- #define GPIO_OSPEEDR_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR1_Pos)
- #define GPIO_OSPEEDR_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1_Msk
- #define GPIO_OSPEEDR_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR1_Pos)
- #define GPIO_OSPEEDR_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR1_Pos)
- #define GPIO_OSPEEDR_OSPEEDR2_Pos (4U)
- #define GPIO_OSPEEDR_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR2_Pos)
- #define GPIO_OSPEEDR_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2_Msk
- #define GPIO_OSPEEDR_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR2_Pos)
- #define GPIO_OSPEEDR_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR2_Pos)
- #define GPIO_OSPEEDR_OSPEEDR3_Pos (6U)
- #define GPIO_OSPEEDR_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR3_Pos)
- #define GPIO_OSPEEDR_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3_Msk
- #define GPIO_OSPEEDR_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR3_Pos)
- #define GPIO_OSPEEDR_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR3_Pos)
- #define GPIO_OSPEEDR_OSPEEDR4_Pos (8U)
- #define GPIO_OSPEEDR_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR4_Pos)
- #define GPIO_OSPEEDR_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4_Msk
- #define GPIO_OSPEEDR_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR4_Pos)
- #define GPIO_OSPEEDR_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR4_Pos)
- #define GPIO_OSPEEDR_OSPEEDR5_Pos (10U)
- #define GPIO_OSPEEDR_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR5_Pos)
- #define GPIO_OSPEEDR_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5_Msk
- #define GPIO_OSPEEDR_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR5_Pos)
- #define GPIO_OSPEEDR_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR5_Pos)
- #define GPIO_OSPEEDR_OSPEEDR6_Pos (12U)
- #define GPIO_OSPEEDR_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR6_Pos)
- #define GPIO_OSPEEDR_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6_Msk
- #define GPIO_OSPEEDR_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR6_Pos)
- #define GPIO_OSPEEDR_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR6_Pos)
- #define GPIO_OSPEEDR_OSPEEDR7_Pos (14U)
- #define GPIO_OSPEEDR_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR7_Pos)
- #define GPIO_OSPEEDR_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7_Msk
- #define GPIO_OSPEEDR_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR7_Pos)
- #define GPIO_OSPEEDR_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR7_Pos)
- #define GPIO_OSPEEDR_OSPEEDR8_Pos (16U)
- #define GPIO_OSPEEDR_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR8_Pos)
- #define GPIO_OSPEEDR_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8_Msk
- #define GPIO_OSPEEDR_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR8_Pos)
- #define GPIO_OSPEEDR_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR8_Pos)
- #define GPIO_OSPEEDR_OSPEEDR9_Pos (18U)
- #define GPIO_OSPEEDR_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR9_Pos)
- #define GPIO_OSPEEDR_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9_Msk
- #define GPIO_OSPEEDR_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR9_Pos)
- #define GPIO_OSPEEDR_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR9_Pos)
- #define GPIO_OSPEEDR_OSPEEDR10_Pos (20U)
- #define GPIO_OSPEEDR_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR10_Pos)
- #define GPIO_OSPEEDR_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10_Msk
- #define GPIO_OSPEEDR_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR10_Pos)
- #define GPIO_OSPEEDR_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR10_Pos)
- #define GPIO_OSPEEDR_OSPEEDR11_Pos (22U)
- #define GPIO_OSPEEDR_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR11_Pos)
- #define GPIO_OSPEEDR_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11_Msk
- #define GPIO_OSPEEDR_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR11_Pos)
- #define GPIO_OSPEEDR_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR11_Pos)
- #define GPIO_OSPEEDR_OSPEEDR12_Pos (24U)
- #define GPIO_OSPEEDR_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR12_Pos)
- #define GPIO_OSPEEDR_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12_Msk
- #define GPIO_OSPEEDR_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR12_Pos)
- #define GPIO_OSPEEDR_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR12_Pos)
- #define GPIO_OSPEEDR_OSPEEDR13_Pos (26U)
- #define GPIO_OSPEEDR_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR13_Pos)
- #define GPIO_OSPEEDR_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13_Msk
- #define GPIO_OSPEEDR_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR13_Pos)
- #define GPIO_OSPEEDR_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR13_Pos)
- #define GPIO_OSPEEDR_OSPEEDR14_Pos (28U)
- #define GPIO_OSPEEDR_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR14_Pos)
- #define GPIO_OSPEEDR_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14_Msk
- #define GPIO_OSPEEDR_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR14_Pos)
- #define GPIO_OSPEEDR_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR14_Pos)
- #define GPIO_OSPEEDR_OSPEEDR15_Pos (30U)
- #define GPIO_OSPEEDR_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR15_Pos)
- #define GPIO_OSPEEDR_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15_Msk
- #define GPIO_OSPEEDR_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR15_Pos)
- #define GPIO_OSPEEDR_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR15_Pos)
- #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
- #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
- #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
- #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
- #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
- #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
- #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
- #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
- #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
- #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
- #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
- #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
- #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
- #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
- #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
- #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
- #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
- #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
- #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
- #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
- #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
- #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
- #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
- #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
- #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
- #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
- #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
- #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
- #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
- #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
- #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
- #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
- #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
- #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
- #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
- #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
- #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
- #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
- #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
- #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
- #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
- #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
- #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
- #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
- #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
- #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
- #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
- #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
- #define GPIO_PUPDR_PUPDR0_Pos (0U)
- #define GPIO_PUPDR_PUPDR0_Msk (0x3UL << GPIO_PUPDR_PUPDR0_Pos)
- #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk
- #define GPIO_PUPDR_PUPDR0_0 (0x1UL << GPIO_PUPDR_PUPDR0_Pos)
- #define GPIO_PUPDR_PUPDR0_1 (0x2UL << GPIO_PUPDR_PUPDR0_Pos)
- #define GPIO_PUPDR_PUPDR1_Pos (2U)
- #define GPIO_PUPDR_PUPDR1_Msk (0x3UL << GPIO_PUPDR_PUPDR1_Pos)
- #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk
- #define GPIO_PUPDR_PUPDR1_0 (0x1UL << GPIO_PUPDR_PUPDR1_Pos)
- #define GPIO_PUPDR_PUPDR1_1 (0x2UL << GPIO_PUPDR_PUPDR1_Pos)
- #define GPIO_PUPDR_PUPDR2_Pos (4U)
- #define GPIO_PUPDR_PUPDR2_Msk (0x3UL << GPIO_PUPDR_PUPDR2_Pos)
- #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk
- #define GPIO_PUPDR_PUPDR2_0 (0x1UL << GPIO_PUPDR_PUPDR2_Pos)
- #define GPIO_PUPDR_PUPDR2_1 (0x2UL << GPIO_PUPDR_PUPDR2_Pos)
- #define GPIO_PUPDR_PUPDR3_Pos (6U)
- #define GPIO_PUPDR_PUPDR3_Msk (0x3UL << GPIO_PUPDR_PUPDR3_Pos)
- #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk
- #define GPIO_PUPDR_PUPDR3_0 (0x1UL << GPIO_PUPDR_PUPDR3_Pos)
- #define GPIO_PUPDR_PUPDR3_1 (0x2UL << GPIO_PUPDR_PUPDR3_Pos)
- #define GPIO_PUPDR_PUPDR4_Pos (8U)
- #define GPIO_PUPDR_PUPDR4_Msk (0x3UL << GPIO_PUPDR_PUPDR4_Pos)
- #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk
- #define GPIO_PUPDR_PUPDR4_0 (0x1UL << GPIO_PUPDR_PUPDR4_Pos)
- #define GPIO_PUPDR_PUPDR4_1 (0x2UL << GPIO_PUPDR_PUPDR4_Pos)
- #define GPIO_PUPDR_PUPDR5_Pos (10U)
- #define GPIO_PUPDR_PUPDR5_Msk (0x3UL << GPIO_PUPDR_PUPDR5_Pos)
- #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk
- #define GPIO_PUPDR_PUPDR5_0 (0x1UL << GPIO_PUPDR_PUPDR5_Pos)
- #define GPIO_PUPDR_PUPDR5_1 (0x2UL << GPIO_PUPDR_PUPDR5_Pos)
- #define GPIO_PUPDR_PUPDR6_Pos (12U)
- #define GPIO_PUPDR_PUPDR6_Msk (0x3UL << GPIO_PUPDR_PUPDR6_Pos)
- #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk
- #define GPIO_PUPDR_PUPDR6_0 (0x1UL << GPIO_PUPDR_PUPDR6_Pos)
- #define GPIO_PUPDR_PUPDR6_1 (0x2UL << GPIO_PUPDR_PUPDR6_Pos)
- #define GPIO_PUPDR_PUPDR7_Pos (14U)
- #define GPIO_PUPDR_PUPDR7_Msk (0x3UL << GPIO_PUPDR_PUPDR7_Pos)
- #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk
- #define GPIO_PUPDR_PUPDR7_0 (0x1UL << GPIO_PUPDR_PUPDR7_Pos)
- #define GPIO_PUPDR_PUPDR7_1 (0x2UL << GPIO_PUPDR_PUPDR7_Pos)
- #define GPIO_PUPDR_PUPDR8_Pos (16U)
- #define GPIO_PUPDR_PUPDR8_Msk (0x3UL << GPIO_PUPDR_PUPDR8_Pos)
- #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk
- #define GPIO_PUPDR_PUPDR8_0 (0x1UL << GPIO_PUPDR_PUPDR8_Pos)
- #define GPIO_PUPDR_PUPDR8_1 (0x2UL << GPIO_PUPDR_PUPDR8_Pos)
- #define GPIO_PUPDR_PUPDR9_Pos (18U)
- #define GPIO_PUPDR_PUPDR9_Msk (0x3UL << GPIO_PUPDR_PUPDR9_Pos)
- #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk
- #define GPIO_PUPDR_PUPDR9_0 (0x1UL << GPIO_PUPDR_PUPDR9_Pos)
- #define GPIO_PUPDR_PUPDR9_1 (0x2UL << GPIO_PUPDR_PUPDR9_Pos)
- #define GPIO_PUPDR_PUPDR10_Pos (20U)
- #define GPIO_PUPDR_PUPDR10_Msk (0x3UL << GPIO_PUPDR_PUPDR10_Pos)
- #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk
- #define GPIO_PUPDR_PUPDR10_0 (0x1UL << GPIO_PUPDR_PUPDR10_Pos)
- #define GPIO_PUPDR_PUPDR10_1 (0x2UL << GPIO_PUPDR_PUPDR10_Pos)
- #define GPIO_PUPDR_PUPDR11_Pos (22U)
- #define GPIO_PUPDR_PUPDR11_Msk (0x3UL << GPIO_PUPDR_PUPDR11_Pos)
- #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk
- #define GPIO_PUPDR_PUPDR11_0 (0x1UL << GPIO_PUPDR_PUPDR11_Pos)
- #define GPIO_PUPDR_PUPDR11_1 (0x2UL << GPIO_PUPDR_PUPDR11_Pos)
- #define GPIO_PUPDR_PUPDR12_Pos (24U)
- #define GPIO_PUPDR_PUPDR12_Msk (0x3UL << GPIO_PUPDR_PUPDR12_Pos)
- #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk
- #define GPIO_PUPDR_PUPDR12_0 (0x1UL << GPIO_PUPDR_PUPDR12_Pos)
- #define GPIO_PUPDR_PUPDR12_1 (0x2UL << GPIO_PUPDR_PUPDR12_Pos)
- #define GPIO_PUPDR_PUPDR13_Pos (26U)
- #define GPIO_PUPDR_PUPDR13_Msk (0x3UL << GPIO_PUPDR_PUPDR13_Pos)
- #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk
- #define GPIO_PUPDR_PUPDR13_0 (0x1UL << GPIO_PUPDR_PUPDR13_Pos)
- #define GPIO_PUPDR_PUPDR13_1 (0x2UL << GPIO_PUPDR_PUPDR13_Pos)
- #define GPIO_PUPDR_PUPDR14_Pos (28U)
- #define GPIO_PUPDR_PUPDR14_Msk (0x3UL << GPIO_PUPDR_PUPDR14_Pos)
- #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk
- #define GPIO_PUPDR_PUPDR14_0 (0x1UL << GPIO_PUPDR_PUPDR14_Pos)
- #define GPIO_PUPDR_PUPDR14_1 (0x2UL << GPIO_PUPDR_PUPDR14_Pos)
- #define GPIO_PUPDR_PUPDR15_Pos (30U)
- #define GPIO_PUPDR_PUPDR15_Msk (0x3UL << GPIO_PUPDR_PUPDR15_Pos)
- #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk
- #define GPIO_PUPDR_PUPDR15_0 (0x1UL << GPIO_PUPDR_PUPDR15_Pos)
- #define GPIO_PUPDR_PUPDR15_1 (0x2UL << GPIO_PUPDR_PUPDR15_Pos)
- #define GPIO_IDR_0 (0x00000001U)
- #define GPIO_IDR_1 (0x00000002U)
- #define GPIO_IDR_2 (0x00000004U)
- #define GPIO_IDR_3 (0x00000008U)
- #define GPIO_IDR_4 (0x00000010U)
- #define GPIO_IDR_5 (0x00000020U)
- #define GPIO_IDR_6 (0x00000040U)
- #define GPIO_IDR_7 (0x00000080U)
- #define GPIO_IDR_8 (0x00000100U)
- #define GPIO_IDR_9 (0x00000200U)
- #define GPIO_IDR_10 (0x00000400U)
- #define GPIO_IDR_11 (0x00000800U)
- #define GPIO_IDR_12 (0x00001000U)
- #define GPIO_IDR_13 (0x00002000U)
- #define GPIO_IDR_14 (0x00004000U)
- #define GPIO_IDR_15 (0x00008000U)
- #define GPIO_ODR_0 (0x00000001U)
- #define GPIO_ODR_1 (0x00000002U)
- #define GPIO_ODR_2 (0x00000004U)
- #define GPIO_ODR_3 (0x00000008U)
- #define GPIO_ODR_4 (0x00000010U)
- #define GPIO_ODR_5 (0x00000020U)
- #define GPIO_ODR_6 (0x00000040U)
- #define GPIO_ODR_7 (0x00000080U)
- #define GPIO_ODR_8 (0x00000100U)
- #define GPIO_ODR_9 (0x00000200U)
- #define GPIO_ODR_10 (0x00000400U)
- #define GPIO_ODR_11 (0x00000800U)
- #define GPIO_ODR_12 (0x00001000U)
- #define GPIO_ODR_13 (0x00002000U)
- #define GPIO_ODR_14 (0x00004000U)
- #define GPIO_ODR_15 (0x00008000U)
- #define GPIO_BSRR_BS_0 (0x00000001U)
- #define GPIO_BSRR_BS_1 (0x00000002U)
- #define GPIO_BSRR_BS_2 (0x00000004U)
- #define GPIO_BSRR_BS_3 (0x00000008U)
- #define GPIO_BSRR_BS_4 (0x00000010U)
- #define GPIO_BSRR_BS_5 (0x00000020U)
- #define GPIO_BSRR_BS_6 (0x00000040U)
- #define GPIO_BSRR_BS_7 (0x00000080U)
- #define GPIO_BSRR_BS_8 (0x00000100U)
- #define GPIO_BSRR_BS_9 (0x00000200U)
- #define GPIO_BSRR_BS_10 (0x00000400U)
- #define GPIO_BSRR_BS_11 (0x00000800U)
- #define GPIO_BSRR_BS_12 (0x00001000U)
- #define GPIO_BSRR_BS_13 (0x00002000U)
- #define GPIO_BSRR_BS_14 (0x00004000U)
- #define GPIO_BSRR_BS_15 (0x00008000U)
- #define GPIO_BSRR_BR_0 (0x00010000U)
- #define GPIO_BSRR_BR_1 (0x00020000U)
- #define GPIO_BSRR_BR_2 (0x00040000U)
- #define GPIO_BSRR_BR_3 (0x00080000U)
- #define GPIO_BSRR_BR_4 (0x00100000U)
- #define GPIO_BSRR_BR_5 (0x00200000U)
- #define GPIO_BSRR_BR_6 (0x00400000U)
- #define GPIO_BSRR_BR_7 (0x00800000U)
- #define GPIO_BSRR_BR_8 (0x01000000U)
- #define GPIO_BSRR_BR_9 (0x02000000U)
- #define GPIO_BSRR_BR_10 (0x04000000U)
- #define GPIO_BSRR_BR_11 (0x08000000U)
- #define GPIO_BSRR_BR_12 (0x10000000U)
- #define GPIO_BSRR_BR_13 (0x20000000U)
- #define GPIO_BSRR_BR_14 (0x40000000U)
- #define GPIO_BSRR_BR_15 (0x80000000U)
- #define GPIO_LCKR_LCK0_Pos (0U)
- #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)
- #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
- #define GPIO_LCKR_LCK1_Pos (1U)
- #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)
- #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
- #define GPIO_LCKR_LCK2_Pos (2U)
- #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)
- #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
- #define GPIO_LCKR_LCK3_Pos (3U)
- #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)
- #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
- #define GPIO_LCKR_LCK4_Pos (4U)
- #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)
- #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
- #define GPIO_LCKR_LCK5_Pos (5U)
- #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)
- #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
- #define GPIO_LCKR_LCK6_Pos (6U)
- #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)
- #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
- #define GPIO_LCKR_LCK7_Pos (7U)
- #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)
- #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
- #define GPIO_LCKR_LCK8_Pos (8U)
- #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)
- #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
- #define GPIO_LCKR_LCK9_Pos (9U)
- #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)
- #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
- #define GPIO_LCKR_LCK10_Pos (10U)
- #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)
- #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
- #define GPIO_LCKR_LCK11_Pos (11U)
- #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)
- #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
- #define GPIO_LCKR_LCK12_Pos (12U)
- #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)
- #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
- #define GPIO_LCKR_LCK13_Pos (13U)
- #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)
- #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
- #define GPIO_LCKR_LCK14_Pos (14U)
- #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)
- #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
- #define GPIO_LCKR_LCK15_Pos (15U)
- #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)
- #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
- #define GPIO_LCKR_LCKK_Pos (16U)
- #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)
- #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
- #define GPIO_AFRL_AFSEL0_Pos (0U)
- #define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos)
- #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
- #define GPIO_AFRL_AFSEL1_Pos (4U)
- #define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos)
- #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
- #define GPIO_AFRL_AFSEL2_Pos (8U)
- #define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos)
- #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
- #define GPIO_AFRL_AFSEL3_Pos (12U)
- #define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos)
- #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
- #define GPIO_AFRL_AFSEL4_Pos (16U)
- #define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos)
- #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
- #define GPIO_AFRL_AFSEL5_Pos (20U)
- #define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos)
- #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
- #define GPIO_AFRL_AFSEL6_Pos (24U)
- #define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos)
- #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
- #define GPIO_AFRL_AFSEL7_Pos (28U)
- #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos)
- #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
- #define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos
- #define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk
- #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
- #define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos
- #define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk
- #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
- #define GPIO_AFRL_AFRL2_Pos GPIO_AFRL_AFSEL2_Pos
- #define GPIO_AFRL_AFRL2_Msk GPIO_AFRL_AFSEL2_Msk
- #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
- #define GPIO_AFRL_AFRL3_Pos GPIO_AFRL_AFSEL3_Pos
- #define GPIO_AFRL_AFRL3_Msk GPIO_AFRL_AFSEL3_Msk
- #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
- #define GPIO_AFRL_AFRL4_Pos GPIO_AFRL_AFSEL4_Pos
- #define GPIO_AFRL_AFRL4_Msk GPIO_AFRL_AFSEL4_Msk
- #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
- #define GPIO_AFRL_AFRL5_Pos GPIO_AFRL_AFSEL5_Pos
- #define GPIO_AFRL_AFRL5_Msk GPIO_AFRL_AFSEL5_Msk
- #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
- #define GPIO_AFRL_AFRL6_Pos GPIO_AFRL_AFSEL6_Pos
- #define GPIO_AFRL_AFRL6_Msk GPIO_AFRL_AFSEL6_Msk
- #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
- #define GPIO_AFRL_AFRL7_Pos GPIO_AFRL_AFSEL7_Pos
- #define GPIO_AFRL_AFRL7_Msk GPIO_AFRL_AFSEL7_Msk
- #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
-
- #define GPIO_AFRH_AFSEL8_Pos (0U)
- #define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos)
- #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
- #define GPIO_AFRH_AFSEL9_Pos (4U)
- #define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos)
- #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
- #define GPIO_AFRH_AFSEL10_Pos (8U)
- #define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos)
- #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
- #define GPIO_AFRH_AFSEL11_Pos (12U)
- #define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos)
- #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
- #define GPIO_AFRH_AFSEL12_Pos (16U)
- #define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos)
- #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
- #define GPIO_AFRH_AFSEL13_Pos (20U)
- #define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos)
- #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
- #define GPIO_AFRH_AFSEL14_Pos (24U)
- #define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos)
- #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
- #define GPIO_AFRH_AFSEL15_Pos (28U)
- #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos)
- #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
-
- #define GPIO_AFRH_AFRH0_Pos GPIO_AFRH_AFSEL8_Pos
- #define GPIO_AFRH_AFRH0_Msk GPIO_AFRH_AFSEL8_Msk
- #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
- #define GPIO_AFRH_AFRH1_Pos GPIO_AFRH_AFSEL9_Pos
- #define GPIO_AFRH_AFRH1_Msk GPIO_AFRH_AFSEL9_Msk
- #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
- #define GPIO_AFRH_AFRH2_Pos GPIO_AFRH_AFSEL10_Pos
- #define GPIO_AFRH_AFRH2_Msk GPIO_AFRH_AFSEL10_Msk
- #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
- #define GPIO_AFRH_AFRH3_Pos GPIO_AFRH_AFSEL11_Pos
- #define GPIO_AFRH_AFRH3_Msk GPIO_AFRH_AFSEL11_Msk
- #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
- #define GPIO_AFRH_AFRH4_Pos GPIO_AFRH_AFSEL12_Pos
- #define GPIO_AFRH_AFRH4_Msk GPIO_AFRH_AFSEL12_Msk
- #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
- #define GPIO_AFRH_AFRH5_Pos GPIO_AFRH_AFSEL13_Pos
- #define GPIO_AFRH_AFRH5_Msk GPIO_AFRH_AFSEL13_Msk
- #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
- #define GPIO_AFRH_AFRH6_Pos GPIO_AFRH_AFSEL14_Pos
- #define GPIO_AFRH_AFRH6_Msk GPIO_AFRH_AFSEL14_Msk
- #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
- #define GPIO_AFRH_AFRH7_Pos GPIO_AFRH_AFSEL15_Pos
- #define GPIO_AFRH_AFRH7_Msk GPIO_AFRH_AFSEL15_Msk
- #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
- #define GPIO_BRR_BR_0 (0x00000001U)
- #define GPIO_BRR_BR_1 (0x00000002U)
- #define GPIO_BRR_BR_2 (0x00000004U)
- #define GPIO_BRR_BR_3 (0x00000008U)
- #define GPIO_BRR_BR_4 (0x00000010U)
- #define GPIO_BRR_BR_5 (0x00000020U)
- #define GPIO_BRR_BR_6 (0x00000040U)
- #define GPIO_BRR_BR_7 (0x00000080U)
- #define GPIO_BRR_BR_8 (0x00000100U)
- #define GPIO_BRR_BR_9 (0x00000200U)
- #define GPIO_BRR_BR_10 (0x00000400U)
- #define GPIO_BRR_BR_11 (0x00000800U)
- #define GPIO_BRR_BR_12 (0x00001000U)
- #define GPIO_BRR_BR_13 (0x00002000U)
- #define GPIO_BRR_BR_14 (0x00004000U)
- #define GPIO_BRR_BR_15 (0x00008000U)
- #define I2C_CR1_PE_Pos (0U)
- #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)
- #define I2C_CR1_PE I2C_CR1_PE_Msk
- #define I2C_CR1_TXIE_Pos (1U)
- #define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos)
- #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk
- #define I2C_CR1_RXIE_Pos (2U)
- #define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos)
- #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk
- #define I2C_CR1_ADDRIE_Pos (3U)
- #define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos)
- #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk
- #define I2C_CR1_NACKIE_Pos (4U)
- #define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos)
- #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk
- #define I2C_CR1_STOPIE_Pos (5U)
- #define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos)
- #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk
- #define I2C_CR1_TCIE_Pos (6U)
- #define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos)
- #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk
- #define I2C_CR1_ERRIE_Pos (7U)
- #define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos)
- #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk
- #define I2C_CR1_DNF_Pos (8U)
- #define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos)
- #define I2C_CR1_DNF I2C_CR1_DNF_Msk
- #define I2C_CR1_ANFOFF_Pos (12U)
- #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos)
- #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk
- #define I2C_CR1_SWRST_Pos (13U)
- #define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos)
- #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk
- #define I2C_CR1_TXDMAEN_Pos (14U)
- #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos)
- #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk
- #define I2C_CR1_RXDMAEN_Pos (15U)
- #define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos)
- #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk
- #define I2C_CR1_SBC_Pos (16U)
- #define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos)
- #define I2C_CR1_SBC I2C_CR1_SBC_Msk
- #define I2C_CR1_NOSTRETCH_Pos (17U)
- #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)
- #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk
- #define I2C_CR1_GCEN_Pos (19U)
- #define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos)
- #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk
- #define I2C_CR1_SMBHEN_Pos (20U)
- #define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos)
- #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk
- #define I2C_CR1_SMBDEN_Pos (21U)
- #define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos)
- #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk
- #define I2C_CR1_ALERTEN_Pos (22U)
- #define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos)
- #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk
- #define I2C_CR1_PECEN_Pos (23U)
- #define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos)
- #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk
- #define I2C_CR2_SADD_Pos (0U)
- #define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos)
- #define I2C_CR2_SADD I2C_CR2_SADD_Msk
- #define I2C_CR2_RD_WRN_Pos (10U)
- #define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos)
- #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk
- #define I2C_CR2_ADD10_Pos (11U)
- #define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos)
- #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk
- #define I2C_CR2_HEAD10R_Pos (12U)
- #define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos)
- #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk
- #define I2C_CR2_START_Pos (13U)
- #define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos)
- #define I2C_CR2_START I2C_CR2_START_Msk
- #define I2C_CR2_STOP_Pos (14U)
- #define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos)
- #define I2C_CR2_STOP I2C_CR2_STOP_Msk
- #define I2C_CR2_NACK_Pos (15U)
- #define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos)
- #define I2C_CR2_NACK I2C_CR2_NACK_Msk
- #define I2C_CR2_NBYTES_Pos (16U)
- #define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos)
- #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk
- #define I2C_CR2_RELOAD_Pos (24U)
- #define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos)
- #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk
- #define I2C_CR2_AUTOEND_Pos (25U)
- #define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos)
- #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk
- #define I2C_CR2_PECBYTE_Pos (26U)
- #define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos)
- #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk
- #define I2C_OAR1_OA1_Pos (0U)
- #define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos)
- #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk
- #define I2C_OAR1_OA1MODE_Pos (10U)
- #define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos)
- #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk
- #define I2C_OAR1_OA1EN_Pos (15U)
- #define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos)
- #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk
- #define I2C_OAR2_OA2_Pos (1U)
- #define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos)
- #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk
- #define I2C_OAR2_OA2MSK_Pos (8U)
- #define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos)
- #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk
- #define I2C_OAR2_OA2NOMASK (0x00000000U)
- #define I2C_OAR2_OA2MASK01_Pos (8U)
- #define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos)
- #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk
- #define I2C_OAR2_OA2MASK02_Pos (9U)
- #define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos)
- #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk
- #define I2C_OAR2_OA2MASK03_Pos (8U)
- #define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos)
- #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk
- #define I2C_OAR2_OA2MASK04_Pos (10U)
- #define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos)
- #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk
- #define I2C_OAR2_OA2MASK05_Pos (8U)
- #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos)
- #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk
- #define I2C_OAR2_OA2MASK06_Pos (9U)
- #define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos)
- #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk
- #define I2C_OAR2_OA2MASK07_Pos (8U)
- #define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos)
- #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk
- #define I2C_OAR2_OA2EN_Pos (15U)
- #define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos)
- #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk
- #define I2C_TIMINGR_SCLL_Pos (0U)
- #define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos)
- #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk
- #define I2C_TIMINGR_SCLH_Pos (8U)
- #define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos)
- #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk
- #define I2C_TIMINGR_SDADEL_Pos (16U)
- #define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos)
- #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk
- #define I2C_TIMINGR_SCLDEL_Pos (20U)
- #define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos)
- #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk
- #define I2C_TIMINGR_PRESC_Pos (28U)
- #define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos)
- #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk
- #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
- #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)
- #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk
- #define I2C_TIMEOUTR_TIDLE_Pos (12U)
- #define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)
- #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk
- #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
- #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)
- #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk
- #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
- #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)
- #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk
- #define I2C_TIMEOUTR_TEXTEN_Pos (31U)
- #define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)
- #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk
- #define I2C_ISR_TXE_Pos (0U)
- #define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos)
- #define I2C_ISR_TXE I2C_ISR_TXE_Msk
- #define I2C_ISR_TXIS_Pos (1U)
- #define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos)
- #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk
- #define I2C_ISR_RXNE_Pos (2U)
- #define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos)
- #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk
- #define I2C_ISR_ADDR_Pos (3U)
- #define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos)
- #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk
- #define I2C_ISR_NACKF_Pos (4U)
- #define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos)
- #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk
- #define I2C_ISR_STOPF_Pos (5U)
- #define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos)
- #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk
- #define I2C_ISR_TC_Pos (6U)
- #define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos)
- #define I2C_ISR_TC I2C_ISR_TC_Msk
- #define I2C_ISR_TCR_Pos (7U)
- #define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos)
- #define I2C_ISR_TCR I2C_ISR_TCR_Msk
- #define I2C_ISR_BERR_Pos (8U)
- #define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos)
- #define I2C_ISR_BERR I2C_ISR_BERR_Msk
- #define I2C_ISR_ARLO_Pos (9U)
- #define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos)
- #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk
- #define I2C_ISR_OVR_Pos (10U)
- #define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos)
- #define I2C_ISR_OVR I2C_ISR_OVR_Msk
- #define I2C_ISR_PECERR_Pos (11U)
- #define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos)
- #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk
- #define I2C_ISR_TIMEOUT_Pos (12U)
- #define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos)
- #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk
- #define I2C_ISR_ALERT_Pos (13U)
- #define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos)
- #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk
- #define I2C_ISR_BUSY_Pos (15U)
- #define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos)
- #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk
- #define I2C_ISR_DIR_Pos (16U)
- #define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos)
- #define I2C_ISR_DIR I2C_ISR_DIR_Msk
- #define I2C_ISR_ADDCODE_Pos (17U)
- #define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos)
- #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk
- #define I2C_ICR_ADDRCF_Pos (3U)
- #define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos)
- #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk
- #define I2C_ICR_NACKCF_Pos (4U)
- #define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos)
- #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk
- #define I2C_ICR_STOPCF_Pos (5U)
- #define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos)
- #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk
- #define I2C_ICR_BERRCF_Pos (8U)
- #define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos)
- #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk
- #define I2C_ICR_ARLOCF_Pos (9U)
- #define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos)
- #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk
- #define I2C_ICR_OVRCF_Pos (10U)
- #define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos)
- #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk
- #define I2C_ICR_PECCF_Pos (11U)
- #define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos)
- #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk
- #define I2C_ICR_TIMOUTCF_Pos (12U)
- #define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos)
- #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk
- #define I2C_ICR_ALERTCF_Pos (13U)
- #define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos)
- #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk
- #define I2C_PECR_PEC_Pos (0U)
- #define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos)
- #define I2C_PECR_PEC I2C_PECR_PEC_Msk
- #define I2C_RXDR_RXDATA_Pos (0U)
- #define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos)
- #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk
- #define I2C_TXDR_TXDATA_Pos (0U)
- #define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos)
- #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk
- #define IWDG_KR_KEY_Pos (0U)
- #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)
- #define IWDG_KR_KEY IWDG_KR_KEY_Msk
- #define IWDG_PR_PR_Pos (0U)
- #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)
- #define IWDG_PR_PR IWDG_PR_PR_Msk
- #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)
- #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)
- #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)
- #define IWDG_RLR_RL_Pos (0U)
- #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)
- #define IWDG_RLR_RL IWDG_RLR_RL_Msk
- #define IWDG_SR_PVU_Pos (0U)
- #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)
- #define IWDG_SR_PVU IWDG_SR_PVU_Msk
- #define IWDG_SR_RVU_Pos (1U)
- #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)
- #define IWDG_SR_RVU IWDG_SR_RVU_Msk
- #define IWDG_SR_WVU_Pos (2U)
- #define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos)
- #define IWDG_SR_WVU IWDG_SR_WVU_Msk
- #define IWDG_WINR_WIN_Pos (0U)
- #define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos)
- #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk
- #define PWR_CR_LPDS_Pos (0U)
- #define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos)
- #define PWR_CR_LPDS PWR_CR_LPDS_Msk
- #define PWR_CR_PDDS_Pos (1U)
- #define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos)
- #define PWR_CR_PDDS PWR_CR_PDDS_Msk
- #define PWR_CR_CWUF_Pos (2U)
- #define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos)
- #define PWR_CR_CWUF PWR_CR_CWUF_Msk
- #define PWR_CR_CSBF_Pos (3U)
- #define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos)
- #define PWR_CR_CSBF PWR_CR_CSBF_Msk
- #define PWR_CR_DBP_Pos (8U)
- #define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos)
- #define PWR_CR_DBP PWR_CR_DBP_Msk
- #define PWR_CSR_WUF_Pos (0U)
- #define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos)
- #define PWR_CSR_WUF PWR_CSR_WUF_Msk
- #define PWR_CSR_SBF_Pos (1U)
- #define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos)
- #define PWR_CSR_SBF PWR_CSR_SBF_Msk
- #define PWR_CSR_EWUP1_Pos (8U)
- #define PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos)
- #define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk
- #define PWR_CSR_EWUP2_Pos (9U)
- #define PWR_CSR_EWUP2_Msk (0x1UL << PWR_CSR_EWUP2_Pos)
- #define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk
- #define RCC_CR_HSION_Pos (0U)
- #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)
- #define RCC_CR_HSION RCC_CR_HSION_Msk
- #define RCC_CR_HSIRDY_Pos (1U)
- #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)
- #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
- #define RCC_CR_HSITRIM_Pos (3U)
- #define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos)
- #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
- #define RCC_CR_HSITRIM_0 (0x01UL << RCC_CR_HSITRIM_Pos)
- #define RCC_CR_HSITRIM_1 (0x02UL << RCC_CR_HSITRIM_Pos)
- #define RCC_CR_HSITRIM_2 (0x04UL << RCC_CR_HSITRIM_Pos)
- #define RCC_CR_HSITRIM_3 (0x08UL << RCC_CR_HSITRIM_Pos)
- #define RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos)
- #define RCC_CR_HSICAL_Pos (8U)
- #define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos)
- #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
- #define RCC_CR_HSICAL_0 (0x01UL << RCC_CR_HSICAL_Pos)
- #define RCC_CR_HSICAL_1 (0x02UL << RCC_CR_HSICAL_Pos)
- #define RCC_CR_HSICAL_2 (0x04UL << RCC_CR_HSICAL_Pos)
- #define RCC_CR_HSICAL_3 (0x08UL << RCC_CR_HSICAL_Pos)
- #define RCC_CR_HSICAL_4 (0x10UL << RCC_CR_HSICAL_Pos)
- #define RCC_CR_HSICAL_5 (0x20UL << RCC_CR_HSICAL_Pos)
- #define RCC_CR_HSICAL_6 (0x40UL << RCC_CR_HSICAL_Pos)
- #define RCC_CR_HSICAL_7 (0x80UL << RCC_CR_HSICAL_Pos)
- #define RCC_CR_HSEON_Pos (16U)
- #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)
- #define RCC_CR_HSEON RCC_CR_HSEON_Msk
- #define RCC_CR_HSERDY_Pos (17U)
- #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)
- #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
- #define RCC_CR_HSEBYP_Pos (18U)
- #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)
- #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
- #define RCC_CR_CSSON_Pos (19U)
- #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos)
- #define RCC_CR_CSSON RCC_CR_CSSON_Msk
- #define RCC_CR_PLLON_Pos (24U)
- #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)
- #define RCC_CR_PLLON RCC_CR_PLLON_Msk
- #define RCC_CR_PLLRDY_Pos (25U)
- #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)
- #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
- #define RCC_CFGR_SW_Pos (0U)
- #define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)
- #define RCC_CFGR_SW RCC_CFGR_SW_Msk
- #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)
- #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)
- #define RCC_CFGR_SW_HSI (0x00000000U)
- #define RCC_CFGR_SW_HSE (0x00000001U)
- #define RCC_CFGR_SW_PLL (0x00000002U)
- #define RCC_CFGR_SWS_Pos (2U)
- #define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)
- #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk
- #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)
- #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)
- #define RCC_CFGR_SWS_HSI (0x00000000U)
- #define RCC_CFGR_SWS_HSE (0x00000004U)
- #define RCC_CFGR_SWS_PLL (0x00000008U)
- #define RCC_CFGR_HPRE_Pos (4U)
- #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)
- #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk
- #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)
- #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)
- #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)
- #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)
- #define RCC_CFGR_HPRE_DIV1 (0x00000000U)
- #define RCC_CFGR_HPRE_DIV2 (0x00000080U)
- #define RCC_CFGR_HPRE_DIV4 (0x00000090U)
- #define RCC_CFGR_HPRE_DIV8 (0x000000A0U)
- #define RCC_CFGR_HPRE_DIV16 (0x000000B0U)
- #define RCC_CFGR_HPRE_DIV64 (0x000000C0U)
- #define RCC_CFGR_HPRE_DIV128 (0x000000D0U)
- #define RCC_CFGR_HPRE_DIV256 (0x000000E0U)
- #define RCC_CFGR_HPRE_DIV512 (0x000000F0U)
- #define RCC_CFGR_PPRE_Pos (8U)
- #define RCC_CFGR_PPRE_Msk (0x7UL << RCC_CFGR_PPRE_Pos)
- #define RCC_CFGR_PPRE RCC_CFGR_PPRE_Msk
- #define RCC_CFGR_PPRE_0 (0x1UL << RCC_CFGR_PPRE_Pos)
- #define RCC_CFGR_PPRE_1 (0x2UL << RCC_CFGR_PPRE_Pos)
- #define RCC_CFGR_PPRE_2 (0x4UL << RCC_CFGR_PPRE_Pos)
- #define RCC_CFGR_PPRE_DIV1 (0x00000000U)
- #define RCC_CFGR_PPRE_DIV2_Pos (10U)
- #define RCC_CFGR_PPRE_DIV2_Msk (0x1UL << RCC_CFGR_PPRE_DIV2_Pos)
- #define RCC_CFGR_PPRE_DIV2 RCC_CFGR_PPRE_DIV2_Msk
- #define RCC_CFGR_PPRE_DIV4_Pos (8U)
- #define RCC_CFGR_PPRE_DIV4_Msk (0x5UL << RCC_CFGR_PPRE_DIV4_Pos)
- #define RCC_CFGR_PPRE_DIV4 RCC_CFGR_PPRE_DIV4_Msk
- #define RCC_CFGR_PPRE_DIV8_Pos (9U)
- #define RCC_CFGR_PPRE_DIV8_Msk (0x3UL << RCC_CFGR_PPRE_DIV8_Pos)
- #define RCC_CFGR_PPRE_DIV8 RCC_CFGR_PPRE_DIV8_Msk
- #define RCC_CFGR_PPRE_DIV16_Pos (8U)
- #define RCC_CFGR_PPRE_DIV16_Msk (0x7UL << RCC_CFGR_PPRE_DIV16_Pos)
- #define RCC_CFGR_PPRE_DIV16 RCC_CFGR_PPRE_DIV16_Msk
- #define RCC_CFGR_ADCPRE_Pos (14U)
- #define RCC_CFGR_ADCPRE_Msk (0x1UL << RCC_CFGR_ADCPRE_Pos)
- #define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk
- #define RCC_CFGR_ADCPRE_DIV2 (0x00000000U)
- #define RCC_CFGR_ADCPRE_DIV4 (0x00004000U)
- #define RCC_CFGR_PLLSRC_Pos (16U)
- #define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos)
- #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk
- #define RCC_CFGR_PLLSRC_HSI_DIV2 (0x00000000U)
- #define RCC_CFGR_PLLSRC_HSE_PREDIV (0x00010000U)
- #define RCC_CFGR_PLLXTPRE_Pos (17U)
- #define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos)
- #define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk
- #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 (0x00000000U)
- #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 (0x00020000U)
- #define RCC_CFGR_PLLMUL_Pos (18U)
- #define RCC_CFGR_PLLMUL_Msk (0xFUL << RCC_CFGR_PLLMUL_Pos)
- #define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk
- #define RCC_CFGR_PLLMUL_0 (0x1UL << RCC_CFGR_PLLMUL_Pos)
- #define RCC_CFGR_PLLMUL_1 (0x2UL << RCC_CFGR_PLLMUL_Pos)
- #define RCC_CFGR_PLLMUL_2 (0x4UL << RCC_CFGR_PLLMUL_Pos)
- #define RCC_CFGR_PLLMUL_3 (0x8UL << RCC_CFGR_PLLMUL_Pos)
- #define RCC_CFGR_PLLMUL2 (0x00000000U)
- #define RCC_CFGR_PLLMUL3 (0x00040000U)
- #define RCC_CFGR_PLLMUL4 (0x00080000U)
- #define RCC_CFGR_PLLMUL5 (0x000C0000U)
- #define RCC_CFGR_PLLMUL6 (0x00100000U)
- #define RCC_CFGR_PLLMUL7 (0x00140000U)
- #define RCC_CFGR_PLLMUL8 (0x00180000U)
- #define RCC_CFGR_PLLMUL9 (0x001C0000U)
- #define RCC_CFGR_PLLMUL10 (0x00200000U)
- #define RCC_CFGR_PLLMUL11 (0x00240000U)
- #define RCC_CFGR_PLLMUL12 (0x00280000U)
- #define RCC_CFGR_PLLMUL13 (0x002C0000U)
- #define RCC_CFGR_PLLMUL14 (0x00300000U)
- #define RCC_CFGR_PLLMUL15 (0x00340000U)
- #define RCC_CFGR_PLLMUL16 (0x00380000U)
- #define RCC_CFGR_MCO_Pos (24U)
- #define RCC_CFGR_MCO_Msk (0xFUL << RCC_CFGR_MCO_Pos)
- #define RCC_CFGR_MCO RCC_CFGR_MCO_Msk
- #define RCC_CFGR_MCO_0 (0x1UL << RCC_CFGR_MCO_Pos)
- #define RCC_CFGR_MCO_1 (0x2UL << RCC_CFGR_MCO_Pos)
- #define RCC_CFGR_MCO_2 (0x4UL << RCC_CFGR_MCO_Pos)
- #define RCC_CFGR_MCO_NOCLOCK (0x00000000U)
- #define RCC_CFGR_MCO_HSI14 (0x01000000U)
- #define RCC_CFGR_MCO_LSI (0x02000000U)
- #define RCC_CFGR_MCO_LSE (0x03000000U)
- #define RCC_CFGR_MCO_SYSCLK (0x04000000U)
- #define RCC_CFGR_MCO_HSI (0x05000000U)
- #define RCC_CFGR_MCO_HSE (0x06000000U)
- #define RCC_CFGR_MCO_PLL (0x07000000U)
- #define RCC_CFGR_MCOPRE_Pos (28U)
- #define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos)
- #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk
- #define RCC_CFGR_MCOPRE_DIV1 (0x00000000U)
- #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U)
- #define RCC_CFGR_MCOPRE_DIV4 (0x20000000U)
- #define RCC_CFGR_MCOPRE_DIV8 (0x30000000U)
- #define RCC_CFGR_MCOPRE_DIV16 (0x40000000U)
- #define RCC_CFGR_MCOPRE_DIV32 (0x50000000U)
- #define RCC_CFGR_MCOPRE_DIV64 (0x60000000U)
- #define RCC_CFGR_MCOPRE_DIV128 (0x70000000U)
- #define RCC_CFGR_PLLNODIV_Pos (31U)
- #define RCC_CFGR_PLLNODIV_Msk (0x1UL << RCC_CFGR_PLLNODIV_Pos)
- #define RCC_CFGR_PLLNODIV RCC_CFGR_PLLNODIV_Msk
- #define RCC_CFGR_MCOSEL RCC_CFGR_MCO
- #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
- #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
- #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
- #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
- #define RCC_CFGR_MCOSEL_HSI14 RCC_CFGR_MCO_HSI14
- #define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCO_LSI
- #define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCO_LSE
- #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
- #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
- #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
- #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL
- #define RCC_CIR_LSIRDYF_Pos (0U)
- #define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos)
- #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
- #define RCC_CIR_LSERDYF_Pos (1U)
- #define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos)
- #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
- #define RCC_CIR_HSIRDYF_Pos (2U)
- #define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos)
- #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
- #define RCC_CIR_HSERDYF_Pos (3U)
- #define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos)
- #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
- #define RCC_CIR_PLLRDYF_Pos (4U)
- #define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos)
- #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
- #define RCC_CIR_HSI14RDYF_Pos (5U)
- #define RCC_CIR_HSI14RDYF_Msk (0x1UL << RCC_CIR_HSI14RDYF_Pos)
- #define RCC_CIR_HSI14RDYF RCC_CIR_HSI14RDYF_Msk
- #define RCC_CIR_CSSF_Pos (7U)
- #define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos)
- #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
- #define RCC_CIR_LSIRDYIE_Pos (8U)
- #define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos)
- #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
- #define RCC_CIR_LSERDYIE_Pos (9U)
- #define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos)
- #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
- #define RCC_CIR_HSIRDYIE_Pos (10U)
- #define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos)
- #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
- #define RCC_CIR_HSERDYIE_Pos (11U)
- #define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos)
- #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
- #define RCC_CIR_PLLRDYIE_Pos (12U)
- #define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos)
- #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
- #define RCC_CIR_HSI14RDYIE_Pos (13U)
- #define RCC_CIR_HSI14RDYIE_Msk (0x1UL << RCC_CIR_HSI14RDYIE_Pos)
- #define RCC_CIR_HSI14RDYIE RCC_CIR_HSI14RDYIE_Msk
- #define RCC_CIR_LSIRDYC_Pos (16U)
- #define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos)
- #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
- #define RCC_CIR_LSERDYC_Pos (17U)
- #define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos)
- #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
- #define RCC_CIR_HSIRDYC_Pos (18U)
- #define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos)
- #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
- #define RCC_CIR_HSERDYC_Pos (19U)
- #define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos)
- #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
- #define RCC_CIR_PLLRDYC_Pos (20U)
- #define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos)
- #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
- #define RCC_CIR_HSI14RDYC_Pos (21U)
- #define RCC_CIR_HSI14RDYC_Msk (0x1UL << RCC_CIR_HSI14RDYC_Pos)
- #define RCC_CIR_HSI14RDYC RCC_CIR_HSI14RDYC_Msk
- #define RCC_CIR_CSSC_Pos (23U)
- #define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos)
- #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
- #define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
- #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)
- #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
- #define RCC_APB2RSTR_ADCRST_Pos (9U)
- #define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos)
- #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
- #define RCC_APB2RSTR_TIM1RST_Pos (11U)
- #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)
- #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
- #define RCC_APB2RSTR_SPI1RST_Pos (12U)
- #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)
- #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
- #define RCC_APB2RSTR_USART1RST_Pos (14U)
- #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)
- #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
- #define RCC_APB2RSTR_TIM16RST_Pos (17U)
- #define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)
- #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
- #define RCC_APB2RSTR_TIM17RST_Pos (18U)
- #define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)
- #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk
- #define RCC_APB2RSTR_DBGMCURST_Pos (22U)
- #define RCC_APB2RSTR_DBGMCURST_Msk (0x1UL << RCC_APB2RSTR_DBGMCURST_Pos)
- #define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk
- #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
- #define RCC_APB1RSTR_TIM3RST_Pos (1U)
- #define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)
- #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
- #define RCC_APB1RSTR_TIM14RST_Pos (8U)
- #define RCC_APB1RSTR_TIM14RST_Msk (0x1UL << RCC_APB1RSTR_TIM14RST_Pos)
- #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
- #define RCC_APB1RSTR_WWDGRST_Pos (11U)
- #define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)
- #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
- #define RCC_APB1RSTR_I2C1RST_Pos (21U)
- #define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)
- #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
- #define RCC_APB1RSTR_PWRRST_Pos (28U)
- #define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos)
- #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
- #define RCC_AHBENR_DMAEN_Pos (0U)
- #define RCC_AHBENR_DMAEN_Msk (0x1UL << RCC_AHBENR_DMAEN_Pos)
- #define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk
- #define RCC_AHBENR_SRAMEN_Pos (2U)
- #define RCC_AHBENR_SRAMEN_Msk (0x1UL << RCC_AHBENR_SRAMEN_Pos)
- #define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk
- #define RCC_AHBENR_FLITFEN_Pos (4U)
- #define RCC_AHBENR_FLITFEN_Msk (0x1UL << RCC_AHBENR_FLITFEN_Pos)
- #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk
- #define RCC_AHBENR_CRCEN_Pos (6U)
- #define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos)
- #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk
- #define RCC_AHBENR_GPIOAEN_Pos (17U)
- #define RCC_AHBENR_GPIOAEN_Msk (0x1UL << RCC_AHBENR_GPIOAEN_Pos)
- #define RCC_AHBENR_GPIOAEN RCC_AHBENR_GPIOAEN_Msk
- #define RCC_AHBENR_GPIOBEN_Pos (18U)
- #define RCC_AHBENR_GPIOBEN_Msk (0x1UL << RCC_AHBENR_GPIOBEN_Pos)
- #define RCC_AHBENR_GPIOBEN RCC_AHBENR_GPIOBEN_Msk
- #define RCC_AHBENR_GPIOCEN_Pos (19U)
- #define RCC_AHBENR_GPIOCEN_Msk (0x1UL << RCC_AHBENR_GPIOCEN_Pos)
- #define RCC_AHBENR_GPIOCEN RCC_AHBENR_GPIOCEN_Msk
- #define RCC_AHBENR_GPIODEN_Pos (20U)
- #define RCC_AHBENR_GPIODEN_Msk (0x1UL << RCC_AHBENR_GPIODEN_Pos)
- #define RCC_AHBENR_GPIODEN RCC_AHBENR_GPIODEN_Msk
- #define RCC_AHBENR_GPIOFEN_Pos (22U)
- #define RCC_AHBENR_GPIOFEN_Msk (0x1UL << RCC_AHBENR_GPIOFEN_Pos)
- #define RCC_AHBENR_GPIOFEN RCC_AHBENR_GPIOFEN_Msk
- #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN
- #define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN
- #define RCC_APB2ENR_SYSCFGCOMPEN_Pos (0U)
- #define RCC_APB2ENR_SYSCFGCOMPEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGCOMPEN_Pos)
- #define RCC_APB2ENR_SYSCFGCOMPEN RCC_APB2ENR_SYSCFGCOMPEN_Msk
- #define RCC_APB2ENR_ADCEN_Pos (9U)
- #define RCC_APB2ENR_ADCEN_Msk (0x1UL << RCC_APB2ENR_ADCEN_Pos)
- #define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk
- #define RCC_APB2ENR_TIM1EN_Pos (11U)
- #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)
- #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
- #define RCC_APB2ENR_SPI1EN_Pos (12U)
- #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)
- #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
- #define RCC_APB2ENR_USART1EN_Pos (14U)
- #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)
- #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
- #define RCC_APB2ENR_TIM16EN_Pos (17U)
- #define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos)
- #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
- #define RCC_APB2ENR_TIM17EN_Pos (18U)
- #define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos)
- #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk
- #define RCC_APB2ENR_DBGMCUEN_Pos (22U)
- #define RCC_APB2ENR_DBGMCUEN_Msk (0x1UL << RCC_APB2ENR_DBGMCUEN_Pos)
- #define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGMCUEN_Msk
- #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN
- #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN
- #define RCC_APB1ENR_TIM3EN_Pos (1U)
- #define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos)
- #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
- #define RCC_APB1ENR_TIM14EN_Pos (8U)
- #define RCC_APB1ENR_TIM14EN_Msk (0x1UL << RCC_APB1ENR_TIM14EN_Pos)
- #define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
- #define RCC_APB1ENR_WWDGEN_Pos (11U)
- #define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos)
- #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
- #define RCC_APB1ENR_I2C1EN_Pos (21U)
- #define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos)
- #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
- #define RCC_APB1ENR_PWREN_Pos (28U)
- #define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos)
- #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
- #define RCC_BDCR_LSEON_Pos (0U)
- #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)
- #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
- #define RCC_BDCR_LSERDY_Pos (1U)
- #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)
- #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
- #define RCC_BDCR_LSEBYP_Pos (2U)
- #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)
- #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
- #define RCC_BDCR_LSEDRV_Pos (3U)
- #define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos)
- #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
- #define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos)
- #define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos)
- #define RCC_BDCR_RTCSEL_Pos (8U)
- #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)
- #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
- #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)
- #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)
- #define RCC_BDCR_RTCSEL_NOCLOCK (0x00000000U)
- #define RCC_BDCR_RTCSEL_LSE (0x00000100U)
- #define RCC_BDCR_RTCSEL_LSI (0x00000200U)
- #define RCC_BDCR_RTCSEL_HSE (0x00000300U)
- #define RCC_BDCR_RTCEN_Pos (15U)
- #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)
- #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
- #define RCC_BDCR_BDRST_Pos (16U)
- #define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)
- #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
- #define RCC_CSR_LSION_Pos (0U)
- #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)
- #define RCC_CSR_LSION RCC_CSR_LSION_Msk
- #define RCC_CSR_LSIRDY_Pos (1U)
- #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)
- #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
- #define RCC_CSR_V18PWRRSTF_Pos (23U)
- #define RCC_CSR_V18PWRRSTF_Msk (0x1UL << RCC_CSR_V18PWRRSTF_Pos)
- #define RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF_Msk
- #define RCC_CSR_RMVF_Pos (24U)
- #define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos)
- #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
- #define RCC_CSR_OBLRSTF_Pos (25U)
- #define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos)
- #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk
- #define RCC_CSR_PINRSTF_Pos (26U)
- #define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos)
- #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
- #define RCC_CSR_PORRSTF_Pos (27U)
- #define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos)
- #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
- #define RCC_CSR_SFTRSTF_Pos (28U)
- #define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos)
- #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
- #define RCC_CSR_IWDGRSTF_Pos (29U)
- #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos)
- #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
- #define RCC_CSR_WWDGRSTF_Pos (30U)
- #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos)
- #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
- #define RCC_CSR_LPWRRSTF_Pos (31U)
- #define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos)
- #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
- #define RCC_CSR_OBL RCC_CSR_OBLRSTF
- #define RCC_AHBRSTR_GPIOARST_Pos (17U)
- #define RCC_AHBRSTR_GPIOARST_Msk (0x1UL << RCC_AHBRSTR_GPIOARST_Pos)
- #define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk
- #define RCC_AHBRSTR_GPIOBRST_Pos (18U)
- #define RCC_AHBRSTR_GPIOBRST_Msk (0x1UL << RCC_AHBRSTR_GPIOBRST_Pos)
- #define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk
- #define RCC_AHBRSTR_GPIOCRST_Pos (19U)
- #define RCC_AHBRSTR_GPIOCRST_Msk (0x1UL << RCC_AHBRSTR_GPIOCRST_Pos)
- #define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk
- #define RCC_AHBRSTR_GPIODRST_Pos (20U)
- #define RCC_AHBRSTR_GPIODRST_Msk (0x1UL << RCC_AHBRSTR_GPIODRST_Pos)
- #define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk
- #define RCC_AHBRSTR_GPIOFRST_Pos (22U)
- #define RCC_AHBRSTR_GPIOFRST_Msk (0x1UL << RCC_AHBRSTR_GPIOFRST_Pos)
- #define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk
- #define RCC_CFGR2_PREDIV_Pos (0U)
- #define RCC_CFGR2_PREDIV_Msk (0xFUL << RCC_CFGR2_PREDIV_Pos)
- #define RCC_CFGR2_PREDIV RCC_CFGR2_PREDIV_Msk
- #define RCC_CFGR2_PREDIV_0 (0x1UL << RCC_CFGR2_PREDIV_Pos)
- #define RCC_CFGR2_PREDIV_1 (0x2UL << RCC_CFGR2_PREDIV_Pos)
- #define RCC_CFGR2_PREDIV_2 (0x4UL << RCC_CFGR2_PREDIV_Pos)
- #define RCC_CFGR2_PREDIV_3 (0x8UL << RCC_CFGR2_PREDIV_Pos)
- #define RCC_CFGR2_PREDIV_DIV1 (0x00000000U)
- #define RCC_CFGR2_PREDIV_DIV2 (0x00000001U)
- #define RCC_CFGR2_PREDIV_DIV3 (0x00000002U)
- #define RCC_CFGR2_PREDIV_DIV4 (0x00000003U)
- #define RCC_CFGR2_PREDIV_DIV5 (0x00000004U)
- #define RCC_CFGR2_PREDIV_DIV6 (0x00000005U)
- #define RCC_CFGR2_PREDIV_DIV7 (0x00000006U)
- #define RCC_CFGR2_PREDIV_DIV8 (0x00000007U)
- #define RCC_CFGR2_PREDIV_DIV9 (0x00000008U)
- #define RCC_CFGR2_PREDIV_DIV10 (0x00000009U)
- #define RCC_CFGR2_PREDIV_DIV11 (0x0000000AU)
- #define RCC_CFGR2_PREDIV_DIV12 (0x0000000BU)
- #define RCC_CFGR2_PREDIV_DIV13 (0x0000000CU)
- #define RCC_CFGR2_PREDIV_DIV14 (0x0000000DU)
- #define RCC_CFGR2_PREDIV_DIV15 (0x0000000EU)
- #define RCC_CFGR2_PREDIV_DIV16 (0x0000000FU)
- #define RCC_CFGR3_USART1SW_Pos (0U)
- #define RCC_CFGR3_USART1SW_Msk (0x3UL << RCC_CFGR3_USART1SW_Pos)
- #define RCC_CFGR3_USART1SW RCC_CFGR3_USART1SW_Msk
- #define RCC_CFGR3_USART1SW_0 (0x1UL << RCC_CFGR3_USART1SW_Pos)
- #define RCC_CFGR3_USART1SW_1 (0x2UL << RCC_CFGR3_USART1SW_Pos)
- #define RCC_CFGR3_USART1SW_PCLK (0x00000000U)
- #define RCC_CFGR3_USART1SW_SYSCLK (0x00000001U)
- #define RCC_CFGR3_USART1SW_LSE (0x00000002U)
- #define RCC_CFGR3_USART1SW_HSI (0x00000003U)
- #define RCC_CFGR3_I2C1SW_Pos (4U)
- #define RCC_CFGR3_I2C1SW_Msk (0x1UL << RCC_CFGR3_I2C1SW_Pos)
- #define RCC_CFGR3_I2C1SW RCC_CFGR3_I2C1SW_Msk
- #define RCC_CFGR3_I2C1SW_HSI (0x00000000U)
- #define RCC_CFGR3_I2C1SW_SYSCLK_Pos (4U)
- #define RCC_CFGR3_I2C1SW_SYSCLK_Msk (0x1UL << RCC_CFGR3_I2C1SW_SYSCLK_Pos)
- #define RCC_CFGR3_I2C1SW_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK_Msk
- #define RCC_CR2_HSI14ON_Pos (0U)
- #define RCC_CR2_HSI14ON_Msk (0x1UL << RCC_CR2_HSI14ON_Pos)
- #define RCC_CR2_HSI14ON RCC_CR2_HSI14ON_Msk
- #define RCC_CR2_HSI14RDY_Pos (1U)
- #define RCC_CR2_HSI14RDY_Msk (0x1UL << RCC_CR2_HSI14RDY_Pos)
- #define RCC_CR2_HSI14RDY RCC_CR2_HSI14RDY_Msk
- #define RCC_CR2_HSI14DIS_Pos (2U)
- #define RCC_CR2_HSI14DIS_Msk (0x1UL << RCC_CR2_HSI14DIS_Pos)
- #define RCC_CR2_HSI14DIS RCC_CR2_HSI14DIS_Msk
- #define RCC_CR2_HSI14TRIM_Pos (3U)
- #define RCC_CR2_HSI14TRIM_Msk (0x1FUL << RCC_CR2_HSI14TRIM_Pos)
- #define RCC_CR2_HSI14TRIM RCC_CR2_HSI14TRIM_Msk
- #define RCC_CR2_HSI14CAL_Pos (8U)
- #define RCC_CR2_HSI14CAL_Msk (0xFFUL << RCC_CR2_HSI14CAL_Pos)
- #define RCC_CR2_HSI14CAL RCC_CR2_HSI14CAL_Msk
- #define RTC_TAMPER1_SUPPORT
- #define RTC_TAMPER2_SUPPORT
- #define RTC_TR_PM_Pos (22U)
- #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)
- #define RTC_TR_PM RTC_TR_PM_Msk
- #define RTC_TR_HT_Pos (20U)
- #define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)
- #define RTC_TR_HT RTC_TR_HT_Msk
- #define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)
- #define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)
- #define RTC_TR_HU_Pos (16U)
- #define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)
- #define RTC_TR_HU RTC_TR_HU_Msk
- #define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)
- #define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)
- #define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)
- #define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)
- #define RTC_TR_MNT_Pos (12U)
- #define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)
- #define RTC_TR_MNT RTC_TR_MNT_Msk
- #define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)
- #define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)
- #define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)
- #define RTC_TR_MNU_Pos (8U)
- #define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)
- #define RTC_TR_MNU RTC_TR_MNU_Msk
- #define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)
- #define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)
- #define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)
- #define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)
- #define RTC_TR_ST_Pos (4U)
- #define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)
- #define RTC_TR_ST RTC_TR_ST_Msk
- #define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)
- #define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)
- #define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)
- #define RTC_TR_SU_Pos (0U)
- #define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)
- #define RTC_TR_SU RTC_TR_SU_Msk
- #define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)
- #define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)
- #define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)
- #define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)
- #define RTC_DR_YT_Pos (20U)
- #define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)
- #define RTC_DR_YT RTC_DR_YT_Msk
- #define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)
- #define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)
- #define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)
- #define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)
- #define RTC_DR_YU_Pos (16U)
- #define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)
- #define RTC_DR_YU RTC_DR_YU_Msk
- #define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)
- #define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)
- #define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)
- #define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)
- #define RTC_DR_WDU_Pos (13U)
- #define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)
- #define RTC_DR_WDU RTC_DR_WDU_Msk
- #define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)
- #define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)
- #define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)
- #define RTC_DR_MT_Pos (12U)
- #define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)
- #define RTC_DR_MT RTC_DR_MT_Msk
- #define RTC_DR_MU_Pos (8U)
- #define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)
- #define RTC_DR_MU RTC_DR_MU_Msk
- #define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)
- #define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)
- #define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)
- #define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)
- #define RTC_DR_DT_Pos (4U)
- #define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)
- #define RTC_DR_DT RTC_DR_DT_Msk
- #define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)
- #define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)
- #define RTC_DR_DU_Pos (0U)
- #define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)
- #define RTC_DR_DU RTC_DR_DU_Msk
- #define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)
- #define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)
- #define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)
- #define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)
- #define RTC_CR_COE_Pos (23U)
- #define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)
- #define RTC_CR_COE RTC_CR_COE_Msk
- #define RTC_CR_OSEL_Pos (21U)
- #define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)
- #define RTC_CR_OSEL RTC_CR_OSEL_Msk
- #define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)
- #define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)
- #define RTC_CR_POL_Pos (20U)
- #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)
- #define RTC_CR_POL RTC_CR_POL_Msk
- #define RTC_CR_COSEL_Pos (19U)
- #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos)
- #define RTC_CR_COSEL RTC_CR_COSEL_Msk
- #define RTC_CR_BKP_Pos (18U)
- #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)
- #define RTC_CR_BKP RTC_CR_BKP_Msk
- #define RTC_CR_SUB1H_Pos (17U)
- #define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)
- #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
- #define RTC_CR_ADD1H_Pos (16U)
- #define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)
- #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
- #define RTC_CR_TSIE_Pos (15U)
- #define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)
- #define RTC_CR_TSIE RTC_CR_TSIE_Msk
- #define RTC_CR_ALRAIE_Pos (12U)
- #define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)
- #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
- #define RTC_CR_TSE_Pos (11U)
- #define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)
- #define RTC_CR_TSE RTC_CR_TSE_Msk
- #define RTC_CR_ALRAE_Pos (8U)
- #define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)
- #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
- #define RTC_CR_FMT_Pos (6U)
- #define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)
- #define RTC_CR_FMT RTC_CR_FMT_Msk
- #define RTC_CR_BYPSHAD_Pos (5U)
- #define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos)
- #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
- #define RTC_CR_REFCKON_Pos (4U)
- #define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)
- #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
- #define RTC_CR_TSEDGE_Pos (3U)
- #define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)
- #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
- #define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
- #define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
- #define RTC_CR_BCK RTC_CR_BKP
- #define RTC_ISR_RECALPF_Pos (16U)
- #define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos)
- #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
- #define RTC_ISR_TAMP2F_Pos (14U)
- #define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos)
- #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
- #define RTC_ISR_TAMP1F_Pos (13U)
- #define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos)
- #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
- #define RTC_ISR_TSOVF_Pos (12U)
- #define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos)
- #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
- #define RTC_ISR_TSF_Pos (11U)
- #define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos)
- #define RTC_ISR_TSF RTC_ISR_TSF_Msk
- #define RTC_ISR_ALRAF_Pos (8U)
- #define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos)
- #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
- #define RTC_ISR_INIT_Pos (7U)
- #define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos)
- #define RTC_ISR_INIT RTC_ISR_INIT_Msk
- #define RTC_ISR_INITF_Pos (6U)
- #define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos)
- #define RTC_ISR_INITF RTC_ISR_INITF_Msk
- #define RTC_ISR_RSF_Pos (5U)
- #define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos)
- #define RTC_ISR_RSF RTC_ISR_RSF_Msk
- #define RTC_ISR_INITS_Pos (4U)
- #define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos)
- #define RTC_ISR_INITS RTC_ISR_INITS_Msk
- #define RTC_ISR_SHPF_Pos (3U)
- #define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos)
- #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
- #define RTC_ISR_ALRAWF_Pos (0U)
- #define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos)
- #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
- #define RTC_PRER_PREDIV_A_Pos (16U)
- #define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)
- #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
- #define RTC_PRER_PREDIV_S_Pos (0U)
- #define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)
- #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
- #define RTC_ALRMAR_MSK4_Pos (31U)
- #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)
- #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
- #define RTC_ALRMAR_WDSEL_Pos (30U)
- #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)
- #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
- #define RTC_ALRMAR_DT_Pos (28U)
- #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)
- #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
- #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)
- #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)
- #define RTC_ALRMAR_DU_Pos (24U)
- #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)
- #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
- #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)
- #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)
- #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)
- #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)
- #define RTC_ALRMAR_MSK3_Pos (23U)
- #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)
- #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
- #define RTC_ALRMAR_PM_Pos (22U)
- #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos)
- #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
- #define RTC_ALRMAR_HT_Pos (20U)
- #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)
- #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
- #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)
- #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)
- #define RTC_ALRMAR_HU_Pos (16U)
- #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)
- #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
- #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)
- #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)
- #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)
- #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)
- #define RTC_ALRMAR_MSK2_Pos (15U)
- #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)
- #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
- #define RTC_ALRMAR_MNT_Pos (12U)
- #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)
- #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
- #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)
- #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)
- #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)
- #define RTC_ALRMAR_MNU_Pos (8U)
- #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)
- #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
- #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)
- #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)
- #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)
- #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)
- #define RTC_ALRMAR_MSK1_Pos (7U)
- #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)
- #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
- #define RTC_ALRMAR_ST_Pos (4U)
- #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)
- #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
- #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)
- #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)
- #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)
- #define RTC_ALRMAR_SU_Pos (0U)
- #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)
- #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
- #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)
- #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)
- #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)
- #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)
- #define RTC_WPR_KEY_Pos (0U)
- #define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)
- #define RTC_WPR_KEY RTC_WPR_KEY_Msk
- #define RTC_SSR_SS_Pos (0U)
- #define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos)
- #define RTC_SSR_SS RTC_SSR_SS_Msk
- #define RTC_SHIFTR_SUBFS_Pos (0U)
- #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)
- #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
- #define RTC_SHIFTR_ADD1S_Pos (31U)
- #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos)
- #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
- #define RTC_TSTR_PM_Pos (22U)
- #define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)
- #define RTC_TSTR_PM RTC_TSTR_PM_Msk
- #define RTC_TSTR_HT_Pos (20U)
- #define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)
- #define RTC_TSTR_HT RTC_TSTR_HT_Msk
- #define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)
- #define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)
- #define RTC_TSTR_HU_Pos (16U)
- #define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)
- #define RTC_TSTR_HU RTC_TSTR_HU_Msk
- #define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)
- #define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)
- #define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)
- #define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)
- #define RTC_TSTR_MNT_Pos (12U)
- #define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)
- #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
- #define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)
- #define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)
- #define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)
- #define RTC_TSTR_MNU_Pos (8U)
- #define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)
- #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
- #define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)
- #define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)
- #define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)
- #define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)
- #define RTC_TSTR_ST_Pos (4U)
- #define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)
- #define RTC_TSTR_ST RTC_TSTR_ST_Msk
- #define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)
- #define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)
- #define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)
- #define RTC_TSTR_SU_Pos (0U)
- #define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)
- #define RTC_TSTR_SU RTC_TSTR_SU_Msk
- #define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)
- #define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)
- #define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)
- #define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)
- #define RTC_TSDR_WDU_Pos (13U)
- #define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)
- #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
- #define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)
- #define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)
- #define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)
- #define RTC_TSDR_MT_Pos (12U)
- #define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)
- #define RTC_TSDR_MT RTC_TSDR_MT_Msk
- #define RTC_TSDR_MU_Pos (8U)
- #define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)
- #define RTC_TSDR_MU RTC_TSDR_MU_Msk
- #define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)
- #define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)
- #define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)
- #define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)
- #define RTC_TSDR_DT_Pos (4U)
- #define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)
- #define RTC_TSDR_DT RTC_TSDR_DT_Msk
- #define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)
- #define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)
- #define RTC_TSDR_DU_Pos (0U)
- #define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)
- #define RTC_TSDR_DU RTC_TSDR_DU_Msk
- #define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)
- #define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)
- #define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)
- #define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)
- #define RTC_TSSSR_SS_Pos (0U)
- #define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos)
- #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
- #define RTC_CALR_CALP_Pos (15U)
- #define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos)
- #define RTC_CALR_CALP RTC_CALR_CALP_Msk
- #define RTC_CALR_CALW8_Pos (14U)
- #define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos)
- #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
- #define RTC_CALR_CALW16_Pos (13U)
- #define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos)
- #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
- #define RTC_CALR_CALM_Pos (0U)
- #define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos)
- #define RTC_CALR_CALM RTC_CALR_CALM_Msk
- #define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos)
- #define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos)
- #define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos)
- #define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos)
- #define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos)
- #define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos)
- #define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos)
- #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos)
- #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos)
- #define RTC_TAFCR_PC15MODE_Pos (23U)
- #define RTC_TAFCR_PC15MODE_Msk (0x1UL << RTC_TAFCR_PC15MODE_Pos)
- #define RTC_TAFCR_PC15MODE RTC_TAFCR_PC15MODE_Msk
- #define RTC_TAFCR_PC15VALUE_Pos (22U)
- #define RTC_TAFCR_PC15VALUE_Msk (0x1UL << RTC_TAFCR_PC15VALUE_Pos)
- #define RTC_TAFCR_PC15VALUE RTC_TAFCR_PC15VALUE_Msk
- #define RTC_TAFCR_PC14MODE_Pos (21U)
- #define RTC_TAFCR_PC14MODE_Msk (0x1UL << RTC_TAFCR_PC14MODE_Pos)
- #define RTC_TAFCR_PC14MODE RTC_TAFCR_PC14MODE_Msk
- #define RTC_TAFCR_PC14VALUE_Pos (20U)
- #define RTC_TAFCR_PC14VALUE_Msk (0x1UL << RTC_TAFCR_PC14VALUE_Pos)
- #define RTC_TAFCR_PC14VALUE RTC_TAFCR_PC14VALUE_Msk
- #define RTC_TAFCR_PC13MODE_Pos (19U)
- #define RTC_TAFCR_PC13MODE_Msk (0x1UL << RTC_TAFCR_PC13MODE_Pos)
- #define RTC_TAFCR_PC13MODE RTC_TAFCR_PC13MODE_Msk
- #define RTC_TAFCR_PC13VALUE_Pos (18U)
- #define RTC_TAFCR_PC13VALUE_Msk (0x1UL << RTC_TAFCR_PC13VALUE_Pos)
- #define RTC_TAFCR_PC13VALUE RTC_TAFCR_PC13VALUE_Msk
- #define RTC_TAFCR_TAMPPUDIS_Pos (15U)
- #define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)
- #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
- #define RTC_TAFCR_TAMPPRCH_Pos (13U)
- #define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)
- #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
- #define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)
- #define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)
- #define RTC_TAFCR_TAMPFLT_Pos (11U)
- #define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos)
- #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
- #define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos)
- #define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos)
- #define RTC_TAFCR_TAMPFREQ_Pos (8U)
- #define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)
- #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
- #define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)
- #define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)
- #define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)
- #define RTC_TAFCR_TAMPTS_Pos (7U)
- #define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos)
- #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
- #define RTC_TAFCR_TAMP2TRG_Pos (4U)
- #define RTC_TAFCR_TAMP2TRG_Msk (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)
- #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
- #define RTC_TAFCR_TAMP2E_Pos (3U)
- #define RTC_TAFCR_TAMP2E_Msk (0x1UL << RTC_TAFCR_TAMP2E_Pos)
- #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
- #define RTC_TAFCR_TAMPIE_Pos (2U)
- #define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos)
- #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
- #define RTC_TAFCR_TAMP1TRG_Pos (1U)
- #define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)
- #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
- #define RTC_TAFCR_TAMP1E_Pos (0U)
- #define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos)
- #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
- #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_PC13VALUE
- #define RTC_ALRMASSR_MASKSS_Pos (24U)
- #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos)
- #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
- #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos)
- #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos)
- #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos)
- #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos)
- #define RTC_ALRMASSR_SS_Pos (0U)
- #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos)
- #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
- #define SPI_CR1_CPHA_Pos (0U)
- #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos)
- #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk
- #define SPI_CR1_CPOL_Pos (1U)
- #define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos)
- #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk
- #define SPI_CR1_MSTR_Pos (2U)
- #define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos)
- #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk
- #define SPI_CR1_BR_Pos (3U)
- #define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos)
- #define SPI_CR1_BR SPI_CR1_BR_Msk
- #define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos)
- #define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos)
- #define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos)
- #define SPI_CR1_SPE_Pos (6U)
- #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)
- #define SPI_CR1_SPE SPI_CR1_SPE_Msk
- #define SPI_CR1_LSBFIRST_Pos (7U)
- #define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos)
- #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk
- #define SPI_CR1_SSI_Pos (8U)
- #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)
- #define SPI_CR1_SSI SPI_CR1_SSI_Msk
- #define SPI_CR1_SSM_Pos (9U)
- #define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos)
- #define SPI_CR1_SSM SPI_CR1_SSM_Msk
- #define SPI_CR1_RXONLY_Pos (10U)
- #define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos)
- #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk
- #define SPI_CR1_CRCL_Pos (11U)
- #define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos)
- #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk
- #define SPI_CR1_CRCNEXT_Pos (12U)
- #define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos)
- #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk
- #define SPI_CR1_CRCEN_Pos (13U)
- #define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos)
- #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk
- #define SPI_CR1_BIDIOE_Pos (14U)
- #define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos)
- #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk
- #define SPI_CR1_BIDIMODE_Pos (15U)
- #define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos)
- #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk
- #define SPI_CR2_RXDMAEN_Pos (0U)
- #define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos)
- #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk
- #define SPI_CR2_TXDMAEN_Pos (1U)
- #define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos)
- #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk
- #define SPI_CR2_SSOE_Pos (2U)
- #define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos)
- #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk
- #define SPI_CR2_NSSP_Pos (3U)
- #define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos)
- #define SPI_CR2_NSSP SPI_CR2_NSSP_Msk
- #define SPI_CR2_FRF_Pos (4U)
- #define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos)
- #define SPI_CR2_FRF SPI_CR2_FRF_Msk
- #define SPI_CR2_ERRIE_Pos (5U)
- #define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos)
- #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk
- #define SPI_CR2_RXNEIE_Pos (6U)
- #define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos)
- #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk
- #define SPI_CR2_TXEIE_Pos (7U)
- #define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos)
- #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk
- #define SPI_CR2_DS_Pos (8U)
- #define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos)
- #define SPI_CR2_DS SPI_CR2_DS_Msk
- #define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos)
- #define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos)
- #define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos)
- #define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos)
- #define SPI_CR2_FRXTH_Pos (12U)
- #define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos)
- #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk
- #define SPI_CR2_LDMARX_Pos (13U)
- #define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos)
- #define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk
- #define SPI_CR2_LDMATX_Pos (14U)
- #define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos)
- #define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk
- #define SPI_SR_RXNE_Pos (0U)
- #define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos)
- #define SPI_SR_RXNE SPI_SR_RXNE_Msk
- #define SPI_SR_TXE_Pos (1U)
- #define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos)
- #define SPI_SR_TXE SPI_SR_TXE_Msk
- #define SPI_SR_CRCERR_Pos (4U)
- #define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos)
- #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk
- #define SPI_SR_MODF_Pos (5U)
- #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)
- #define SPI_SR_MODF SPI_SR_MODF_Msk
- #define SPI_SR_OVR_Pos (6U)
- #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)
- #define SPI_SR_OVR SPI_SR_OVR_Msk
- #define SPI_SR_BSY_Pos (7U)
- #define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos)
- #define SPI_SR_BSY SPI_SR_BSY_Msk
- #define SPI_SR_FRE_Pos (8U)
- #define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos)
- #define SPI_SR_FRE SPI_SR_FRE_Msk
- #define SPI_SR_FRLVL_Pos (9U)
- #define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos)
- #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk
- #define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos)
- #define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos)
- #define SPI_SR_FTLVL_Pos (11U)
- #define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos)
- #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk
- #define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos)
- #define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos)
- #define SPI_DR_DR_Pos (0U)
- #define SPI_DR_DR_Msk (0xFFFFFFFFUL << SPI_DR_DR_Pos)
- #define SPI_DR_DR SPI_DR_DR_Msk
- #define SPI_CRCPR_CRCPOLY_Pos (0U)
- #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFFFFFUL << SPI_CRCPR_CRCPOLY_Pos)
- #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk
- #define SPI_RXCRCR_RXCRC_Pos (0U)
- #define SPI_RXCRCR_RXCRC_Msk (0xFFFFFFFFUL << SPI_RXCRCR_RXCRC_Pos)
- #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk
- #define SPI_TXCRCR_TXCRC_Pos (0U)
- #define SPI_TXCRCR_TXCRC_Msk (0xFFFFFFFFUL << SPI_TXCRCR_TXCRC_Pos)
- #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk
- #define SPI_I2SCFGR_I2SMOD_Pos (11U)
- #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)
- #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk
- #define SYSCFG_CFGR1_MEM_MODE_Pos (0U)
- #define SYSCFG_CFGR1_MEM_MODE_Msk (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos)
- #define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk
- #define SYSCFG_CFGR1_MEM_MODE_0 (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos)
- #define SYSCFG_CFGR1_MEM_MODE_1 (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos)
- #define SYSCFG_CFGR1_DMA_RMP_Pos (8U)
- #define SYSCFG_CFGR1_DMA_RMP_Msk (0x1FUL << SYSCFG_CFGR1_DMA_RMP_Pos)
- #define SYSCFG_CFGR1_DMA_RMP SYSCFG_CFGR1_DMA_RMP_Msk
- #define SYSCFG_CFGR1_ADC_DMA_RMP_Pos (8U)
- #define SYSCFG_CFGR1_ADC_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_ADC_DMA_RMP_Pos)
- #define SYSCFG_CFGR1_ADC_DMA_RMP SYSCFG_CFGR1_ADC_DMA_RMP_Msk
- #define SYSCFG_CFGR1_USART1TX_DMA_RMP_Pos (9U)
- #define SYSCFG_CFGR1_USART1TX_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_USART1TX_DMA_RMP_Pos)
- #define SYSCFG_CFGR1_USART1TX_DMA_RMP SYSCFG_CFGR1_USART1TX_DMA_RMP_Msk
- #define SYSCFG_CFGR1_USART1RX_DMA_RMP_Pos (10U)
- #define SYSCFG_CFGR1_USART1RX_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_USART1RX_DMA_RMP_Pos)
- #define SYSCFG_CFGR1_USART1RX_DMA_RMP SYSCFG_CFGR1_USART1RX_DMA_RMP_Msk
- #define SYSCFG_CFGR1_TIM16_DMA_RMP_Pos (11U)
- #define SYSCFG_CFGR1_TIM16_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_TIM16_DMA_RMP_Pos)
- #define SYSCFG_CFGR1_TIM16_DMA_RMP SYSCFG_CFGR1_TIM16_DMA_RMP_Msk
- #define SYSCFG_CFGR1_TIM17_DMA_RMP_Pos (12U)
- #define SYSCFG_CFGR1_TIM17_DMA_RMP_Msk (0x1UL << SYSCFG_CFGR1_TIM17_DMA_RMP_Pos)
- #define SYSCFG_CFGR1_TIM17_DMA_RMP SYSCFG_CFGR1_TIM17_DMA_RMP_Msk
- #define SYSCFG_CFGR1_I2C_FMP_PB6_Pos (16U)
- #define SYSCFG_CFGR1_I2C_FMP_PB6_Msk (0x1UL << SYSCFG_CFGR1_I2C_FMP_PB6_Pos)
- #define SYSCFG_CFGR1_I2C_FMP_PB6 SYSCFG_CFGR1_I2C_FMP_PB6_Msk
- #define SYSCFG_CFGR1_I2C_FMP_PB7_Pos (17U)
- #define SYSCFG_CFGR1_I2C_FMP_PB7_Msk (0x1UL << SYSCFG_CFGR1_I2C_FMP_PB7_Pos)
- #define SYSCFG_CFGR1_I2C_FMP_PB7 SYSCFG_CFGR1_I2C_FMP_PB7_Msk
- #define SYSCFG_CFGR1_I2C_FMP_PB8_Pos (18U)
- #define SYSCFG_CFGR1_I2C_FMP_PB8_Msk (0x1UL << SYSCFG_CFGR1_I2C_FMP_PB8_Pos)
- #define SYSCFG_CFGR1_I2C_FMP_PB8 SYSCFG_CFGR1_I2C_FMP_PB8_Msk
- #define SYSCFG_CFGR1_I2C_FMP_PB9_Pos (19U)
- #define SYSCFG_CFGR1_I2C_FMP_PB9_Msk (0x1UL << SYSCFG_CFGR1_I2C_FMP_PB9_Pos)
- #define SYSCFG_CFGR1_I2C_FMP_PB9 SYSCFG_CFGR1_I2C_FMP_PB9_Msk
- #define SYSCFG_CFGR1_I2C_FMP_I2C1_Pos (20U)
- #define SYSCFG_CFGR1_I2C_FMP_I2C1_Msk (0x1UL << SYSCFG_CFGR1_I2C_FMP_I2C1_Pos)
- #define SYSCFG_CFGR1_I2C_FMP_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1_Msk
- #define SYSCFG_CFGR1_I2C_FMP_PA9_Pos (22U)
- #define SYSCFG_CFGR1_I2C_FMP_PA9_Msk (0x1UL << SYSCFG_CFGR1_I2C_FMP_PA9_Pos)
- #define SYSCFG_CFGR1_I2C_FMP_PA9 SYSCFG_CFGR1_I2C_FMP_PA9_Msk
- #define SYSCFG_CFGR1_I2C_FMP_PA10_Pos (23U)
- #define SYSCFG_CFGR1_I2C_FMP_PA10_Msk (0x1UL << SYSCFG_CFGR1_I2C_FMP_PA10_Pos)
- #define SYSCFG_CFGR1_I2C_FMP_PA10 SYSCFG_CFGR1_I2C_FMP_PA10_Msk
- #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
- #define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)
- #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk
- #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
- #define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)
- #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk
- #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
- #define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)
- #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk
- #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
- #define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)
- #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk
- #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U)
- #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U)
- #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U)
- #define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U)
- #define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U)
-
- #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U)
- #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U)
- #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U)
- #define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U)
- #define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U)
- #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U)
- #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U)
- #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U)
- #define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U)
- #define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U)
- #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U)
- #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U)
- #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U)
- #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U)
- #define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U)
- #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
- #define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)
- #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk
- #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
- #define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)
- #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk
- #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
- #define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)
- #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk
- #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
- #define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)
- #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk
- #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U)
- #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U)
- #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U)
- #define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U)
- #define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U)
- #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U)
- #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U)
- #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U)
- #define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U)
- #define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U)
- #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U)
- #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U)
- #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U)
- #define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U)
- #define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U)
- #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U)
- #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U)
- #define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U)
- #define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U)
- #define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U)
- #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
- #define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)
- #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk
- #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
- #define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)
- #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk
- #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
- #define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)
- #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk
- #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
- #define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)
- #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk
- #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U)
- #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U)
- #define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U)
- #define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U)
- #define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U)
- #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U)
- #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U)
- #define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U)
- #define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U)
- #define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U)
- #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U)
- #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U)
- #define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U)
- #define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U)
- #define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U)
- #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U)
- #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U)
- #define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U)
- #define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U)
- #define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U)
- #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
- #define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)
- #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk
- #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
- #define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)
- #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk
- #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
- #define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)
- #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk
- #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
- #define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)
- #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk
- #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U)
- #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U)
- #define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U)
- #define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U)
- #define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U)
- #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U)
- #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U)
- #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U)
- #define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U)
- #define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U)
- #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U)
- #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U)
- #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U)
- #define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U)
- #define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U)
- #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U)
- #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U)
- #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U)
- #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U)
- #define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U)
- #define SYSCFG_CFGR2_LOCKUP_LOCK_Pos (0U)
- #define SYSCFG_CFGR2_LOCKUP_LOCK_Msk (0x1UL << SYSCFG_CFGR2_LOCKUP_LOCK_Pos)
- #define SYSCFG_CFGR2_LOCKUP_LOCK SYSCFG_CFGR2_LOCKUP_LOCK_Msk
- #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos (1U)
- #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk (0x1UL << SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos)
- #define SYSCFG_CFGR2_SRAM_PARITY_LOCK SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk
- #define SYSCFG_CFGR2_SRAM_PEF_Pos (8U)
- #define SYSCFG_CFGR2_SRAM_PEF_Msk (0x1UL << SYSCFG_CFGR2_SRAM_PEF_Pos)
- #define SYSCFG_CFGR2_SRAM_PEF SYSCFG_CFGR2_SRAM_PEF_Msk
- #define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF
- #define TIM_CR1_CEN_Pos (0U)
- #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)
- #define TIM_CR1_CEN TIM_CR1_CEN_Msk
- #define TIM_CR1_UDIS_Pos (1U)
- #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)
- #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk
- #define TIM_CR1_URS_Pos (2U)
- #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)
- #define TIM_CR1_URS TIM_CR1_URS_Msk
- #define TIM_CR1_OPM_Pos (3U)
- #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)
- #define TIM_CR1_OPM TIM_CR1_OPM_Msk
- #define TIM_CR1_DIR_Pos (4U)
- #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)
- #define TIM_CR1_DIR TIM_CR1_DIR_Msk
- #define TIM_CR1_CMS_Pos (5U)
- #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)
- #define TIM_CR1_CMS TIM_CR1_CMS_Msk
- #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)
- #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)
- #define TIM_CR1_ARPE_Pos (7U)
- #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)
- #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk
- #define TIM_CR1_CKD_Pos (8U)
- #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)
- #define TIM_CR1_CKD TIM_CR1_CKD_Msk
- #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)
- #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)
- #define TIM_CR2_CCPC_Pos (0U)
- #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)
- #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk
- #define TIM_CR2_CCUS_Pos (2U)
- #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)
- #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk
- #define TIM_CR2_CCDS_Pos (3U)
- #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)
- #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk
- #define TIM_CR2_MMS_Pos (4U)
- #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)
- #define TIM_CR2_MMS TIM_CR2_MMS_Msk
- #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)
- #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)
- #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)
- #define TIM_CR2_TI1S_Pos (7U)
- #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)
- #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk
- #define TIM_CR2_OIS1_Pos (8U)
- #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)
- #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk
- #define TIM_CR2_OIS1N_Pos (9U)
- #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)
- #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk
- #define TIM_CR2_OIS2_Pos (10U)
- #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)
- #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk
- #define TIM_CR2_OIS2N_Pos (11U)
- #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)
- #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk
- #define TIM_CR2_OIS3_Pos (12U)
- #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)
- #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk
- #define TIM_CR2_OIS3N_Pos (13U)
- #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)
- #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk
- #define TIM_CR2_OIS4_Pos (14U)
- #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)
- #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk
- #define TIM_SMCR_SMS_Pos (0U)
- #define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos)
- #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk
- #define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos)
- #define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos)
- #define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos)
- #define TIM_SMCR_OCCS_Pos (3U)
- #define TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos)
- #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk
- #define TIM_SMCR_TS_Pos (4U)
- #define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos)
- #define TIM_SMCR_TS TIM_SMCR_TS_Msk
- #define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos)
- #define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos)
- #define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos)
- #define TIM_SMCR_MSM_Pos (7U)
- #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)
- #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk
- #define TIM_SMCR_ETF_Pos (8U)
- #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)
- #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk
- #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)
- #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)
- #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)
- #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)
- #define TIM_SMCR_ETPS_Pos (12U)
- #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)
- #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk
- #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)
- #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)
- #define TIM_SMCR_ECE_Pos (14U)
- #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)
- #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk
- #define TIM_SMCR_ETP_Pos (15U)
- #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)
- #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk
- #define TIM_DIER_UIE_Pos (0U)
- #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)
- #define TIM_DIER_UIE TIM_DIER_UIE_Msk
- #define TIM_DIER_CC1IE_Pos (1U)
- #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)
- #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk
- #define TIM_DIER_CC2IE_Pos (2U)
- #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)
- #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk
- #define TIM_DIER_CC3IE_Pos (3U)
- #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)
- #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk
- #define TIM_DIER_CC4IE_Pos (4U)
- #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)
- #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk
- #define TIM_DIER_COMIE_Pos (5U)
- #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)
- #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk
- #define TIM_DIER_TIE_Pos (6U)
- #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)
- #define TIM_DIER_TIE TIM_DIER_TIE_Msk
- #define TIM_DIER_BIE_Pos (7U)
- #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)
- #define TIM_DIER_BIE TIM_DIER_BIE_Msk
- #define TIM_DIER_UDE_Pos (8U)
- #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)
- #define TIM_DIER_UDE TIM_DIER_UDE_Msk
- #define TIM_DIER_CC1DE_Pos (9U)
- #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)
- #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk
- #define TIM_DIER_CC2DE_Pos (10U)
- #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)
- #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk
- #define TIM_DIER_CC3DE_Pos (11U)
- #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)
- #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk
- #define TIM_DIER_CC4DE_Pos (12U)
- #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)
- #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk
- #define TIM_DIER_COMDE_Pos (13U)
- #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)
- #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk
- #define TIM_DIER_TDE_Pos (14U)
- #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)
- #define TIM_DIER_TDE TIM_DIER_TDE_Msk
- #define TIM_SR_UIF_Pos (0U)
- #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)
- #define TIM_SR_UIF TIM_SR_UIF_Msk
- #define TIM_SR_CC1IF_Pos (1U)
- #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)
- #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk
- #define TIM_SR_CC2IF_Pos (2U)
- #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)
- #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk
- #define TIM_SR_CC3IF_Pos (3U)
- #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)
- #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk
- #define TIM_SR_CC4IF_Pos (4U)
- #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)
- #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk
- #define TIM_SR_COMIF_Pos (5U)
- #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)
- #define TIM_SR_COMIF TIM_SR_COMIF_Msk
- #define TIM_SR_TIF_Pos (6U)
- #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)
- #define TIM_SR_TIF TIM_SR_TIF_Msk
- #define TIM_SR_BIF_Pos (7U)
- #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)
- #define TIM_SR_BIF TIM_SR_BIF_Msk
- #define TIM_SR_CC1OF_Pos (9U)
- #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)
- #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk
- #define TIM_SR_CC2OF_Pos (10U)
- #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)
- #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk
- #define TIM_SR_CC3OF_Pos (11U)
- #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)
- #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk
- #define TIM_SR_CC4OF_Pos (12U)
- #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)
- #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk
- #define TIM_EGR_UG_Pos (0U)
- #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)
- #define TIM_EGR_UG TIM_EGR_UG_Msk
- #define TIM_EGR_CC1G_Pos (1U)
- #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)
- #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk
- #define TIM_EGR_CC2G_Pos (2U)
- #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)
- #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk
- #define TIM_EGR_CC3G_Pos (3U)
- #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)
- #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk
- #define TIM_EGR_CC4G_Pos (4U)
- #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)
- #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk
- #define TIM_EGR_COMG_Pos (5U)
- #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)
- #define TIM_EGR_COMG TIM_EGR_COMG_Msk
- #define TIM_EGR_TG_Pos (6U)
- #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)
- #define TIM_EGR_TG TIM_EGR_TG_Msk
- #define TIM_EGR_BG_Pos (7U)
- #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)
- #define TIM_EGR_BG TIM_EGR_BG_Msk
- #define TIM_CCMR1_CC1S_Pos (0U)
- #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)
- #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk
- #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)
- #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)
- #define TIM_CCMR1_OC1FE_Pos (2U)
- #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)
- #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk
- #define TIM_CCMR1_OC1PE_Pos (3U)
- #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)
- #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk
- #define TIM_CCMR1_OC1M_Pos (4U)
- #define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos)
- #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk
- #define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos)
- #define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos)
- #define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos)
- #define TIM_CCMR1_OC1CE_Pos (7U)
- #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)
- #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk
- #define TIM_CCMR1_CC2S_Pos (8U)
- #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)
- #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk
- #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)
- #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)
- #define TIM_CCMR1_OC2FE_Pos (10U)
- #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)
- #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk
- #define TIM_CCMR1_OC2PE_Pos (11U)
- #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)
- #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk
- #define TIM_CCMR1_OC2M_Pos (12U)
- #define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos)
- #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk
- #define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos)
- #define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos)
- #define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos)
- #define TIM_CCMR1_OC2CE_Pos (15U)
- #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)
- #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk
- #define TIM_CCMR1_IC1PSC_Pos (2U)
- #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)
- #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk
- #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)
- #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)
- #define TIM_CCMR1_IC1F_Pos (4U)
- #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)
- #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk
- #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)
- #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)
- #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)
- #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)
- #define TIM_CCMR1_IC2PSC_Pos (10U)
- #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)
- #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk
- #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)
- #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)
- #define TIM_CCMR1_IC2F_Pos (12U)
- #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)
- #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk
- #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)
- #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)
- #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)
- #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)
- #define TIM_CCMR2_CC3S_Pos (0U)
- #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)
- #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk
- #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)
- #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)
- #define TIM_CCMR2_OC3FE_Pos (2U)
- #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)
- #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk
- #define TIM_CCMR2_OC3PE_Pos (3U)
- #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)
- #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk
- #define TIM_CCMR2_OC3M_Pos (4U)
- #define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos)
- #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk
- #define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos)
- #define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos)
- #define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos)
- #define TIM_CCMR2_OC3CE_Pos (7U)
- #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)
- #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk
- #define TIM_CCMR2_CC4S_Pos (8U)
- #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)
- #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk
- #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)
- #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)
- #define TIM_CCMR2_OC4FE_Pos (10U)
- #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)
- #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk
- #define TIM_CCMR2_OC4PE_Pos (11U)
- #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)
- #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk
- #define TIM_CCMR2_OC4M_Pos (12U)
- #define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos)
- #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk
- #define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos)
- #define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos)
- #define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos)
- #define TIM_CCMR2_OC4CE_Pos (15U)
- #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)
- #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk
- #define TIM_CCMR2_IC3PSC_Pos (2U)
- #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)
- #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk
- #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)
- #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)
- #define TIM_CCMR2_IC3F_Pos (4U)
- #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)
- #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk
- #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)
- #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)
- #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)
- #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)
- #define TIM_CCMR2_IC4PSC_Pos (10U)
- #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)
- #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk
- #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)
- #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)
- #define TIM_CCMR2_IC4F_Pos (12U)
- #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)
- #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk
- #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)
- #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)
- #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)
- #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)
- #define TIM_CCER_CC1E_Pos (0U)
- #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)
- #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk
- #define TIM_CCER_CC1P_Pos (1U)
- #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)
- #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk
- #define TIM_CCER_CC1NE_Pos (2U)
- #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)
- #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk
- #define TIM_CCER_CC1NP_Pos (3U)
- #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)
- #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk
- #define TIM_CCER_CC2E_Pos (4U)
- #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)
- #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk
- #define TIM_CCER_CC2P_Pos (5U)
- #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)
- #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk
- #define TIM_CCER_CC2NE_Pos (6U)
- #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)
- #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk
- #define TIM_CCER_CC2NP_Pos (7U)
- #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)
- #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk
- #define TIM_CCER_CC3E_Pos (8U)
- #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)
- #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk
- #define TIM_CCER_CC3P_Pos (9U)
- #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)
- #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk
- #define TIM_CCER_CC3NE_Pos (10U)
- #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)
- #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk
- #define TIM_CCER_CC3NP_Pos (11U)
- #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)
- #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk
- #define TIM_CCER_CC4E_Pos (12U)
- #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)
- #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk
- #define TIM_CCER_CC4P_Pos (13U)
- #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)
- #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk
- #define TIM_CCER_CC4NP_Pos (15U)
- #define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)
- #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk
- #define TIM_CNT_CNT_Pos (0U)
- #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)
- #define TIM_CNT_CNT TIM_CNT_CNT_Msk
- #define TIM_PSC_PSC_Pos (0U)
- #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)
- #define TIM_PSC_PSC TIM_PSC_PSC_Msk
- #define TIM_ARR_ARR_Pos (0U)
- #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)
- #define TIM_ARR_ARR TIM_ARR_ARR_Msk
- #define TIM_RCR_REP_Pos (0U)
- #define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos)
- #define TIM_RCR_REP TIM_RCR_REP_Msk
- #define TIM_CCR1_CCR1_Pos (0U)
- #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)
- #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk
- #define TIM_CCR2_CCR2_Pos (0U)
- #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)
- #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk
- #define TIM_CCR3_CCR3_Pos (0U)
- #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)
- #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk
- #define TIM_CCR4_CCR4_Pos (0U)
- #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)
- #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk
- #define TIM_BDTR_DTG_Pos (0U)
- #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)
- #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk
- #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)
- #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)
- #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)
- #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)
- #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)
- #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)
- #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)
- #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)
- #define TIM_BDTR_LOCK_Pos (8U)
- #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)
- #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk
- #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)
- #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)
- #define TIM_BDTR_OSSI_Pos (10U)
- #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)
- #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk
- #define TIM_BDTR_OSSR_Pos (11U)
- #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)
- #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk
- #define TIM_BDTR_BKE_Pos (12U)
- #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)
- #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk
- #define TIM_BDTR_BKP_Pos (13U)
- #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)
- #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk
- #define TIM_BDTR_AOE_Pos (14U)
- #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)
- #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk
- #define TIM_BDTR_MOE_Pos (15U)
- #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)
- #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk
- #define TIM_DCR_DBA_Pos (0U)
- #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)
- #define TIM_DCR_DBA TIM_DCR_DBA_Msk
- #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)
- #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)
- #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)
- #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)
- #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)
- #define TIM_DCR_DBL_Pos (8U)
- #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)
- #define TIM_DCR_DBL TIM_DCR_DBL_Msk
- #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)
- #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)
- #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)
- #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)
- #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)
- #define TIM_DMAR_DMAB_Pos (0U)
- #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)
- #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk
- #define TIM14_OR_TI1_RMP_Pos (0U)
- #define TIM14_OR_TI1_RMP_Msk (0x3UL << TIM14_OR_TI1_RMP_Pos)
- #define TIM14_OR_TI1_RMP TIM14_OR_TI1_RMP_Msk
- #define TIM14_OR_TI1_RMP_0 (0x1UL << TIM14_OR_TI1_RMP_Pos)
- #define TIM14_OR_TI1_RMP_1 (0x2UL << TIM14_OR_TI1_RMP_Pos)
- #define USART_CR1_UE_Pos (0U)
- #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)
- #define USART_CR1_UE USART_CR1_UE_Msk
- #define USART_CR1_RE_Pos (2U)
- #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)
- #define USART_CR1_RE USART_CR1_RE_Msk
- #define USART_CR1_TE_Pos (3U)
- #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)
- #define USART_CR1_TE USART_CR1_TE_Msk
- #define USART_CR1_IDLEIE_Pos (4U)
- #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)
- #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk
- #define USART_CR1_RXNEIE_Pos (5U)
- #define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos)
- #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk
- #define USART_CR1_TCIE_Pos (6U)
- #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)
- #define USART_CR1_TCIE USART_CR1_TCIE_Msk
- #define USART_CR1_TXEIE_Pos (7U)
- #define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos)
- #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk
- #define USART_CR1_PEIE_Pos (8U)
- #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)
- #define USART_CR1_PEIE USART_CR1_PEIE_Msk
- #define USART_CR1_PS_Pos (9U)
- #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)
- #define USART_CR1_PS USART_CR1_PS_Msk
- #define USART_CR1_PCE_Pos (10U)
- #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)
- #define USART_CR1_PCE USART_CR1_PCE_Msk
- #define USART_CR1_WAKE_Pos (11U)
- #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)
- #define USART_CR1_WAKE USART_CR1_WAKE_Msk
- #define USART_CR1_M_Pos (12U)
- #define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos)
- #define USART_CR1_M USART_CR1_M_Msk
- #define USART_CR1_MME_Pos (13U)
- #define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos)
- #define USART_CR1_MME USART_CR1_MME_Msk
- #define USART_CR1_CMIE_Pos (14U)
- #define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos)
- #define USART_CR1_CMIE USART_CR1_CMIE_Msk
- #define USART_CR1_OVER8_Pos (15U)
- #define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)
- #define USART_CR1_OVER8 USART_CR1_OVER8_Msk
- #define USART_CR1_DEDT_Pos (16U)
- #define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos)
- #define USART_CR1_DEDT USART_CR1_DEDT_Msk
- #define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos)
- #define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos)
- #define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos)
- #define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos)
- #define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos)
- #define USART_CR1_DEAT_Pos (21U)
- #define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos)
- #define USART_CR1_DEAT USART_CR1_DEAT_Msk
- #define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos)
- #define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos)
- #define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos)
- #define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos)
- #define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos)
- #define USART_CR1_RTOIE_Pos (26U)
- #define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos)
- #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk
- #define USART_CR1_EOBIE_Pos (27U)
- #define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos)
- #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk
- #define USART_CR2_ADDM7_Pos (4U)
- #define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos)
- #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk
- #define USART_CR2_LBCL_Pos (8U)
- #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)
- #define USART_CR2_LBCL USART_CR2_LBCL_Msk
- #define USART_CR2_CPHA_Pos (9U)
- #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)
- #define USART_CR2_CPHA USART_CR2_CPHA_Msk
- #define USART_CR2_CPOL_Pos (10U)
- #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)
- #define USART_CR2_CPOL USART_CR2_CPOL_Msk
- #define USART_CR2_CLKEN_Pos (11U)
- #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)
- #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk
- #define USART_CR2_STOP_Pos (12U)
- #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)
- #define USART_CR2_STOP USART_CR2_STOP_Msk
- #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)
- #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)
- #define USART_CR2_SWAP_Pos (15U)
- #define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos)
- #define USART_CR2_SWAP USART_CR2_SWAP_Msk
- #define USART_CR2_RXINV_Pos (16U)
- #define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos)
- #define USART_CR2_RXINV USART_CR2_RXINV_Msk
- #define USART_CR2_TXINV_Pos (17U)
- #define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos)
- #define USART_CR2_TXINV USART_CR2_TXINV_Msk
- #define USART_CR2_DATAINV_Pos (18U)
- #define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos)
- #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk
- #define USART_CR2_MSBFIRST_Pos (19U)
- #define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos)
- #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk
- #define USART_CR2_ABREN_Pos (20U)
- #define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos)
- #define USART_CR2_ABREN USART_CR2_ABREN_Msk
- #define USART_CR2_ABRMODE_Pos (21U)
- #define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos)
- #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk
- #define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos)
- #define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos)
- #define USART_CR2_RTOEN_Pos (23U)
- #define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos)
- #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk
- #define USART_CR2_ADD_Pos (24U)
- #define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos)
- #define USART_CR2_ADD USART_CR2_ADD_Msk
- #define USART_CR3_EIE_Pos (0U)
- #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)
- #define USART_CR3_EIE USART_CR3_EIE_Msk
- #define USART_CR3_HDSEL_Pos (3U)
- #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)
- #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk
- #define USART_CR3_DMAR_Pos (6U)
- #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)
- #define USART_CR3_DMAR USART_CR3_DMAR_Msk
- #define USART_CR3_DMAT_Pos (7U)
- #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)
- #define USART_CR3_DMAT USART_CR3_DMAT_Msk
- #define USART_CR3_RTSE_Pos (8U)
- #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)
- #define USART_CR3_RTSE USART_CR3_RTSE_Msk
- #define USART_CR3_CTSE_Pos (9U)
- #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)
- #define USART_CR3_CTSE USART_CR3_CTSE_Msk
- #define USART_CR3_CTSIE_Pos (10U)
- #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)
- #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk
- #define USART_CR3_ONEBIT_Pos (11U)
- #define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos)
- #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk
- #define USART_CR3_OVRDIS_Pos (12U)
- #define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos)
- #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk
- #define USART_CR3_DDRE_Pos (13U)
- #define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos)
- #define USART_CR3_DDRE USART_CR3_DDRE_Msk
- #define USART_CR3_DEM_Pos (14U)
- #define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos)
- #define USART_CR3_DEM USART_CR3_DEM_Msk
- #define USART_CR3_DEP_Pos (15U)
- #define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos)
- #define USART_CR3_DEP USART_CR3_DEP_Msk
- #define USART_BRR_DIV_FRACTION_Pos (0U)
- #define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos)
- #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk
- #define USART_BRR_DIV_MANTISSA_Pos (4U)
- #define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)
- #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk
- #define USART_GTPR_PSC_Pos (0U)
- #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)
- #define USART_GTPR_PSC USART_GTPR_PSC_Msk
- #define USART_GTPR_GT_Pos (8U)
- #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)
- #define USART_GTPR_GT USART_GTPR_GT_Msk
- #define USART_RTOR_RTO_Pos (0U)
- #define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos)
- #define USART_RTOR_RTO USART_RTOR_RTO_Msk
- #define USART_RTOR_BLEN_Pos (24U)
- #define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos)
- #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk
- #define USART_RQR_ABRRQ_Pos (0U)
- #define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos)
- #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk
- #define USART_RQR_SBKRQ_Pos (1U)
- #define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos)
- #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk
- #define USART_RQR_MMRQ_Pos (2U)
- #define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos)
- #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk
- #define USART_RQR_RXFRQ_Pos (3U)
- #define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos)
- #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk
- #define USART_ISR_PE_Pos (0U)
- #define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos)
- #define USART_ISR_PE USART_ISR_PE_Msk
- #define USART_ISR_FE_Pos (1U)
- #define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos)
- #define USART_ISR_FE USART_ISR_FE_Msk
- #define USART_ISR_NE_Pos (2U)
- #define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos)
- #define USART_ISR_NE USART_ISR_NE_Msk
- #define USART_ISR_ORE_Pos (3U)
- #define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos)
- #define USART_ISR_ORE USART_ISR_ORE_Msk
- #define USART_ISR_IDLE_Pos (4U)
- #define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos)
- #define USART_ISR_IDLE USART_ISR_IDLE_Msk
- #define USART_ISR_RXNE_Pos (5U)
- #define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos)
- #define USART_ISR_RXNE USART_ISR_RXNE_Msk
- #define USART_ISR_TC_Pos (6U)
- #define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos)
- #define USART_ISR_TC USART_ISR_TC_Msk
- #define USART_ISR_TXE_Pos (7U)
- #define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos)
- #define USART_ISR_TXE USART_ISR_TXE_Msk
- #define USART_ISR_CTSIF_Pos (9U)
- #define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos)
- #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk
- #define USART_ISR_CTS_Pos (10U)
- #define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos)
- #define USART_ISR_CTS USART_ISR_CTS_Msk
- #define USART_ISR_RTOF_Pos (11U)
- #define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos)
- #define USART_ISR_RTOF USART_ISR_RTOF_Msk
- #define USART_ISR_ABRE_Pos (14U)
- #define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos)
- #define USART_ISR_ABRE USART_ISR_ABRE_Msk
- #define USART_ISR_ABRF_Pos (15U)
- #define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos)
- #define USART_ISR_ABRF USART_ISR_ABRF_Msk
- #define USART_ISR_BUSY_Pos (16U)
- #define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos)
- #define USART_ISR_BUSY USART_ISR_BUSY_Msk
- #define USART_ISR_CMF_Pos (17U)
- #define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos)
- #define USART_ISR_CMF USART_ISR_CMF_Msk
- #define USART_ISR_SBKF_Pos (18U)
- #define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos)
- #define USART_ISR_SBKF USART_ISR_SBKF_Msk
- #define USART_ISR_RWU_Pos (19U)
- #define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos)
- #define USART_ISR_RWU USART_ISR_RWU_Msk
- #define USART_ISR_TEACK_Pos (21U)
- #define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos)
- #define USART_ISR_TEACK USART_ISR_TEACK_Msk
- #define USART_ISR_REACK_Pos (22U)
- #define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos)
- #define USART_ISR_REACK USART_ISR_REACK_Msk
- #define USART_ICR_PECF_Pos (0U)
- #define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos)
- #define USART_ICR_PECF USART_ICR_PECF_Msk
- #define USART_ICR_FECF_Pos (1U)
- #define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos)
- #define USART_ICR_FECF USART_ICR_FECF_Msk
- #define USART_ICR_NCF_Pos (2U)
- #define USART_ICR_NCF_Msk (0x1UL << USART_ICR_NCF_Pos)
- #define USART_ICR_NCF USART_ICR_NCF_Msk
- #define USART_ICR_ORECF_Pos (3U)
- #define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos)
- #define USART_ICR_ORECF USART_ICR_ORECF_Msk
- #define USART_ICR_IDLECF_Pos (4U)
- #define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos)
- #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk
- #define USART_ICR_TCCF_Pos (6U)
- #define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos)
- #define USART_ICR_TCCF USART_ICR_TCCF_Msk
- #define USART_ICR_CTSCF_Pos (9U)
- #define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos)
- #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk
- #define USART_ICR_RTOCF_Pos (11U)
- #define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos)
- #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk
- #define USART_ICR_CMCF_Pos (17U)
- #define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos)
- #define USART_ICR_CMCF USART_ICR_CMCF_Msk
- #define USART_RDR_RDR ((uint16_t)0x01FFU)
- #define USART_TDR_TDR ((uint16_t)0x01FFU)
- #define WWDG_CR_T_Pos (0U)
- #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)
- #define WWDG_CR_T WWDG_CR_T_Msk
- #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)
- #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)
- #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)
- #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)
- #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)
- #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)
- #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)
- #define WWDG_CR_T0 WWDG_CR_T_0
- #define WWDG_CR_T1 WWDG_CR_T_1
- #define WWDG_CR_T2 WWDG_CR_T_2
- #define WWDG_CR_T3 WWDG_CR_T_3
- #define WWDG_CR_T4 WWDG_CR_T_4
- #define WWDG_CR_T5 WWDG_CR_T_5
- #define WWDG_CR_T6 WWDG_CR_T_6
- #define WWDG_CR_WDGA_Pos (7U)
- #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)
- #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk
- #define WWDG_CFR_W_Pos (0U)
- #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)
- #define WWDG_CFR_W WWDG_CFR_W_Msk
- #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)
- #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)
- #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)
- #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)
- #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)
- #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)
- #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)
- #define WWDG_CFR_W0 WWDG_CFR_W_0
- #define WWDG_CFR_W1 WWDG_CFR_W_1
- #define WWDG_CFR_W2 WWDG_CFR_W_2
- #define WWDG_CFR_W3 WWDG_CFR_W_3
- #define WWDG_CFR_W4 WWDG_CFR_W_4
- #define WWDG_CFR_W5 WWDG_CFR_W_5
- #define WWDG_CFR_W6 WWDG_CFR_W_6
- #define WWDG_CFR_WDGTB_Pos (7U)
- #define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos)
- #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk
- #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)
- #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)
- #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
- #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
- #define WWDG_CFR_EWI_Pos (9U)
- #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)
- #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk
- #define WWDG_SR_EWIF_Pos (0U)
- #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)
- #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk
-
- #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
- #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
- #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
- #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
- ((INSTANCE) == DMA1_Channel2) || \
- ((INSTANCE) == DMA1_Channel3) || \
- ((INSTANCE) == DMA1_Channel4) || \
- ((INSTANCE) == DMA1_Channel5))
- #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
- ((INSTANCE) == GPIOB) || \
- ((INSTANCE) == GPIOC) || \
- ((INSTANCE) == GPIOD) || \
- ((INSTANCE) == GPIOF))
- #define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
- ((INSTANCE) == GPIOB) || \
- ((INSTANCE) == GPIOF))
- #define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
- ((INSTANCE) == GPIOB))
- #define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
- #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
- #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
- #define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
- #define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
- #define IS_TIM_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM14) || \
- ((INSTANCE) == TIM16) || \
- ((INSTANCE) == TIM17))
- #define IS_TIM_CC1_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM14) || \
- ((INSTANCE) == TIM16) || \
- ((INSTANCE) == TIM17))
- #define IS_TIM_CC2_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM3))
- #define IS_TIM_CC3_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM3))
- #define IS_TIM_CC4_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM3))
- #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM3))
- #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM3))
- #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM3))
- #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM3))
- #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM3))
- #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM3))
- #define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1))
-
- #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1))
- #define IS_TIM_XOR_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM3))
- #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM3))
- #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM3))
- #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (0)
- #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM16) || \
- ((INSTANCE) == TIM17))
- #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM16) || \
- ((INSTANCE) == TIM17))
- #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
- ((((INSTANCE) == TIM1) && \
- (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2) || \
- ((CHANNEL) == TIM_CHANNEL_3) || \
- ((CHANNEL) == TIM_CHANNEL_4))) \
- || \
- (((INSTANCE) == TIM3) && \
- (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2) || \
- ((CHANNEL) == TIM_CHANNEL_3) || \
- ((CHANNEL) == TIM_CHANNEL_4))) \
- || \
- (((INSTANCE) == TIM14) && \
- (((CHANNEL) == TIM_CHANNEL_1))) \
- || \
- (((INSTANCE) == TIM16) && \
- (((CHANNEL) == TIM_CHANNEL_1))) \
- || \
- (((INSTANCE) == TIM17) && \
- (((CHANNEL) == TIM_CHANNEL_1))))
- #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
- ((((INSTANCE) == TIM1) && \
- (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2) || \
- ((CHANNEL) == TIM_CHANNEL_3))) \
- || \
- (((INSTANCE) == TIM16) && \
- ((CHANNEL) == TIM_CHANNEL_1)) \
- || \
- (((INSTANCE) == TIM17) && \
- ((CHANNEL) == TIM_CHANNEL_1)))
- #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM3))
- #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM16) || \
- ((INSTANCE) == TIM17))
- #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM14) || \
- ((INSTANCE) == TIM16) || \
- ((INSTANCE) == TIM17))
- #define IS_TIM_DMA_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM16) || \
- ((INSTANCE) == TIM17))
-
- #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM16) || \
- ((INSTANCE) == TIM17))
-
- #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM16) || \
- ((INSTANCE) == TIM17))
- #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
- ((INSTANCE) == TIM14)
- #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
- ((INSTANCE) == TIM1)
- #define IS_USART_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
-
-
- #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
-
- #define IS_UART_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
- #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
- #define IS_UART_HWFLOW_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
- #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
- #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
- #define ADC1_COMP_IRQn ADC1_IRQn
- #define DMA1_Ch1_IRQn DMA1_Channel1_IRQn
- #define DMA1_Ch2_3_DMA2_Ch1_2_IRQn DMA1_Channel2_3_IRQn
- #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
- #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn
- #define RCC_CRS_IRQn RCC_IRQn
- #define ADC1_COMP_IRQHandler ADC1_IRQHandler
- #define DMA1_Ch1_IRQHandler DMA1_Channel1_IRQHandler
- #define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler DMA1_Channel2_3_IRQHandler
- #define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler
- #define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_IRQHandler
- #define RCC_CRS_IRQHandler RCC_IRQHandler
- #ifdef __cplusplus
- }
- #endif
- #endif
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