Accum-Tester/board/board_LGDP4532.h

/*
 * This file is subject to the terms of the GFX License. If a copy of
 * the license was not distributed with this file, you can obtain one at:
 *
 *              http://ugfx.org/license.html
 */

/*
	driver quickly hacked together from a chinese sourcecode that came
	with the board and existing ili9320 code by Chris van Dongen (sjaak)
	(sjaak2002 at msn.com)
	
	Also added rotation for 180 and 270 degrees and minor tweaks to
	setcursor
	
	Added code comes without warranty and free bugs. Feel free to use 
	or misuse the added code :D
*/


/**
 * @file    boards/addons/gdisp/board_ILI9325_hy_stm32_100p.h
 * @brief   GDISP Graphic Driver subsystem board SPI interface for the ILI9325 display.
 *
 * @note	This file contains a mix of hardware specific and operating system specific
 *			code. You will need to change it for your CPU and/or operating system.
 */

#ifndef GDISP_LLD_BOARD_H
#define GDISP_LLD_BOARD_H

// For a multiple display configuration we would put all this in a structure and then
//	set g->board to that structure.
#define GDISP_REG              (*((volatile uint16_t *) 0x60000000)) /* RS = 0 */
#define GDISP_RAM              (*((volatile uint16_t *) 0x60020000)) /* RS = 1 */

static inline void init_board(GDisplay *g) {

	(void) g;
	// As we are not using multiple displays we set g->board to NULL as we don't use it.

	/* FSMC setup for F1 */
	rccEnableAHB(RCC_AHBENR_FSMCEN, 0);

	/* set pin modes. by default sets in board files */
/*	IOBus busD = {GPIOD, PAL_WHOLE_PORT, 0};
	IOBus busE = {GPIOE, PAL_WHOLE_PORT, 0};
	palSetBusMode(&busD, PAL_MODE_STM32_ALTERNATE_PUSHPULL);
	palSetBusMode(&busE, PAL_MODE_STM32_ALTERNATE_PUSHPULL);
	palSetPadMode(GPIOE, GPIOE_TFT_RST, PAL_MODE_OUTPUT_PUSHPULL);
	palSetPadMode(GPIOD, GPIOD_TFT_LIGHT, PAL_MODE_OUTPUT_PUSHPULL);
*/

  const uint8_t FSMC_Bank = 0x0;

  /* Bank1 NOR/SRAM control register configuration */ 
  // FSMC_MemoryType_NOR | FSMC_MemoryDataWidth_16b | FSMC_WriteOperation_Enable
  FSMC_Bank1->BTCR[FSMC_Bank] = (uint32_t)(0x8 | 0x10 | 0x1000);

  // if FSMC_MemoryType_NOR
  FSMC_Bank1->BTCR[FSMC_Bank] |= ((uint32_t)0x00000040);
  
  /* Bank1 NOR/SRAM timing register configuration */
  // AddressSetupTime | DataSetupTime | FSMC_AccessMode_B
  FSMC_Bank1->BTCR[FSMC_Bank+1] = (uint32_t)(0x2 | (0x5 << 8) | 0x10000000);

  /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
  FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;

  /* Enable FSMC Bank1_SRAM Bank */
  FSMC_Bank1->BTCR[FSMC_Bank] |= 0x1;
}

static inline void post_init_board(GDisplay *g) {
	(void) g;
}

static inline void setpin_reset(GDisplay *g, bool_t state) {
	(void) g;
	if(state)
		palClearPad(GPIOE, GPIOE_TFT_RST);
	else
		palSetPad(GPIOE, GPIOE_TFT_RST);
}

static inline void set_backlight(GDisplay *g, uint8_t percent) {
	(void) g;
	(void)percent;
}

static inline void gdisp_lld_backlight(GDisplay *g, uint8_t percent) {
	(void) g;
	(void)percent;
}

static inline void acquire_bus(GDisplay *g) {
	(void) g;
}

static inline void release_bus(GDisplay *g) {
	(void) g;
}

static inline void write_index(GDisplay *g, uint16_t index) {
	(void) g;
	GDISP_REG = index;
}

static inline void write_data(GDisplay *g, uint16_t data) {
	(void) g;
	GDISP_RAM = data;
}

static inline void setreadmode(GDisplay *g) {
	(void) g;
}

static inline void setwritemode(GDisplay *g) {
	(void) g;
}

static inline uint16_t read_data(GDisplay *g) {
	(void) g;
	return GDISP_RAM;
}

#endif /* GDISP_LLD_BOARD_H */