Accum-Tester/board/board_ILI9341.h

/*
 * This file is subject to the terms of the GFX License. If a copy of
 * the license was not distributed with this file, you can obtain one at:
 *
 *              http://ugfx.io/license.html
 */

/**
 * @file    boards/addons/gdisp/board_ILI9341_stm32f4xx.h
 * @brief   GDISP Graphic Driver subsystem board SPI interface for the ILI9341 display.
 *
 * @note  This file contains a mix of hardware specific and operating system specific
 *      code. You will need to change it for your CPU and/or operating system.
 */

#ifndef _GDISP_LLD_BOARD_H
#define _GDISP_LLD_BOARD_H

// For a multiple display configuration we would put all this in a structure and then
//  set g->board to that structure.

// Use Bank1.sector4 of NOR/SRAM, address bit HADDR[27,26]=11
// A6 as data command distinguishing line
// Note that STM32 will be shifted to the right by one bit during setting! 111 1110=0x7E
#define GDISP_REG              (*((volatile uint16_t *) 0x6C000000)) /* RS = 0 */
#define GDISP_RAM              (*((volatile uint16_t *) 0x6C000080)) /* RS = 1 */

#ifdef USE_BL_PWM
/* PWM configuration structure. We use timer 12 channel 1 */
static const PWMConfig pwmcfg = {
  100000,       /* 100 kHz PWM clock frequency. */
  100,          /* PWM period is 100 cycles. */
  0,
  {
    {PWM_OUTPUT_ACTIVE_LOW, 0},
    {PWM_OUTPUT_DISABLED, 0},
    {PWM_OUTPUT_DISABLED, 0},
    {PWM_OUTPUT_DISABLED, 0}
  },
  0,
  0
};
#endif // USE_BL_PWM

static GFXINLINE void init_board(GDisplay *g) {
  (void) g;
  // As we are not using multiple displays we set g->board to NULL as we don't use it.

  /* GPIO setup done by board.h */

  /* FSMC setup for F4 */
  rccEnableAHB3(RCC_AHB3ENR_FSMCEN, 0);
/*** ADD DMA support!!!! */
  const unsigned char FSMC_Bank = 0x06; // FSMC_NE4

  /** From china driver */
  /* Bank1 NOR/SRAM control register configuration */
  // FSMC_MemoryDataWidth_16b | FSMC_WriteOperation_Enable | FSMC_ExtendedMode_Enable
  FSMC_Bank1->BTCR[FSMC_Bank] = (uint32_t)(0x10 | 0x1000 | 0x4000);

  /* Bank1 NOR/SRAM timing register configuration */
  // Address setup time (ADDSET) is 16 HCLK 1/168M=6ns*16=96ns
  // Data save time is 25 HCLK = 6*25 = 150ns
  FSMC_Bank1->BTCR[FSMC_Bank+1] = (uint32_t)(0x0F | (0x18 << 8));

  /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
  // Address setup time (ADDSET) is 8 HCLK = 48ns
  // Data save time is 6ns*9 HCLK = 54ns
  //FSMC_Bank1E->BWTR[FSMC_Bank] = (uint32_t)(0x08 | (0x08 << 8));
  /* ILI9341 can WR fastes: */
  //FSMC_Bank1E->BWTR[FSMC_Bank]&=~(0XF<<0);	//Address setup time (ADDSET) is cleared
  //FSMC_Bank1E->BWTR[FSMC_Bank]&=~(0XF<<8);	//Data storage time is cleared
  //FSMC_Bank1E->BWTR[FSMC_Bank] |=3<<0;  //Address setup time (ADDSET) is 3 HCLK = 18ns
  //FSMC_Bank1E->BWTR[FSMC_Bank] |=2<<8;  //Data storage time is 6ns*3 HCLK=18ns
  FSMC_Bank1E->BWTR[FSMC_Bank] = (uint32_t)((3 << 0) | (2 <<8 ));

  /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
  FSMC_Bank1->BTCR[FSMC_Bank] |= 0x01;

#ifdef USE_BL_PWM
  /* Display backlight control */
  /* TIM12 is an alternate function 9 (AF9) */
  pwmStart(&PWMD12, &pwmcfg);
  palSetPadMode(GPIOB, 15, PAL_MODE_ALTERNATE(9));
  pwmEnableChannel(&PWMD12, 0, 100);
#endif // USE_BL_PWM
}

static GFXINLINE void post_init_board(GDisplay *g) {
  (void) g;
}

static GFXINLINE void setpin_reset(GDisplay *g, gBool state) {
  (void) g;
  (void) state;
}

static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
  (void) g;
#ifdef USE_BL_PWM
  pwmEnableChannel(&PWMD12, 0, percent);
#else
  if (percent) {
    palClearLine(LINE_LCD_BL); // PNP transistor
  } else {
    palSetLine(LINE_LCD_BL);
  }
#endif // USE_BL_PWM
}

static GFXINLINE void acquire_bus(GDisplay *g) {
  (void) g;
}

static GFXINLINE void release_bus(GDisplay *g) {
  (void) g;
}

static GFXINLINE void write_index(GDisplay *g, gU16 index) {
  (void) g;
  GDISP_REG = index;
}

static GFXINLINE void write_data(GDisplay *g, gU16 data) {
  (void) g;
  GDISP_RAM = (data | (data<<8));
}

static GFXINLINE void setreadmode(GDisplay *g) {
  (void) g;
}

static GFXINLINE void setwritemode(GDisplay *g) {
  (void) g;
}

static GFXINLINE gU16 read_data(GDisplay *g) {
  (void) g;
  return GDISP_RAM;
}

#endif /* _GDISP_LLD_BOARD_H */